diff options
author | Andrew Vasquez <andrew.vasquez@qlogic.com> | 2005-11-08 17:37:48 -0500 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.(none)> | 2005-11-09 16:19:23 -0500 |
commit | 335a1cc976ffbb58491a9b6dc58955349e3f0388 (patch) | |
tree | 8a5fd35e3cbd278bccd34b241ef5c99d6ea477a6 /drivers/scsi | |
parent | 8d5708f3b5ea0765af92a79ebc4144c91718e695 (diff) |
[SCSI] qla2xxx: Correct ISP24xx soft-reset handling.
A driver must wait 100us before attempting an MMIO operation
to the RISC after a soft-reset has been initiated. A
similar delay was needed with earlier ISPs.
Note: a PCI config-space read is used to flush the MMIO
write to the ISP, since the ISP's state machines are unable
to respond to any MMIO read during the reset process.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 8 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_init.c | 7 |
2 files changed, 8 insertions, 7 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 89793c1c06b1..5c5d2315cfab 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c | |||
@@ -970,7 +970,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |||
970 | int rval; | 970 | int rval; |
971 | uint32_t cnt, timer; | 971 | uint32_t cnt, timer; |
972 | uint32_t risc_address; | 972 | uint32_t risc_address; |
973 | uint16_t mb[4]; | 973 | uint16_t mb[4], wd; |
974 | 974 | ||
975 | uint32_t stat; | 975 | uint32_t stat; |
976 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 976 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
@@ -1514,10 +1514,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |||
1514 | 1514 | ||
1515 | WRT_REG_DWORD(®->ctrl_status, | 1515 | WRT_REG_DWORD(®->ctrl_status, |
1516 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | 1516 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); |
1517 | RD_REG_DWORD(®->ctrl_status); | 1517 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
1518 | 1518 | ||
1519 | udelay(100); | ||
1519 | /* Wait for firmware to complete NVRAM accesses. */ | 1520 | /* Wait for firmware to complete NVRAM accesses. */ |
1520 | udelay(5); | ||
1521 | mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); | 1521 | mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); |
1522 | for (cnt = 10000 ; cnt && mb[0]; cnt--) { | 1522 | for (cnt = 10000 ; cnt && mb[0]; cnt--) { |
1523 | udelay(5); | 1523 | udelay(5); |
@@ -1525,7 +1525,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |||
1525 | barrier(); | 1525 | barrier(); |
1526 | } | 1526 | } |
1527 | 1527 | ||
1528 | udelay(20); | 1528 | /* Wait for soft-reset to complete. */ |
1529 | for (cnt = 0; cnt < 30000; cnt++) { | 1529 | for (cnt = 0; cnt < 30000; cnt++) { |
1530 | if ((RD_REG_DWORD(®->ctrl_status) & | 1530 | if ((RD_REG_DWORD(®->ctrl_status) & |
1531 | CSRX_ISP_SOFT_RESET) == 0) | 1531 | CSRX_ISP_SOFT_RESET) == 0) |
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index 8fb084b706e0..2d720121a0d3 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c | |||
@@ -567,6 +567,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) | |||
567 | unsigned long flags = 0; | 567 | unsigned long flags = 0; |
568 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 568 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
569 | uint32_t cnt, d2; | 569 | uint32_t cnt, d2; |
570 | uint16_t wd; | ||
570 | 571 | ||
571 | spin_lock_irqsave(&ha->hardware_lock, flags); | 572 | spin_lock_irqsave(&ha->hardware_lock, flags); |
572 | 573 | ||
@@ -581,10 +582,10 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) | |||
581 | 582 | ||
582 | WRT_REG_DWORD(®->ctrl_status, | 583 | WRT_REG_DWORD(®->ctrl_status, |
583 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | 584 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); |
584 | RD_REG_DWORD(®->ctrl_status); | 585 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
585 | 586 | ||
587 | udelay(100); | ||
586 | /* Wait for firmware to complete NVRAM accesses. */ | 588 | /* Wait for firmware to complete NVRAM accesses. */ |
587 | udelay(5); | ||
588 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | 589 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); |
589 | for (cnt = 10000 ; cnt && d2; cnt--) { | 590 | for (cnt = 10000 ; cnt && d2; cnt--) { |
590 | udelay(5); | 591 | udelay(5); |
@@ -592,7 +593,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) | |||
592 | barrier(); | 593 | barrier(); |
593 | } | 594 | } |
594 | 595 | ||
595 | udelay(20); | 596 | /* Wait for soft-reset to complete. */ |
596 | d2 = RD_REG_DWORD(®->ctrl_status); | 597 | d2 = RD_REG_DWORD(®->ctrl_status); |
597 | for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { | 598 | for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { |
598 | udelay(5); | 599 | udelay(5); |