aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/scsi
diff options
context:
space:
mode:
authorTejun Heo <htejun@gmail.com>2005-11-18 00:09:05 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-11-18 13:11:39 -0500
commit7d1ce682d08625258524d23ef5eb9e7ae261c1d0 (patch)
treec089afbea310f50e0e869610573125bbe3377300 /drivers/scsi
parentfc71fe40d2bedcc57d3406bf2050481f8b3441b6 (diff)
[PATCH] sil24: add sil24_restart_controller
When an error condition is raised by device via D2H FIS or SDB. sil24 controller should be restarted by setting PORT_CS_INIT and waiting until PORT_CS_RDY is asserted instead of resetting the controller. This patch implements sil24_restart_controller for those cases. This patch also makes sure that PORT_CS_RDY is asserted on sil24_reset_controller completion. Signed-off-by: Tejun Heo <htejun@gmail.com> -- Jeff, delay is reduced to 1us and cnt increased to 10k. My sil3124 turns on PORT_CS_RDY on the second iteration even without any delay. I think 10k * 1us should be more than enough. I tried to convert both restart and reset to use msleep's with work queue, but if we do that, host_set lock should be released after initiating restart or reset, leading to race condition among reset/restart, other interrupts and timeout. Implementing synchronization among those in low-level driver doesn't seem right. Well, reduced timeout should work for the time being. Thanks. Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/sata_sil24.c35
1 files changed, 32 insertions, 3 deletions
diff --git a/drivers/scsi/sata_sil24.c b/drivers/scsi/sata_sil24.c
index cb1933a3bd55..a6836a07a9eb 100644
--- a/drivers/scsi/sata_sil24.c
+++ b/drivers/scsi/sata_sil24.c
@@ -486,6 +486,31 @@ static void sil24_irq_clear(struct ata_port *ap)
486 /* unused */ 486 /* unused */
487} 487}
488 488
489static int __sil24_restart_controller(void __iomem *port)
490{
491 u32 tmp;
492 int cnt;
493
494 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
495
496 /* Max ~10ms */
497 for (cnt = 0; cnt < 10000; cnt++) {
498 tmp = readl(port + PORT_CTRL_STAT);
499 if (tmp & PORT_CS_RDY)
500 return 0;
501 udelay(1);
502 }
503
504 return -1;
505}
506
507static void sil24_restart_controller(struct ata_port *ap)
508{
509 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
510 printk(KERN_ERR DRV_NAME
511 " ata%u: failed to restart controller\n", ap->id);
512}
513
489static int __sil24_reset_controller(void __iomem *port) 514static int __sil24_reset_controller(void __iomem *port)
490{ 515{
491 int cnt; 516 int cnt;
@@ -505,7 +530,11 @@ static int __sil24_reset_controller(void __iomem *port)
505 530
506 if (tmp & PORT_CS_DEV_RST) 531 if (tmp & PORT_CS_DEV_RST)
507 return -1; 532 return -1;
508 return 0; 533
534 if (tmp & PORT_CS_RDY)
535 return 0;
536
537 return __sil24_restart_controller(port);
509} 538}
510 539
511static void sil24_reset_controller(struct ata_port *ap) 540static void sil24_reset_controller(struct ata_port *ap)
@@ -577,6 +606,7 @@ static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
577 */ 606 */
578 sil24_update_tf(ap); 607 sil24_update_tf(ap);
579 err_mask = ac_err_mask(pp->tf.command); 608 err_mask = ac_err_mask(pp->tf.command);
609 sil24_restart_controller(ap);
580 } else { 610 } else {
581 /* 611 /*
582 * Other errors. libata currently doesn't have any 612 * Other errors. libata currently doesn't have any
@@ -584,12 +614,11 @@ static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
584 * ATA_ERR. 614 * ATA_ERR.
585 */ 615 */
586 err_mask = AC_ERR_OTHER; 616 err_mask = AC_ERR_OTHER;
617 sil24_reset_controller(ap);
587 } 618 }
588 619
589 if (qc) 620 if (qc)
590 ata_qc_complete(qc, err_mask); 621 ata_qc_complete(qc, err_mask);
591
592 sil24_reset_controller(ap);
593} 622}
594 623
595static inline void sil24_host_intr(struct ata_port *ap) 624static inline void sil24_host_intr(struct ata_port *ap)