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authorMatthew Wilcox <matthew@wil.cx>2005-12-16 12:50:53 -0500
committerJames Bottomley <jejb@mulgrave.(none)>2005-12-16 13:53:47 -0500
commit19c65091c133a98b20d867c94b1b1380a79e4b81 (patch)
tree03076a960278b81e26437f2acb0f24cc4f7fe039 /drivers/scsi
parentcd453c6353ea30171d966fd1dd87c37b05bccee1 (diff)
[SCSI] Merge sym53c8xx_comm.h and sym53c8xx_defs.h into ncr driver
When the sym1 driver was in the tree, it used to share various parts of its infrastructure with the ncr driver. Now it's gone, these files are just an annoyance, so merge sym53c8xx_comm.h into ncr53c8xx.c and merge sym53c8xx_defs.h into ncr53c8xx.h. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/ncr53c8xx.c734
-rw-r--r--drivers/scsi/ncr53c8xx.h1263
-rw-r--r--drivers/scsi/sym53c8xx_comm.h792
-rw-r--r--drivers/scsi/sym53c8xx_defs.h1320
4 files changed, 1995 insertions, 2114 deletions
diff --git a/drivers/scsi/ncr53c8xx.c b/drivers/scsi/ncr53c8xx.c
index 8e1c77c81f6c..32350707b940 100644
--- a/drivers/scsi/ncr53c8xx.c
+++ b/drivers/scsi/ncr53c8xx.c
@@ -131,7 +131,739 @@
131#define NAME53C "ncr53c" 131#define NAME53C "ncr53c"
132#define NAME53C8XX "ncr53c8xx" 132#define NAME53C8XX "ncr53c8xx"
133 133
134#include "sym53c8xx_comm.h" 134
135/*==========================================================
136**
137** Debugging tags
138**
139**==========================================================
140*/
141
142#define DEBUG_ALLOC (0x0001)
143#define DEBUG_PHASE (0x0002)
144#define DEBUG_QUEUE (0x0008)
145#define DEBUG_RESULT (0x0010)
146#define DEBUG_POINTER (0x0020)
147#define DEBUG_SCRIPT (0x0040)
148#define DEBUG_TINY (0x0080)
149#define DEBUG_TIMING (0x0100)
150#define DEBUG_NEGO (0x0200)
151#define DEBUG_TAGS (0x0400)
152#define DEBUG_SCATTER (0x0800)
153#define DEBUG_IC (0x1000)
154
155/*
156** Enable/Disable debug messages.
157** Can be changed at runtime too.
158*/
159
160#ifdef SCSI_NCR_DEBUG_INFO_SUPPORT
161static int ncr_debug = SCSI_NCR_DEBUG_FLAGS;
162 #define DEBUG_FLAGS ncr_debug
163#else
164 #define DEBUG_FLAGS SCSI_NCR_DEBUG_FLAGS
165#endif
166
167static inline struct list_head *ncr_list_pop(struct list_head *head)
168{
169 if (!list_empty(head)) {
170 struct list_head *elem = head->next;
171
172 list_del(elem);
173 return elem;
174 }
175
176 return NULL;
177}
178
179/*==========================================================
180**
181** Simple power of two buddy-like allocator.
182**
183** This simple code is not intended to be fast, but to
184** provide power of 2 aligned memory allocations.
185** Since the SCRIPTS processor only supplies 8 bit
186** arithmetic, this allocator allows simple and fast
187** address calculations from the SCRIPTS code.
188** In addition, cache line alignment is guaranteed for
189** power of 2 cache line size.
190** Enhanced in linux-2.3.44 to provide a memory pool
191** per pcidev to support dynamic dma mapping. (I would
192** have preferred a real bus astraction, btw).
193**
194**==========================================================
195*/
196
197#define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
198#if PAGE_SIZE >= 8192
199#define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
200#else
201#define MEMO_PAGE_ORDER 1 /* 2 PAGES maximum */
202#endif
203#define MEMO_FREE_UNUSED /* Free unused pages immediately */
204#define MEMO_WARN 1
205#define MEMO_GFP_FLAGS GFP_ATOMIC
206#define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
207#define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
208#define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
209
210typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
211typedef struct device *m_bush_t; /* Something that addresses DMAable */
212
213typedef struct m_link { /* Link between free memory chunks */
214 struct m_link *next;
215} m_link_s;
216
217typedef struct m_vtob { /* Virtual to Bus address translation */
218 struct m_vtob *next;
219 m_addr_t vaddr;
220 m_addr_t baddr;
221} m_vtob_s;
222#define VTOB_HASH_SHIFT 5
223#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
224#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
225#define VTOB_HASH_CODE(m) \
226 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
227
228typedef struct m_pool { /* Memory pool of a given kind */
229 m_bush_t bush;
230 m_addr_t (*getp)(struct m_pool *);
231 void (*freep)(struct m_pool *, m_addr_t);
232 int nump;
233 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
234 struct m_pool *next;
235 struct m_link h[PAGE_SHIFT-MEMO_SHIFT+MEMO_PAGE_ORDER+1];
236} m_pool_s;
237
238static void *___m_alloc(m_pool_s *mp, int size)
239{
240 int i = 0;
241 int s = (1 << MEMO_SHIFT);
242 int j;
243 m_addr_t a;
244 m_link_s *h = mp->h;
245
246 if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
247 return NULL;
248
249 while (size > s) {
250 s <<= 1;
251 ++i;
252 }
253
254 j = i;
255 while (!h[j].next) {
256 if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
257 h[j].next = (m_link_s *)mp->getp(mp);
258 if (h[j].next)
259 h[j].next->next = NULL;
260 break;
261 }
262 ++j;
263 s <<= 1;
264 }
265 a = (m_addr_t) h[j].next;
266 if (a) {
267 h[j].next = h[j].next->next;
268 while (j > i) {
269 j -= 1;
270 s >>= 1;
271 h[j].next = (m_link_s *) (a+s);
272 h[j].next->next = NULL;
273 }
274 }
275#ifdef DEBUG
276 printk("___m_alloc(%d) = %p\n", size, (void *) a);
277#endif
278 return (void *) a;
279}
280
281static void ___m_free(m_pool_s *mp, void *ptr, int size)
282{
283 int i = 0;
284 int s = (1 << MEMO_SHIFT);
285 m_link_s *q;
286 m_addr_t a, b;
287 m_link_s *h = mp->h;
288
289#ifdef DEBUG
290 printk("___m_free(%p, %d)\n", ptr, size);
291#endif
292
293 if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
294 return;
295
296 while (size > s) {
297 s <<= 1;
298 ++i;
299 }
300
301 a = (m_addr_t) ptr;
302
303 while (1) {
304#ifdef MEMO_FREE_UNUSED
305 if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
306 mp->freep(mp, a);
307 break;
308 }
309#endif
310 b = a ^ s;
311 q = &h[i];
312 while (q->next && q->next != (m_link_s *) b) {
313 q = q->next;
314 }
315 if (!q->next) {
316 ((m_link_s *) a)->next = h[i].next;
317 h[i].next = (m_link_s *) a;
318 break;
319 }
320 q->next = q->next->next;
321 a = a & b;
322 s <<= 1;
323 ++i;
324 }
325}
326
327static DEFINE_SPINLOCK(ncr53c8xx_lock);
328
329static void *__m_calloc2(m_pool_s *mp, int size, char *name, int uflags)
330{
331 void *p;
332
333 p = ___m_alloc(mp, size);
334
335 if (DEBUG_FLAGS & DEBUG_ALLOC)
336 printk ("new %-10s[%4d] @%p.\n", name, size, p);
337
338 if (p)
339 memset(p, 0, size);
340 else if (uflags & MEMO_WARN)
341 printk (NAME53C8XX ": failed to allocate %s[%d]\n", name, size);
342
343 return p;
344}
345
346#define __m_calloc(mp, s, n) __m_calloc2(mp, s, n, MEMO_WARN)
347
348static void __m_free(m_pool_s *mp, void *ptr, int size, char *name)
349{
350 if (DEBUG_FLAGS & DEBUG_ALLOC)
351 printk ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
352
353 ___m_free(mp, ptr, size);
354
355}
356
357/*
358 * With pci bus iommu support, we use a default pool of unmapped memory
359 * for memory we donnot need to DMA from/to and one pool per pcidev for
360 * memory accessed by the PCI chip. `mp0' is the default not DMAable pool.
361 */
362
363static m_addr_t ___mp0_getp(m_pool_s *mp)
364{
365 m_addr_t m = __get_free_pages(MEMO_GFP_FLAGS, MEMO_PAGE_ORDER);
366 if (m)
367 ++mp->nump;
368 return m;
369}
370
371static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
372{
373 free_pages(m, MEMO_PAGE_ORDER);
374 --mp->nump;
375}
376
377static m_pool_s mp0 = {NULL, ___mp0_getp, ___mp0_freep};
378
379/*
380 * DMAable pools.
381 */
382
383/*
384 * With pci bus iommu support, we maintain one pool per pcidev and a
385 * hashed reverse table for virtual to bus physical address translations.
386 */
387static m_addr_t ___dma_getp(m_pool_s *mp)
388{
389 m_addr_t vp;
390 m_vtob_s *vbp;
391
392 vbp = __m_calloc(&mp0, sizeof(*vbp), "VTOB");
393 if (vbp) {
394 dma_addr_t daddr;
395 vp = (m_addr_t) dma_alloc_coherent(mp->bush,
396 PAGE_SIZE<<MEMO_PAGE_ORDER,
397 &daddr, GFP_ATOMIC);
398 if (vp) {
399 int hc = VTOB_HASH_CODE(vp);
400 vbp->vaddr = vp;
401 vbp->baddr = daddr;
402 vbp->next = mp->vtob[hc];
403 mp->vtob[hc] = vbp;
404 ++mp->nump;
405 return vp;
406 }
407 }
408 if (vbp)
409 __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
410 return 0;
411}
412
413static void ___dma_freep(m_pool_s *mp, m_addr_t m)
414{
415 m_vtob_s **vbpp, *vbp;
416 int hc = VTOB_HASH_CODE(m);
417
418 vbpp = &mp->vtob[hc];
419 while (*vbpp && (*vbpp)->vaddr != m)
420 vbpp = &(*vbpp)->next;
421 if (*vbpp) {
422 vbp = *vbpp;
423 *vbpp = (*vbpp)->next;
424 dma_free_coherent(mp->bush, PAGE_SIZE<<MEMO_PAGE_ORDER,
425 (void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
426 __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
427 --mp->nump;
428 }
429}
430
431static inline m_pool_s *___get_dma_pool(m_bush_t bush)
432{
433 m_pool_s *mp;
434 for (mp = mp0.next; mp && mp->bush != bush; mp = mp->next);
435 return mp;
436}
437
438static m_pool_s *___cre_dma_pool(m_bush_t bush)
439{
440 m_pool_s *mp;
441 mp = __m_calloc(&mp0, sizeof(*mp), "MPOOL");
442 if (mp) {
443 memset(mp, 0, sizeof(*mp));
444 mp->bush = bush;
445 mp->getp = ___dma_getp;
446 mp->freep = ___dma_freep;
447 mp->next = mp0.next;
448 mp0.next = mp;
449 }
450 return mp;
451}
452
453static void ___del_dma_pool(m_pool_s *p)
454{
455 struct m_pool **pp = &mp0.next;
456
457 while (*pp && *pp != p)
458 pp = &(*pp)->next;
459 if (*pp) {
460 *pp = (*pp)->next;
461 __m_free(&mp0, p, sizeof(*p), "MPOOL");
462 }
463}
464
465static void *__m_calloc_dma(m_bush_t bush, int size, char *name)
466{
467 u_long flags;
468 struct m_pool *mp;
469 void *m = NULL;
470
471 spin_lock_irqsave(&ncr53c8xx_lock, flags);
472 mp = ___get_dma_pool(bush);
473 if (!mp)
474 mp = ___cre_dma_pool(bush);
475 if (mp)
476 m = __m_calloc(mp, size, name);
477 if (mp && !mp->nump)
478 ___del_dma_pool(mp);
479 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
480
481 return m;
482}
483
484static void __m_free_dma(m_bush_t bush, void *m, int size, char *name)
485{
486 u_long flags;
487 struct m_pool *mp;
488
489 spin_lock_irqsave(&ncr53c8xx_lock, flags);
490 mp = ___get_dma_pool(bush);
491 if (mp)
492 __m_free(mp, m, size, name);
493 if (mp && !mp->nump)
494 ___del_dma_pool(mp);
495 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
496}
497
498static m_addr_t __vtobus(m_bush_t bush, void *m)
499{
500 u_long flags;
501 m_pool_s *mp;
502 int hc = VTOB_HASH_CODE(m);
503 m_vtob_s *vp = NULL;
504 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
505
506 spin_lock_irqsave(&ncr53c8xx_lock, flags);
507 mp = ___get_dma_pool(bush);
508 if (mp) {
509 vp = mp->vtob[hc];
510 while (vp && (m_addr_t) vp->vaddr != a)
511 vp = vp->next;
512 }
513 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
514 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
515}
516
517#define _m_calloc_dma(np, s, n) __m_calloc_dma(np->dev, s, n)
518#define _m_free_dma(np, p, s, n) __m_free_dma(np->dev, p, s, n)
519#define m_calloc_dma(s, n) _m_calloc_dma(np, s, n)
520#define m_free_dma(p, s, n) _m_free_dma(np, p, s, n)
521#define _vtobus(np, p) __vtobus(np->dev, p)
522#define vtobus(p) _vtobus(np, p)
523
524/*
525 * Deal with DMA mapping/unmapping.
526 */
527
528/* To keep track of the dma mapping (sg/single) that has been set */
529#define __data_mapped SCp.phase
530#define __data_mapping SCp.have_data_in
531
532static void __unmap_scsi_data(struct device *dev, struct scsi_cmnd *cmd)
533{
534 switch(cmd->__data_mapped) {
535 case 2:
536 dma_unmap_sg(dev, cmd->buffer, cmd->use_sg,
537 cmd->sc_data_direction);
538 break;
539 case 1:
540 dma_unmap_single(dev, cmd->__data_mapping,
541 cmd->request_bufflen,
542 cmd->sc_data_direction);
543 break;
544 }
545 cmd->__data_mapped = 0;
546}
547
548static u_long __map_scsi_single_data(struct device *dev, struct scsi_cmnd *cmd)
549{
550 dma_addr_t mapping;
551
552 if (cmd->request_bufflen == 0)
553 return 0;
554
555 mapping = dma_map_single(dev, cmd->request_buffer,
556 cmd->request_bufflen,
557 cmd->sc_data_direction);
558 cmd->__data_mapped = 1;
559 cmd->__data_mapping = mapping;
560
561 return mapping;
562}
563
564static int __map_scsi_sg_data(struct device *dev, struct scsi_cmnd *cmd)
565{
566 int use_sg;
567
568 if (cmd->use_sg == 0)
569 return 0;
570
571 use_sg = dma_map_sg(dev, cmd->buffer, cmd->use_sg,
572 cmd->sc_data_direction);
573 cmd->__data_mapped = 2;
574 cmd->__data_mapping = use_sg;
575
576 return use_sg;
577}
578
579#define unmap_scsi_data(np, cmd) __unmap_scsi_data(np->dev, cmd)
580#define map_scsi_single_data(np, cmd) __map_scsi_single_data(np->dev, cmd)
581#define map_scsi_sg_data(np, cmd) __map_scsi_sg_data(np->dev, cmd)
582
583/*==========================================================
584**
585** Driver setup.
586**
587** This structure is initialized from linux config
588** options. It can be overridden at boot-up by the boot
589** command line.
590**
591**==========================================================
592*/
593static struct ncr_driver_setup
594 driver_setup = SCSI_NCR_DRIVER_SETUP;
595
596#ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
597static struct ncr_driver_setup
598 driver_safe_setup __initdata = SCSI_NCR_DRIVER_SAFE_SETUP;
599#endif
600
601#define initverbose (driver_setup.verbose)
602#define bootverbose (np->verbose)
603
604
605/*===================================================================
606**
607** Driver setup from the boot command line
608**
609**===================================================================
610*/
611
612#ifdef MODULE
613#define ARG_SEP ' '
614#else
615#define ARG_SEP ','
616#endif
617
618#define OPT_TAGS 1
619#define OPT_MASTER_PARITY 2
620#define OPT_SCSI_PARITY 3
621#define OPT_DISCONNECTION 4
622#define OPT_SPECIAL_FEATURES 5
623#define OPT_UNUSED_1 6
624#define OPT_FORCE_SYNC_NEGO 7
625#define OPT_REVERSE_PROBE 8
626#define OPT_DEFAULT_SYNC 9
627#define OPT_VERBOSE 10
628#define OPT_DEBUG 11
629#define OPT_BURST_MAX 12
630#define OPT_LED_PIN 13
631#define OPT_MAX_WIDE 14
632#define OPT_SETTLE_DELAY 15
633#define OPT_DIFF_SUPPORT 16
634#define OPT_IRQM 17
635#define OPT_PCI_FIX_UP 18
636#define OPT_BUS_CHECK 19
637#define OPT_OPTIMIZE 20
638#define OPT_RECOVERY 21
639#define OPT_SAFE_SETUP 22
640#define OPT_USE_NVRAM 23
641#define OPT_EXCLUDE 24
642#define OPT_HOST_ID 25
643
644#ifdef SCSI_NCR_IARB_SUPPORT
645#define OPT_IARB 26
646#endif
647
648static char setup_token[] __initdata =
649 "tags:" "mpar:"
650 "spar:" "disc:"
651 "specf:" "ultra:"
652 "fsn:" "revprob:"
653 "sync:" "verb:"
654 "debug:" "burst:"
655 "led:" "wide:"
656 "settle:" "diff:"
657 "irqm:" "pcifix:"
658 "buschk:" "optim:"
659 "recovery:"
660 "safe:" "nvram:"
661 "excl:" "hostid:"
662#ifdef SCSI_NCR_IARB_SUPPORT
663 "iarb:"
664#endif
665 ; /* DONNOT REMOVE THIS ';' */
666
667#ifdef MODULE
668#define ARG_SEP ' '
669#else
670#define ARG_SEP ','
671#endif
672
673static int __init get_setup_token(char *p)
674{
675 char *cur = setup_token;
676 char *pc;
677 int i = 0;
678
679 while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
680 ++pc;
681 ++i;
682 if (!strncmp(p, cur, pc - cur))
683 return i;
684 cur = pc;
685 }
686 return 0;
687}
688
689
690static int __init sym53c8xx__setup(char *str)
691{
692#ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
693 char *cur = str;
694 char *pc, *pv;
695 int i, val, c;
696 int xi = 0;
697
698 while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
699 char *pe;
700
701 val = 0;
702 pv = pc;
703 c = *++pv;
704
705 if (c == 'n')
706 val = 0;
707 else if (c == 'y')
708 val = 1;
709 else
710 val = (int) simple_strtoul(pv, &pe, 0);
711
712 switch (get_setup_token(cur)) {
713 case OPT_TAGS:
714 driver_setup.default_tags = val;
715 if (pe && *pe == '/') {
716 i = 0;
717 while (*pe && *pe != ARG_SEP &&
718 i < sizeof(driver_setup.tag_ctrl)-1) {
719 driver_setup.tag_ctrl[i++] = *pe++;
720 }
721 driver_setup.tag_ctrl[i] = '\0';
722 }
723 break;
724 case OPT_MASTER_PARITY:
725 driver_setup.master_parity = val;
726 break;
727 case OPT_SCSI_PARITY:
728 driver_setup.scsi_parity = val;
729 break;
730 case OPT_DISCONNECTION:
731 driver_setup.disconnection = val;
732 break;
733 case OPT_SPECIAL_FEATURES:
734 driver_setup.special_features = val;
735 break;
736 case OPT_FORCE_SYNC_NEGO:
737 driver_setup.force_sync_nego = val;
738 break;
739 case OPT_REVERSE_PROBE:
740 driver_setup.reverse_probe = val;
741 break;
742 case OPT_DEFAULT_SYNC:
743 driver_setup.default_sync = val;
744 break;
745 case OPT_VERBOSE:
746 driver_setup.verbose = val;
747 break;
748 case OPT_DEBUG:
749 driver_setup.debug = val;
750 break;
751 case OPT_BURST_MAX:
752 driver_setup.burst_max = val;
753 break;
754 case OPT_LED_PIN:
755 driver_setup.led_pin = val;
756 break;
757 case OPT_MAX_WIDE:
758 driver_setup.max_wide = val? 1:0;
759 break;
760 case OPT_SETTLE_DELAY:
761 driver_setup.settle_delay = val;
762 break;
763 case OPT_DIFF_SUPPORT:
764 driver_setup.diff_support = val;
765 break;
766 case OPT_IRQM:
767 driver_setup.irqm = val;
768 break;
769 case OPT_PCI_FIX_UP:
770 driver_setup.pci_fix_up = val;
771 break;
772 case OPT_BUS_CHECK:
773 driver_setup.bus_check = val;
774 break;
775 case OPT_OPTIMIZE:
776 driver_setup.optimize = val;
777 break;
778 case OPT_RECOVERY:
779 driver_setup.recovery = val;
780 break;
781 case OPT_USE_NVRAM:
782 driver_setup.use_nvram = val;
783 break;
784 case OPT_SAFE_SETUP:
785 memcpy(&driver_setup, &driver_safe_setup,
786 sizeof(driver_setup));
787 break;
788 case OPT_EXCLUDE:
789 if (xi < SCSI_NCR_MAX_EXCLUDES)
790 driver_setup.excludes[xi++] = val;
791 break;
792 case OPT_HOST_ID:
793 driver_setup.host_id = val;
794 break;
795#ifdef SCSI_NCR_IARB_SUPPORT
796 case OPT_IARB:
797 driver_setup.iarb = val;
798 break;
799#endif
800 default:
801 printk("sym53c8xx_setup: unexpected boot option '%.*s' ignored\n", (int)(pc-cur+1), cur);
802 break;
803 }
804
805 if ((cur = strchr(cur, ARG_SEP)) != NULL)
806 ++cur;
807 }
808#endif /* SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT */
809 return 1;
810}
811
812/*===================================================================
813**
814** Get device queue depth from boot command line.
815**
816**===================================================================
817*/
818#define DEF_DEPTH (driver_setup.default_tags)
819#define ALL_TARGETS -2
820#define NO_TARGET -1
821#define ALL_LUNS -2
822#define NO_LUN -1
823
824static int device_queue_depth(int unit, int target, int lun)
825{
826 int c, h, t, u, v;
827 char *p = driver_setup.tag_ctrl;
828 char *ep;
829
830 h = -1;
831 t = NO_TARGET;
832 u = NO_LUN;
833 while ((c = *p++) != 0) {
834 v = simple_strtoul(p, &ep, 0);
835 switch(c) {
836 case '/':
837 ++h;
838 t = ALL_TARGETS;
839 u = ALL_LUNS;
840 break;
841 case 't':
842 if (t != target)
843 t = (target == v) ? v : NO_TARGET;
844 u = ALL_LUNS;
845 break;
846 case 'u':
847 if (u != lun)
848 u = (lun == v) ? v : NO_LUN;
849 break;
850 case 'q':
851 if (h == unit &&
852 (t == ALL_TARGETS || t == target) &&
853 (u == ALL_LUNS || u == lun))
854 return v;
855 break;
856 case '-':
857 t = ALL_TARGETS;
858 u = ALL_LUNS;
859 break;
860 default:
861 break;
862 }
863 p = ep;
864 }
865 return DEF_DEPTH;
866}
135 867
136 868
137/*========================================================== 869/*==========================================================
diff --git a/drivers/scsi/ncr53c8xx.h b/drivers/scsi/ncr53c8xx.h
index 05c7b83cef09..6a7bef2e6118 100644
--- a/drivers/scsi/ncr53c8xx.h
+++ b/drivers/scsi/ncr53c8xx.h
@@ -2,6 +2,7 @@
2** Device driver for the PCI-SCSI NCR538XX controller family. 2** Device driver for the PCI-SCSI NCR538XX controller family.
3** 3**
4** Copyright (C) 1994 Wolfgang Stanglmeier 4** Copyright (C) 1994 Wolfgang Stanglmeier
5** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
5** 6**
6** This program is free software; you can redistribute it and/or modify 7** This program is free software; you can redistribute it and/or modify
7** it under the terms of the GNU General Public License as published by 8** it under the terms of the GNU General Public License as published by
@@ -36,15 +37,1275 @@
36** And has been ported to NetBSD by 37** And has been ported to NetBSD by
37** Charles M. Hannum <mycroft@gnu.ai.mit.edu> 38** Charles M. Hannum <mycroft@gnu.ai.mit.edu>
38** 39**
40** NVRAM detection and reading.
41** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
42**
43** Added support for MIPS big endian systems.
44** Carsten Langgaard, carstenl@mips.com
45** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
46**
47** Added support for HP PARISC big endian systems.
48** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
49**
39******************************************************************************* 50*******************************************************************************
40*/ 51*/
41 52
42#ifndef NCR53C8XX_H 53#ifndef NCR53C8XX_H
43#define NCR53C8XX_H 54#define NCR53C8XX_H
44 55
56#include <linux/config.h>
45#include <scsi/scsi_host.h> 57#include <scsi/scsi_host.h>
46 58
47#include "sym53c8xx_defs.h" 59/*
60** If you want a driver as small as possible, do not define the
61** following options.
62*/
63#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
64#define SCSI_NCR_DEBUG_INFO_SUPPORT
65
66/*
67** To disable integrity checking, do not define the
68** following option.
69*/
70#ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
71# define SCSI_NCR_ENABLE_INTEGRITY_CHECK
72#endif
73
74/* ---------------------------------------------------------------------
75** Take into account kernel configured parameters.
76** Most of these options can be overridden at startup by a command line.
77** ---------------------------------------------------------------------
78*/
79
80/*
81 * For Ultra2 and Ultra3 SCSI support option, use special features.
82 *
83 * Value (default) means:
84 * bit 0 : all features enabled, except:
85 * bit 1 : PCI Write And Invalidate.
86 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
87 *
88 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
89 * enabled by the driver.
90 */
91#define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
92
93#define SCSI_NCR_MAX_SYNC (80)
94
95/*
96 * Allow tags from 2 to 256, default 8
97 */
98#ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
99#if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
100#define SCSI_NCR_MAX_TAGS (2)
101#elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
102#define SCSI_NCR_MAX_TAGS (256)
103#else
104#define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
105#endif
106#else
107#define SCSI_NCR_MAX_TAGS (8)
108#endif
109
110/*
111 * Allow tagged command queuing support if configured with default number
112 * of tags set to max (see above).
113 */
114#ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
115#define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
116#elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
117#define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
118#else
119#define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
120#endif
121
122/*
123 * Immediate arbitration
124 */
125#if defined(CONFIG_SCSI_NCR53C8XX_IARB)
126#define SCSI_NCR_IARB_SUPPORT
127#endif
128
129/*
130 * Sync transfer frequency at startup.
131 * Allow from 5Mhz to 80Mhz default 20 Mhz.
132 */
133#ifndef CONFIG_SCSI_NCR53C8XX_SYNC
134#define CONFIG_SCSI_NCR53C8XX_SYNC (20)
135#elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
136#undef CONFIG_SCSI_NCR53C8XX_SYNC
137#define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
138#endif
139
140#if CONFIG_SCSI_NCR53C8XX_SYNC == 0
141#define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
142#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
143#define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
144#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
145#define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
146#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
147#define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
148#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
149#define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
150#else
151#define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
152#endif
153
154/*
155 * Disallow disconnections at boot-up
156 */
157#ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
158#define SCSI_NCR_SETUP_DISCONNECTION (0)
159#else
160#define SCSI_NCR_SETUP_DISCONNECTION (1)
161#endif
162
163/*
164 * Force synchronous negotiation for all targets
165 */
166#ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
167#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
168#else
169#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
170#endif
171
172/*
173 * Disable master parity checking (flawed hardwares need that)
174 */
175#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
176#define SCSI_NCR_SETUP_MASTER_PARITY (0)
177#else
178#define SCSI_NCR_SETUP_MASTER_PARITY (1)
179#endif
180
181/*
182 * Disable scsi parity checking (flawed devices may need that)
183 */
184#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
185#define SCSI_NCR_SETUP_SCSI_PARITY (0)
186#else
187#define SCSI_NCR_SETUP_SCSI_PARITY (1)
188#endif
189
190/*
191 * Settle time after reset at boot-up
192 */
193#define SCSI_NCR_SETUP_SETTLE_TIME (2)
194
195/*
196** Bridge quirks work-around option defaulted to 1.
197*/
198#ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
199#define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
200#endif
201
202/*
203** Work-around common bridge misbehaviour.
204**
205** - Do not flush posted writes in the opposite
206** direction on read.
207** - May reorder DMA writes to memory.
208**
209** This option should not affect performances
210** significantly, so it is the default.
211*/
212#if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
213#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
214#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
215#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
216
217/*
218** Same as option 1, but also deal with
219** misconfigured interrupts.
220**
221** - Edge triggerred instead of level sensitive.
222** - No interrupt line connected.
223** - IRQ number misconfigured.
224**
225** If no interrupt is delivered, the driver will
226** catch the interrupt conditions 10 times per
227** second. No need to say that this option is
228** not recommended.
229*/
230#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
231#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
232#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
233#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
234#define SCSI_NCR_PCIQ_BROKEN_INTR
235
236/*
237** Some bridge designers decided to flush
238** everything prior to deliver the interrupt.
239** This option tries to deal with such a
240** behaviour.
241*/
242#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
243#define SCSI_NCR_PCIQ_SYNC_ON_INTR
244#endif
245
246/*
247** Other parameters not configurable with "make config"
248** Avoid to change these constants, unless you know what you are doing.
249*/
250
251#define SCSI_NCR_ALWAYS_SIMPLE_TAG
252#define SCSI_NCR_MAX_SCATTER (127)
253#define SCSI_NCR_MAX_TARGET (16)
254
255/*
256** Compute some desirable value for CAN_QUEUE
257** and CMD_PER_LUN.
258** The driver will use lower values if these
259** ones appear to be too large.
260*/
261#define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
262#define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
263
264#define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
265#define SCSI_NCR_TIMER_INTERVAL (HZ)
266
267#if 1 /* defined CONFIG_SCSI_MULTI_LUN */
268#define SCSI_NCR_MAX_LUN (16)
269#else
270#define SCSI_NCR_MAX_LUN (1)
271#endif
272
273/*
274 * IO functions definition for big/little endian CPU support.
275 * For now, the NCR is only supported in little endian addressing mode,
276 */
277
278#ifdef __BIG_ENDIAN
279
280#define inw_l2b inw
281#define inl_l2b inl
282#define outw_b2l outw
283#define outl_b2l outl
284
285#define readb_raw readb
286#define writeb_raw writeb
287
288#if defined(SCSI_NCR_BIG_ENDIAN)
289#define readw_l2b __raw_readw
290#define readl_l2b __raw_readl
291#define writew_b2l __raw_writew
292#define writel_b2l __raw_writel
293#define readw_raw __raw_readw
294#define readl_raw __raw_readl
295#define writew_raw __raw_writew
296#define writel_raw __raw_writel
297#else /* Other big-endian */
298#define readw_l2b readw
299#define readl_l2b readl
300#define writew_b2l writew
301#define writel_b2l writel
302#define readw_raw readw
303#define readl_raw readl
304#define writew_raw writew
305#define writel_raw writel
306#endif
307
308#else /* little endian */
309
310#define inw_raw inw
311#define inl_raw inl
312#define outw_raw outw
313#define outl_raw outl
314
315#define readb_raw readb
316#define readw_raw readw
317#define readl_raw readl
318#define writeb_raw writeb
319#define writew_raw writew
320#define writel_raw writel
321
322#endif
323
324#if !defined(__hppa__) && !defined(__mips__)
325#ifdef SCSI_NCR_BIG_ENDIAN
326#error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
327#endif
328#endif
329
330#define MEMORY_BARRIER() mb()
331
332
333/*
334 * If the NCR uses big endian addressing mode over the
335 * PCI, actual io register addresses for byte and word
336 * accesses must be changed according to lane routing.
337 * Btw, ncr_offb() and ncr_offw() macros only apply to
338 * constants and so donnot generate bloated code.
339 */
340
341#if defined(SCSI_NCR_BIG_ENDIAN)
342
343#define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
344#define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
345
346#else
347
348#define ncr_offb(o) (o)
349#define ncr_offw(o) (o)
350
351#endif
352
353/*
354 * If the CPU and the NCR use same endian-ness addressing,
355 * no byte reordering is needed for script patching.
356 * Macro cpu_to_scr() is to be used for script patching.
357 * Macro scr_to_cpu() is to be used for getting a DWORD
358 * from the script.
359 */
360
361#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
362
363#define cpu_to_scr(dw) cpu_to_le32(dw)
364#define scr_to_cpu(dw) le32_to_cpu(dw)
365
366#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
367
368#define cpu_to_scr(dw) cpu_to_be32(dw)
369#define scr_to_cpu(dw) be32_to_cpu(dw)
370
371#else
372
373#define cpu_to_scr(dw) (dw)
374#define scr_to_cpu(dw) (dw)
375
376#endif
377
378/*
379 * Access to the controller chip.
380 *
381 * If the CPU and the NCR use same endian-ness addressing,
382 * no byte reordering is needed for accessing chip io
383 * registers. Functions suffixed by '_raw' are assumed
384 * to access the chip over the PCI without doing byte
385 * reordering. Functions suffixed by '_l2b' are
386 * assumed to perform little-endian to big-endian byte
387 * reordering, those suffixed by '_b2l' blah, blah,
388 * blah, ...
389 */
390
391/*
392 * MEMORY mapped IO input / output
393 */
394
395#define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
396#define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
397
398#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
399
400#define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
401#define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
402
403#define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
404#define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
405
406#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
407
408#define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
409#define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
410
411#define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
412#define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
413
414#else
415
416#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
417/* Only 8 or 32 bit transfers allowed */
418#define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
419#else
420#define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
421#endif
422#define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
423
424#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
425/* Only 8 or 32 bit transfers allowed */
426#define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
427#else
428#define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
429#endif
430#define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
431
432#endif
433
434#define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
435#define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
436#define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
437
438#define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
439#define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
440#define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
441
442/*
443 * Set bit field ON, OFF
444 */
445
446#define OUTONB(r, m) OUTB(r, INB(r) | (m))
447#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
448#define OUTONW(r, m) OUTW(r, INW(r) | (m))
449#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
450#define OUTONL(r, m) OUTL(r, INL(r) | (m))
451#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
452
453/*
454 * We normally want the chip to have a consistent view
455 * of driver internal data structures when we restart it.
456 * Thus these macros.
457 */
458#define OUTL_DSP(v) \
459 do { \
460 MEMORY_BARRIER(); \
461 OUTL (nc_dsp, (v)); \
462 } while (0)
463
464#define OUTONB_STD() \
465 do { \
466 MEMORY_BARRIER(); \
467 OUTONB (nc_dcntl, (STD|NOCOM)); \
468 } while (0)
469
470
471/*
472** NCR53C8XX devices features table.
473*/
474struct ncr_chip {
475 unsigned short revision_id;
476 unsigned char burst_max; /* log-base-2 of max burst */
477 unsigned char offset_max;
478 unsigned char nr_divisor;
479 unsigned int features;
480#define FE_LED0 (1<<0)
481#define FE_WIDE (1<<1) /* Wide data transfers */
482#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
483#define FE_DBLR (1<<4) /* Clock doubler present */
484#define FE_QUAD (1<<5) /* Clock quadrupler present */
485#define FE_ERL (1<<6) /* Enable read line */
486#define FE_CLSE (1<<7) /* Cache line size enable */
487#define FE_WRIE (1<<8) /* Write & Invalidate enable */
488#define FE_ERMP (1<<9) /* Enable read multiple */
489#define FE_BOF (1<<10) /* Burst opcode fetch */
490#define FE_DFS (1<<11) /* DMA fifo size */
491#define FE_PFEN (1<<12) /* Prefetch enable */
492#define FE_LDSTR (1<<13) /* Load/Store supported */
493#define FE_RAM (1<<14) /* On chip RAM present */
494#define FE_VARCLK (1<<15) /* SCSI clock may vary */
495#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
496#define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
497#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
498#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
499#define FE_LEDC (1<<20) /* Hardware control of LED */
500#define FE_DIFF (1<<21) /* Support Differential SCSI */
501#define FE_66MHZ (1<<23) /* 66MHz PCI Support */
502#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
503#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
504#define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
505#define FE_EHP (1<<27) /* 720: Even host parity */
506#define FE_MUX (1<<28) /* 720: Multiplexed bus */
507#define FE_EA (1<<29) /* 720: Enable Ack */
508
509#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
510#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
511#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
512};
513
514
515/*
516** Driver setup structure.
517**
518** This structure is initialized from linux config options.
519** It can be overridden at boot-up by the boot command line.
520*/
521#define SCSI_NCR_MAX_EXCLUDES 8
522struct ncr_driver_setup {
523 u8 master_parity;
524 u8 scsi_parity;
525 u8 disconnection;
526 u8 special_features;
527 u8 force_sync_nego;
528 u8 reverse_probe;
529 u8 pci_fix_up;
530 u8 use_nvram;
531 u8 verbose;
532 u8 default_tags;
533 u16 default_sync;
534 u16 debug;
535 u8 burst_max;
536 u8 led_pin;
537 u8 max_wide;
538 u8 settle_delay;
539 u8 diff_support;
540 u8 irqm;
541 u8 bus_check;
542 u8 optimize;
543 u8 recovery;
544 u8 host_id;
545 u16 iarb;
546 u32 excludes[SCSI_NCR_MAX_EXCLUDES];
547 char tag_ctrl[100];
548};
549
550/*
551** Initial setup.
552** Can be overriden at startup by a command line.
553*/
554#define SCSI_NCR_DRIVER_SETUP \
555{ \
556 SCSI_NCR_SETUP_MASTER_PARITY, \
557 SCSI_NCR_SETUP_SCSI_PARITY, \
558 SCSI_NCR_SETUP_DISCONNECTION, \
559 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
560 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
561 0, \
562 0, \
563 1, \
564 0, \
565 SCSI_NCR_SETUP_DEFAULT_TAGS, \
566 SCSI_NCR_SETUP_DEFAULT_SYNC, \
567 0x00, \
568 7, \
569 0, \
570 1, \
571 SCSI_NCR_SETUP_SETTLE_TIME, \
572 0, \
573 0, \
574 1, \
575 0, \
576 0, \
577 255, \
578 0x00 \
579}
580
581/*
582** Boot fail safe setup.
583** Override initial setup from boot command line:
584** ncr53c8xx=safe:y
585*/
586#define SCSI_NCR_DRIVER_SAFE_SETUP \
587{ \
588 0, \
589 1, \
590 0, \
591 0, \
592 0, \
593 0, \
594 0, \
595 1, \
596 2, \
597 0, \
598 255, \
599 0x00, \
600 255, \
601 0, \
602 0, \
603 10, \
604 1, \
605 1, \
606 1, \
607 0, \
608 0, \
609 255 \
610}
611
612/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
613
614/*-----------------------------------------------------------------
615**
616** The ncr 53c810 register structure.
617**
618**-----------------------------------------------------------------
619*/
620
621struct ncr_reg {
622/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
623
624/*01*/ u8 nc_scntl1; /* no reset */
625 #define ISCON 0x10 /* connected to scsi */
626 #define CRST 0x08 /* force reset */
627 #define IARB 0x02 /* immediate arbitration */
628
629/*02*/ u8 nc_scntl2; /* no disconnect expected */
630 #define SDU 0x80 /* cmd: disconnect will raise error */
631 #define CHM 0x40 /* sta: chained mode */
632 #define WSS 0x08 /* sta: wide scsi send [W]*/
633 #define WSR 0x01 /* sta: wide scsi received [W]*/
634
635/*03*/ u8 nc_scntl3; /* cnf system clock dependent */
636 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
637 #define ULTRA 0x80 /* cmd: ULTRA enable */
638 /* bits 0-2, 7 rsvd for C1010 */
639
640/*04*/ u8 nc_scid; /* cnf host adapter scsi address */
641 #define RRE 0x40 /* r/w:e enable response to resel. */
642 #define SRE 0x20 /* r/w:e enable response to select */
643
644/*05*/ u8 nc_sxfer; /* ### Sync speed and count */
645 /* bits 6-7 rsvd for C1010 */
646
647/*06*/ u8 nc_sdid; /* ### Destination-ID */
648
649/*07*/ u8 nc_gpreg; /* ??? IO-Pins */
650
651/*08*/ u8 nc_sfbr; /* ### First byte in phase */
652
653/*09*/ u8 nc_socl;
654 #define CREQ 0x80 /* r/w: SCSI-REQ */
655 #define CACK 0x40 /* r/w: SCSI-ACK */
656 #define CBSY 0x20 /* r/w: SCSI-BSY */
657 #define CSEL 0x10 /* r/w: SCSI-SEL */
658 #define CATN 0x08 /* r/w: SCSI-ATN */
659 #define CMSG 0x04 /* r/w: SCSI-MSG */
660 #define CC_D 0x02 /* r/w: SCSI-C_D */
661 #define CI_O 0x01 /* r/w: SCSI-I_O */
662
663/*0a*/ u8 nc_ssid;
664
665/*0b*/ u8 nc_sbcl;
666
667/*0c*/ u8 nc_dstat;
668 #define DFE 0x80 /* sta: dma fifo empty */
669 #define MDPE 0x40 /* int: master data parity error */
670 #define BF 0x20 /* int: script: bus fault */
671 #define ABRT 0x10 /* int: script: command aborted */
672 #define SSI 0x08 /* int: script: single step */
673 #define SIR 0x04 /* int: script: interrupt instruct. */
674 #define IID 0x01 /* int: script: illegal instruct. */
675
676/*0d*/ u8 nc_sstat0;
677 #define ILF 0x80 /* sta: data in SIDL register lsb */
678 #define ORF 0x40 /* sta: data in SODR register lsb */
679 #define OLF 0x20 /* sta: data in SODL register lsb */
680 #define AIP 0x10 /* sta: arbitration in progress */
681 #define LOA 0x08 /* sta: arbitration lost */
682 #define WOA 0x04 /* sta: arbitration won */
683 #define IRST 0x02 /* sta: scsi reset signal */
684 #define SDP 0x01 /* sta: scsi parity signal */
685
686/*0e*/ u8 nc_sstat1;
687 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
688
689/*0f*/ u8 nc_sstat2;
690 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
691 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
692 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
693 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
694 #define LDSC 0x02 /* sta: disconnect & reconnect */
695
696/*10*/ u8 nc_dsa; /* --> Base page */
697/*11*/ u8 nc_dsa1;
698/*12*/ u8 nc_dsa2;
699/*13*/ u8 nc_dsa3;
700
701/*14*/ u8 nc_istat; /* --> Main Command and status */
702 #define CABRT 0x80 /* cmd: abort current operation */
703 #define SRST 0x40 /* mod: reset chip */
704 #define SIGP 0x20 /* r/w: message from host to ncr */
705 #define SEM 0x10 /* r/w: message between host + ncr */
706 #define CON 0x08 /* sta: connected to scsi */
707 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
708 #define SIP 0x02 /* sta: scsi-interrupt */
709 #define DIP 0x01 /* sta: host/script interrupt */
710
711/*15*/ u8 nc_istat1; /* 896 and later cores only */
712 #define FLSH 0x04 /* sta: chip is flushing */
713 #define SRUN 0x02 /* sta: scripts are running */
714 #define SIRQD 0x01 /* r/w: disable INT pin */
715
716/*16*/ u8 nc_mbox0; /* 896 and later cores only */
717/*17*/ u8 nc_mbox1; /* 896 and later cores only */
718
719/*18*/ u8 nc_ctest0;
720 #define EHP 0x04 /* 720 even host parity */
721/*19*/ u8 nc_ctest1;
722
723/*1a*/ u8 nc_ctest2;
724 #define CSIGP 0x40
725 /* bits 0-2,7 rsvd for C1010 */
726
727/*1b*/ u8 nc_ctest3;
728 #define FLF 0x08 /* cmd: flush dma fifo */
729 #define CLF 0x04 /* cmd: clear dma fifo */
730 #define FM 0x02 /* mod: fetch pin mode */
731 #define WRIE 0x01 /* mod: write and invalidate enable */
732 /* bits 4-7 rsvd for C1010 */
733
734/*1c*/ u32 nc_temp; /* ### Temporary stack */
735
736/*20*/ u8 nc_dfifo;
737/*21*/ u8 nc_ctest4;
738 #define MUX 0x80 /* 720 host bus multiplex mode */
739 #define BDIS 0x80 /* mod: burst disable */
740 #define MPEE 0x08 /* mod: master parity error enable */
741
742/*22*/ u8 nc_ctest5;
743 #define DFS 0x20 /* mod: dma fifo size */
744 /* bits 0-1, 3-7 rsvd for C1010 */
745/*23*/ u8 nc_ctest6;
746
747/*24*/ u32 nc_dbc; /* ### Byte count and command */
748/*28*/ u32 nc_dnad; /* ### Next command register */
749/*2c*/ u32 nc_dsp; /* --> Script Pointer */
750/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
751
752/*34*/ u8 nc_scratcha; /* Temporary register a */
753/*35*/ u8 nc_scratcha1;
754/*36*/ u8 nc_scratcha2;
755/*37*/ u8 nc_scratcha3;
756
757/*38*/ u8 nc_dmode;
758 #define BL_2 0x80 /* mod: burst length shift value +2 */
759 #define BL_1 0x40 /* mod: burst length shift value +1 */
760 #define ERL 0x08 /* mod: enable read line */
761 #define ERMP 0x04 /* mod: enable read multiple */
762 #define BOF 0x02 /* mod: burst op code fetch */
763
764/*39*/ u8 nc_dien;
765/*3a*/ u8 nc_sbr;
766
767/*3b*/ u8 nc_dcntl; /* --> Script execution control */
768 #define CLSE 0x80 /* mod: cache line size enable */
769 #define PFF 0x40 /* cmd: pre-fetch flush */
770 #define PFEN 0x20 /* mod: pre-fetch enable */
771 #define EA 0x20 /* mod: 720 enable-ack */
772 #define SSM 0x10 /* mod: single step mode */
773 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
774 #define STD 0x04 /* cmd: start dma mode */
775 #define IRQD 0x02 /* mod: irq disable */
776 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
777 /* bits 0-1 rsvd for C1010 */
778
779/*3c*/ u32 nc_adder;
780
781/*40*/ u16 nc_sien; /* -->: interrupt enable */
782/*42*/ u16 nc_sist; /* <--: interrupt status */
783 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
784 #define STO 0x0400/* sta: timeout (select) */
785 #define GEN 0x0200/* sta: timeout (general) */
786 #define HTH 0x0100/* sta: timeout (handshake) */
787 #define MA 0x80 /* sta: phase mismatch */
788 #define CMP 0x40 /* sta: arbitration complete */
789 #define SEL 0x20 /* sta: selected by another device */
790 #define RSL 0x10 /* sta: reselected by another device*/
791 #define SGE 0x08 /* sta: gross error (over/underflow)*/
792 #define UDC 0x04 /* sta: unexpected disconnect */
793 #define RST 0x02 /* sta: scsi bus reset detected */
794 #define PAR 0x01 /* sta: scsi parity error */
795
796/*44*/ u8 nc_slpar;
797/*45*/ u8 nc_swide;
798/*46*/ u8 nc_macntl;
799/*47*/ u8 nc_gpcntl;
800/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
801/*49*/ u8 nc_stime1; /* cmd: timeout user defined */
802/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
803
804/*4c*/ u8 nc_stest0;
805
806/*4d*/ u8 nc_stest1;
807 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
808 #define DBLEN 0x08 /* clock doubler running */
809 #define DBLSEL 0x04 /* clock doubler selected */
810
811
812/*4e*/ u8 nc_stest2;
813 #define ROF 0x40 /* reset scsi offset (after gross error!) */
814 #define DIF 0x20 /* 720 SCSI differential mode */
815 #define EXT 0x02 /* extended filtering */
816
817/*4f*/ u8 nc_stest3;
818 #define TE 0x80 /* c: tolerAnt enable */
819 #define HSC 0x20 /* c: Halt SCSI Clock */
820 #define CSF 0x02 /* c: clear scsi fifo */
821
822/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
823/*52*/ u8 nc_stest4;
824 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
825 #define SMODE_HVD 0x40 /* High Voltage Differential */
826 #define SMODE_SE 0x80 /* Single Ended */
827 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
828 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
829 /* bits 0-5 rsvd for C1010 */
830
831/*53*/ u8 nc_53_;
832/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
833/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
834 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
835 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
836 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
837 #define DISFC 0x10 /* Disable Auto FIFO Clear */
838 #define DILS 0x02 /* Disable Internal Load/Store */
839 #define DPR 0x01 /* Disable Pipe Req */
840
841/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
842 #define ZMOD 0x80 /* High Impedance Mode */
843 #define DIC 0x10 /* Disable Internal Cycles */
844 #define DDAC 0x08 /* Disable Dual Address Cycle */
845 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
846 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
847 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
848
849/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
850/*5a*/ u16 nc_5a_;
851
852/*5c*/ u8 nc_scr0; /* Working register B */
853/*5d*/ u8 nc_scr1; /* */
854/*5e*/ u8 nc_scr2; /* */
855/*5f*/ u8 nc_scr3; /* */
856
857/*60*/ u8 nc_scrx[64]; /* Working register C-R */
858/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
859/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
860/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
861/*ac*/ u32 nc_drs; /* DSA Relative Selector */
862/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
863/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
864/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
865/*bc*/ u16 nc_scntl4; /* C1010 only */
866 #define U3EN 0x80 /* Enable Ultra 3 */
867 #define AIPEN 0x40 /* Allow check upper byte lanes */
868 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
869 transfer edge */
870 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
871 transfer edge */
872
873/*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
874/*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
875
876/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
877/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
878/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
879/*c9*/ u8 nc_rbc1; /* */
880/*ca*/ u8 nc_rbc2; /* */
881/*cb*/ u8 nc_rbc3; /* */
882
883/*cc*/ u8 nc_ua; /* Updated Address */
884/*cd*/ u8 nc_ua1; /* */
885/*ce*/ u8 nc_ua2; /* */
886/*cf*/ u8 nc_ua3; /* */
887/*d0*/ u32 nc_esa; /* Entry Storage Address */
888/*d4*/ u8 nc_ia; /* Instruction Address */
889/*d5*/ u8 nc_ia1;
890/*d6*/ u8 nc_ia2;
891/*d7*/ u8 nc_ia3;
892/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
893/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
894
895 /* Following for C1010 only */
896/*e0*/ u16 nc_crcpad; /* CRC Value */
897/*e2*/ u8 nc_crccntl0; /* CRC control register */
898 #define SNDCRC 0x10 /* Send CRC Request */
899/*e3*/ u8 nc_crccntl1; /* CRC control register */
900/*e4*/ u32 nc_crcdata; /* CRC data register */
901/*e8*/ u32 nc_e8_; /* rsvd */
902/*ec*/ u32 nc_ec_; /* rsvd */
903/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
904
905};
906
907/*-----------------------------------------------------------
908**
909** Utility macros for the script.
910**
911**-----------------------------------------------------------
912*/
913
914#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
915#define REG(r) REGJ (nc_, r)
916
917typedef u32 ncrcmd;
918
919/*-----------------------------------------------------------
920**
921** SCSI phases
922**
923** DT phases illegal for ncr driver.
924**
925**-----------------------------------------------------------
926*/
927
928#define SCR_DATA_OUT 0x00000000
929#define SCR_DATA_IN 0x01000000
930#define SCR_COMMAND 0x02000000
931#define SCR_STATUS 0x03000000
932#define SCR_DT_DATA_OUT 0x04000000
933#define SCR_DT_DATA_IN 0x05000000
934#define SCR_MSG_OUT 0x06000000
935#define SCR_MSG_IN 0x07000000
936
937#define SCR_ILG_OUT 0x04000000
938#define SCR_ILG_IN 0x05000000
939
940/*-----------------------------------------------------------
941**
942** Data transfer via SCSI.
943**
944**-----------------------------------------------------------
945**
946** MOVE_ABS (LEN)
947** <<start address>>
948**
949** MOVE_IND (LEN)
950** <<dnad_offset>>
951**
952** MOVE_TBL
953** <<dnad_offset>>
954**
955**-----------------------------------------------------------
956*/
957
958#define OPC_MOVE 0x08000000
959
960#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
961#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
962#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
963
964#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
965#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
966#define SCR_CHMOV_TBL (0x10000000)
967
968struct scr_tblmove {
969 u32 size;
970 u32 addr;
971};
972
973/*-----------------------------------------------------------
974**
975** Selection
976**
977**-----------------------------------------------------------
978**
979** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
980** <<alternate_address>>
981**
982** SEL_TBL | << dnad_offset>> [ | REL_JMP]
983** <<alternate_address>>
984**
985**-----------------------------------------------------------
986*/
987
988#define SCR_SEL_ABS 0x40000000
989#define SCR_SEL_ABS_ATN 0x41000000
990#define SCR_SEL_TBL 0x42000000
991#define SCR_SEL_TBL_ATN 0x43000000
992
993
994#ifdef SCSI_NCR_BIG_ENDIAN
995struct scr_tblsel {
996 u8 sel_scntl3;
997 u8 sel_id;
998 u8 sel_sxfer;
999 u8 sel_scntl4;
1000};
1001#else
1002struct scr_tblsel {
1003 u8 sel_scntl4;
1004 u8 sel_sxfer;
1005 u8 sel_id;
1006 u8 sel_scntl3;
1007};
1008#endif
1009
1010#define SCR_JMP_REL 0x04000000
1011#define SCR_ID(id) (((u32)(id)) << 16)
1012
1013/*-----------------------------------------------------------
1014**
1015** Waiting for Disconnect or Reselect
1016**
1017**-----------------------------------------------------------
1018**
1019** WAIT_DISC
1020** dummy: <<alternate_address>>
1021**
1022** WAIT_RESEL
1023** <<alternate_address>>
1024**
1025**-----------------------------------------------------------
1026*/
1027
1028#define SCR_WAIT_DISC 0x48000000
1029#define SCR_WAIT_RESEL 0x50000000
1030
1031/*-----------------------------------------------------------
1032**
1033** Bit Set / Reset
1034**
1035**-----------------------------------------------------------
1036**
1037** SET (flags {|.. })
1038**
1039** CLR (flags {|.. })
1040**
1041**-----------------------------------------------------------
1042*/
1043
1044#define SCR_SET(f) (0x58000000 | (f))
1045#define SCR_CLR(f) (0x60000000 | (f))
1046
1047#define SCR_CARRY 0x00000400
1048#define SCR_TRG 0x00000200
1049#define SCR_ACK 0x00000040
1050#define SCR_ATN 0x00000008
1051
1052
1053
1054
1055/*-----------------------------------------------------------
1056**
1057** Memory to memory move
1058**
1059**-----------------------------------------------------------
1060**
1061** COPY (bytecount)
1062** << source_address >>
1063** << destination_address >>
1064**
1065** SCR_COPY sets the NO FLUSH option by default.
1066** SCR_COPY_F does not set this option.
1067**
1068** For chips which do not support this option,
1069** ncr_copy_and_bind() will remove this bit.
1070**-----------------------------------------------------------
1071*/
1072
1073#define SCR_NO_FLUSH 0x01000000
1074
1075#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1076#define SCR_COPY_F(n) (0xc0000000 | (n))
1077
1078/*-----------------------------------------------------------
1079**
1080** Register move and binary operations
1081**
1082**-----------------------------------------------------------
1083**
1084** SFBR_REG (reg, op, data) reg = SFBR op data
1085** << 0 >>
1086**
1087** REG_SFBR (reg, op, data) SFBR = reg op data
1088** << 0 >>
1089**
1090** REG_REG (reg, op, data) reg = reg op data
1091** << 0 >>
1092**
1093**-----------------------------------------------------------
1094** On 810A, 860, 825A, 875, 895 and 896 chips the content
1095** of SFBR register can be used as data (SCR_SFBR_DATA).
1096** The 896 has additionnal IO registers starting at
1097** offset 0x80. Bit 7 of register offset is stored in
1098** bit 7 of the SCRIPTS instruction first DWORD.
1099**-----------------------------------------------------------
1100*/
1101
1102#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1103
1104#define SCR_SFBR_REG(reg,op,data) \
1105 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1106
1107#define SCR_REG_SFBR(reg,op,data) \
1108 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1109
1110#define SCR_REG_REG(reg,op,data) \
1111 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1112
1113
1114#define SCR_LOAD 0x00000000
1115#define SCR_SHL 0x01000000
1116#define SCR_OR 0x02000000
1117#define SCR_XOR 0x03000000
1118#define SCR_AND 0x04000000
1119#define SCR_SHR 0x05000000
1120#define SCR_ADD 0x06000000
1121#define SCR_ADDC 0x07000000
1122
1123#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1124
1125/*-----------------------------------------------------------
1126**
1127** FROM_REG (reg) SFBR = reg
1128** << 0 >>
1129**
1130** TO_REG (reg) reg = SFBR
1131** << 0 >>
1132**
1133** LOAD_REG (reg, data) reg = <data>
1134** << 0 >>
1135**
1136** LOAD_SFBR(data) SFBR = <data>
1137** << 0 >>
1138**
1139**-----------------------------------------------------------
1140*/
1141
1142#define SCR_FROM_REG(reg) \
1143 SCR_REG_SFBR(reg,SCR_OR,0)
1144
1145#define SCR_TO_REG(reg) \
1146 SCR_SFBR_REG(reg,SCR_OR,0)
1147
1148#define SCR_LOAD_REG(reg,data) \
1149 SCR_REG_REG(reg,SCR_LOAD,data)
1150
1151#define SCR_LOAD_SFBR(data) \
1152 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1153
1154/*-----------------------------------------------------------
1155**
1156** LOAD from memory to register.
1157** STORE from register to memory.
1158**
1159** Only supported by 810A, 860, 825A, 875, 895 and 896.
1160**
1161**-----------------------------------------------------------
1162**
1163** LOAD_ABS (LEN)
1164** <<start address>>
1165**
1166** LOAD_REL (LEN) (DSA relative)
1167** <<dsa_offset>>
1168**
1169**-----------------------------------------------------------
1170*/
1171
1172#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1173#define SCR_NO_FLUSH2 0x02000000
1174#define SCR_DSA_REL2 0x10000000
1175
1176#define SCR_LOAD_R(reg, how, n) \
1177 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1178
1179#define SCR_STORE_R(reg, how, n) \
1180 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1181
1182#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1183#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1184#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1185#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1186
1187#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1188#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1189#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1190#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1191
1192
1193/*-----------------------------------------------------------
1194**
1195** Waiting for Disconnect or Reselect
1196**
1197**-----------------------------------------------------------
1198**
1199** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1200** <<address>>
1201**
1202** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1203** <<distance>>
1204**
1205** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1206** <<address>>
1207**
1208** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1209** <<distance>>
1210**
1211** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1212** <<dummy>>
1213**
1214** INT [ | IFTRUE/IFFALSE ( ... ) ]
1215** <<ident>>
1216**
1217** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1218** <<ident>>
1219**
1220** Conditions:
1221** WHEN (phase)
1222** IF (phase)
1223** CARRYSET
1224** DATA (data, mask)
1225**
1226**-----------------------------------------------------------
1227*/
1228
1229#define SCR_NO_OP 0x80000000
1230#define SCR_JUMP 0x80080000
1231#define SCR_JUMP64 0x80480000
1232#define SCR_JUMPR 0x80880000
1233#define SCR_CALL 0x88080000
1234#define SCR_CALLR 0x88880000
1235#define SCR_RETURN 0x90080000
1236#define SCR_INT 0x98080000
1237#define SCR_INT_FLY 0x98180000
1238
1239#define IFFALSE(arg) (0x00080000 | (arg))
1240#define IFTRUE(arg) (0x00000000 | (arg))
1241
1242#define WHEN(phase) (0x00030000 | (phase))
1243#define IF(phase) (0x00020000 | (phase))
1244
1245#define DATA(D) (0x00040000 | ((D) & 0xff))
1246#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1247
1248#define CARRYSET (0x00200000)
1249
1250/*-----------------------------------------------------------
1251**
1252** SCSI constants.
1253**
1254**-----------------------------------------------------------
1255*/
1256
1257/*
1258** Messages
1259*/
1260
1261#define M_COMPLETE COMMAND_COMPLETE
1262#define M_EXTENDED EXTENDED_MESSAGE
1263#define M_SAVE_DP SAVE_POINTERS
1264#define M_RESTORE_DP RESTORE_POINTERS
1265#define M_DISCONNECT DISCONNECT
1266#define M_ID_ERROR INITIATOR_ERROR
1267#define M_ABORT ABORT_TASK_SET
1268#define M_REJECT MESSAGE_REJECT
1269#define M_NOOP NOP
1270#define M_PARITY MSG_PARITY_ERROR
1271#define M_LCOMPLETE LINKED_CMD_COMPLETE
1272#define M_FCOMPLETE LINKED_FLG_CMD_COMPLETE
1273#define M_RESET TARGET_RESET
1274#define M_ABORT_TAG ABORT_TASK
1275#define M_CLEAR_QUEUE CLEAR_TASK_SET
1276#define M_INIT_REC INITIATE_RECOVERY
1277#define M_REL_REC RELEASE_RECOVERY
1278#define M_TERMINATE (0x11)
1279#define M_SIMPLE_TAG SIMPLE_QUEUE_TAG
1280#define M_HEAD_TAG HEAD_OF_QUEUE_TAG
1281#define M_ORDERED_TAG ORDERED_QUEUE_TAG
1282#define M_IGN_RESIDUE IGNORE_WIDE_RESIDUE
1283#define M_IDENTIFY (0x80)
1284
1285#define M_X_MODIFY_DP EXTENDED_MODIFY_DATA_POINTER
1286#define M_X_SYNC_REQ EXTENDED_SDTR
1287#define M_X_WIDE_REQ EXTENDED_WDTR
1288#define M_X_PPR_REQ EXTENDED_PPR
1289
1290/*
1291** Status
1292*/
1293
1294#define S_GOOD (0x00)
1295#define S_CHECK_COND (0x02)
1296#define S_COND_MET (0x04)
1297#define S_BUSY (0x08)
1298#define S_INT (0x10)
1299#define S_INT_COND_MET (0x14)
1300#define S_CONFLICT (0x18)
1301#define S_TERMINATED (0x20)
1302#define S_QUEUE_FULL (0x28)
1303#define S_ILLEGAL (0xff)
1304#define S_SENSE (0x80)
1305
1306/*
1307 * End of ncrreg from FreeBSD
1308 */
48 1309
49/* 1310/*
50 Build a scatter/gather entry. 1311 Build a scatter/gather entry.
diff --git a/drivers/scsi/sym53c8xx_comm.h b/drivers/scsi/sym53c8xx_comm.h
deleted file mode 100644
index 20ae2b17df58..000000000000
--- a/drivers/scsi/sym53c8xx_comm.h
+++ /dev/null
@@ -1,792 +0,0 @@
1/******************************************************************************
2** High Performance device driver for the Symbios 53C896 controller.
3**
4** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
5**
6** This driver also supports all the Symbios 53C8XX controller family,
7** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8** revisions of 53C815 controllers.
9**
10** This driver is based on the Linux port of the FreeBSD ncr driver.
11**
12** Copyright (C) 1994 Wolfgang Stanglmeier
13**
14**-----------------------------------------------------------------------------
15**
16** This program is free software; you can redistribute it and/or modify
17** it under the terms of the GNU General Public License as published by
18** the Free Software Foundation; either version 2 of the License, or
19** (at your option) any later version.
20**
21** This program is distributed in the hope that it will be useful,
22** but WITHOUT ANY WARRANTY; without even the implied warranty of
23** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24** GNU General Public License for more details.
25**
26** You should have received a copy of the GNU General Public License
27** along with this program; if not, write to the Free Software
28** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29**
30**-----------------------------------------------------------------------------
31**
32** The Linux port of the FreeBSD ncr driver has been achieved in
33** november 1995 by:
34**
35** Gerard Roudier <groudier@free.fr>
36**
37** Being given that this driver originates from the FreeBSD version, and
38** in order to keep synergy on both, any suggested enhancements and corrections
39** received on Linux are automatically a potential candidate for the FreeBSD
40** version.
41**
42** The original driver has been written for 386bsd and FreeBSD by
43** Wolfgang Stanglmeier <wolf@cologne.de>
44** Stefan Esser <se@mi.Uni-Koeln.de>
45**
46**-----------------------------------------------------------------------------
47**
48** Major contributions:
49** --------------------
50**
51** NVRAM detection and reading.
52** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53**
54*******************************************************************************
55*/
56
57/*==========================================================
58**
59** Debugging tags
60**
61**==========================================================
62*/
63
64#define DEBUG_ALLOC (0x0001)
65#define DEBUG_PHASE (0x0002)
66#define DEBUG_QUEUE (0x0008)
67#define DEBUG_RESULT (0x0010)
68#define DEBUG_POINTER (0x0020)
69#define DEBUG_SCRIPT (0x0040)
70#define DEBUG_TINY (0x0080)
71#define DEBUG_TIMING (0x0100)
72#define DEBUG_NEGO (0x0200)
73#define DEBUG_TAGS (0x0400)
74#define DEBUG_SCATTER (0x0800)
75#define DEBUG_IC (0x1000)
76
77/*
78** Enable/Disable debug messages.
79** Can be changed at runtime too.
80*/
81
82#ifdef SCSI_NCR_DEBUG_INFO_SUPPORT
83static int ncr_debug = SCSI_NCR_DEBUG_FLAGS;
84 #define DEBUG_FLAGS ncr_debug
85#else
86 #define DEBUG_FLAGS SCSI_NCR_DEBUG_FLAGS
87#endif
88
89static inline struct list_head *ncr_list_pop(struct list_head *head)
90{
91 if (!list_empty(head)) {
92 struct list_head *elem = head->next;
93
94 list_del(elem);
95 return elem;
96 }
97
98 return NULL;
99}
100
101#ifdef __sparc__
102#include <asm/irq.h>
103#endif
104
105/*==========================================================
106**
107** Simple power of two buddy-like allocator.
108**
109** This simple code is not intended to be fast, but to
110** provide power of 2 aligned memory allocations.
111** Since the SCRIPTS processor only supplies 8 bit
112** arithmetic, this allocator allows simple and fast
113** address calculations from the SCRIPTS code.
114** In addition, cache line alignment is guaranteed for
115** power of 2 cache line size.
116** Enhanced in linux-2.3.44 to provide a memory pool
117** per pcidev to support dynamic dma mapping. (I would
118** have preferred a real bus astraction, btw).
119**
120**==========================================================
121*/
122
123#define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
124#if PAGE_SIZE >= 8192
125#define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
126#else
127#define MEMO_PAGE_ORDER 1 /* 2 PAGES maximum */
128#endif
129#define MEMO_FREE_UNUSED /* Free unused pages immediately */
130#define MEMO_WARN 1
131#define MEMO_GFP_FLAGS GFP_ATOMIC
132#define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
133#define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
134#define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
135
136typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
137typedef struct device *m_bush_t; /* Something that addresses DMAable */
138
139typedef struct m_link { /* Link between free memory chunks */
140 struct m_link *next;
141} m_link_s;
142
143typedef struct m_vtob { /* Virtual to Bus address translation */
144 struct m_vtob *next;
145 m_addr_t vaddr;
146 m_addr_t baddr;
147} m_vtob_s;
148#define VTOB_HASH_SHIFT 5
149#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
150#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
151#define VTOB_HASH_CODE(m) \
152 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
153
154typedef struct m_pool { /* Memory pool of a given kind */
155 m_bush_t bush;
156 m_addr_t (*getp)(struct m_pool *);
157 void (*freep)(struct m_pool *, m_addr_t);
158 int nump;
159 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
160 struct m_pool *next;
161 struct m_link h[PAGE_SHIFT-MEMO_SHIFT+MEMO_PAGE_ORDER+1];
162} m_pool_s;
163
164static void *___m_alloc(m_pool_s *mp, int size)
165{
166 int i = 0;
167 int s = (1 << MEMO_SHIFT);
168 int j;
169 m_addr_t a;
170 m_link_s *h = mp->h;
171
172 if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
173 return NULL;
174
175 while (size > s) {
176 s <<= 1;
177 ++i;
178 }
179
180 j = i;
181 while (!h[j].next) {
182 if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
183 h[j].next = (m_link_s *)mp->getp(mp);
184 if (h[j].next)
185 h[j].next->next = NULL;
186 break;
187 }
188 ++j;
189 s <<= 1;
190 }
191 a = (m_addr_t) h[j].next;
192 if (a) {
193 h[j].next = h[j].next->next;
194 while (j > i) {
195 j -= 1;
196 s >>= 1;
197 h[j].next = (m_link_s *) (a+s);
198 h[j].next->next = NULL;
199 }
200 }
201#ifdef DEBUG
202 printk("___m_alloc(%d) = %p\n", size, (void *) a);
203#endif
204 return (void *) a;
205}
206
207static void ___m_free(m_pool_s *mp, void *ptr, int size)
208{
209 int i = 0;
210 int s = (1 << MEMO_SHIFT);
211 m_link_s *q;
212 m_addr_t a, b;
213 m_link_s *h = mp->h;
214
215#ifdef DEBUG
216 printk("___m_free(%p, %d)\n", ptr, size);
217#endif
218
219 if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
220 return;
221
222 while (size > s) {
223 s <<= 1;
224 ++i;
225 }
226
227 a = (m_addr_t) ptr;
228
229 while (1) {
230#ifdef MEMO_FREE_UNUSED
231 if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
232 mp->freep(mp, a);
233 break;
234 }
235#endif
236 b = a ^ s;
237 q = &h[i];
238 while (q->next && q->next != (m_link_s *) b) {
239 q = q->next;
240 }
241 if (!q->next) {
242 ((m_link_s *) a)->next = h[i].next;
243 h[i].next = (m_link_s *) a;
244 break;
245 }
246 q->next = q->next->next;
247 a = a & b;
248 s <<= 1;
249 ++i;
250 }
251}
252
253static DEFINE_SPINLOCK(ncr53c8xx_lock);
254
255static void *__m_calloc2(m_pool_s *mp, int size, char *name, int uflags)
256{
257 void *p;
258
259 p = ___m_alloc(mp, size);
260
261 if (DEBUG_FLAGS & DEBUG_ALLOC)
262 printk ("new %-10s[%4d] @%p.\n", name, size, p);
263
264 if (p)
265 memset(p, 0, size);
266 else if (uflags & MEMO_WARN)
267 printk (NAME53C8XX ": failed to allocate %s[%d]\n", name, size);
268
269 return p;
270}
271
272#define __m_calloc(mp, s, n) __m_calloc2(mp, s, n, MEMO_WARN)
273
274static void __m_free(m_pool_s *mp, void *ptr, int size, char *name)
275{
276 if (DEBUG_FLAGS & DEBUG_ALLOC)
277 printk ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
278
279 ___m_free(mp, ptr, size);
280
281}
282
283/*
284 * With pci bus iommu support, we use a default pool of unmapped memory
285 * for memory we donnot need to DMA from/to and one pool per pcidev for
286 * memory accessed by the PCI chip. `mp0' is the default not DMAable pool.
287 */
288
289static m_addr_t ___mp0_getp(m_pool_s *mp)
290{
291 m_addr_t m = __get_free_pages(MEMO_GFP_FLAGS, MEMO_PAGE_ORDER);
292 if (m)
293 ++mp->nump;
294 return m;
295}
296
297static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
298{
299 free_pages(m, MEMO_PAGE_ORDER);
300 --mp->nump;
301}
302
303static m_pool_s mp0 = {NULL, ___mp0_getp, ___mp0_freep};
304
305/*
306 * DMAable pools.
307 */
308
309/*
310 * With pci bus iommu support, we maintain one pool per pcidev and a
311 * hashed reverse table for virtual to bus physical address translations.
312 */
313static m_addr_t ___dma_getp(m_pool_s *mp)
314{
315 m_addr_t vp;
316 m_vtob_s *vbp;
317
318 vbp = __m_calloc(&mp0, sizeof(*vbp), "VTOB");
319 if (vbp) {
320 dma_addr_t daddr;
321 vp = (m_addr_t) dma_alloc_coherent(mp->bush,
322 PAGE_SIZE<<MEMO_PAGE_ORDER,
323 &daddr, GFP_ATOMIC);
324 if (vp) {
325 int hc = VTOB_HASH_CODE(vp);
326 vbp->vaddr = vp;
327 vbp->baddr = daddr;
328 vbp->next = mp->vtob[hc];
329 mp->vtob[hc] = vbp;
330 ++mp->nump;
331 return vp;
332 }
333 }
334 if (vbp)
335 __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
336 return 0;
337}
338
339static void ___dma_freep(m_pool_s *mp, m_addr_t m)
340{
341 m_vtob_s **vbpp, *vbp;
342 int hc = VTOB_HASH_CODE(m);
343
344 vbpp = &mp->vtob[hc];
345 while (*vbpp && (*vbpp)->vaddr != m)
346 vbpp = &(*vbpp)->next;
347 if (*vbpp) {
348 vbp = *vbpp;
349 *vbpp = (*vbpp)->next;
350 dma_free_coherent(mp->bush, PAGE_SIZE<<MEMO_PAGE_ORDER,
351 (void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
352 __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
353 --mp->nump;
354 }
355}
356
357static inline m_pool_s *___get_dma_pool(m_bush_t bush)
358{
359 m_pool_s *mp;
360 for (mp = mp0.next; mp && mp->bush != bush; mp = mp->next);
361 return mp;
362}
363
364static m_pool_s *___cre_dma_pool(m_bush_t bush)
365{
366 m_pool_s *mp;
367 mp = __m_calloc(&mp0, sizeof(*mp), "MPOOL");
368 if (mp) {
369 memset(mp, 0, sizeof(*mp));
370 mp->bush = bush;
371 mp->getp = ___dma_getp;
372 mp->freep = ___dma_freep;
373 mp->next = mp0.next;
374 mp0.next = mp;
375 }
376 return mp;
377}
378
379static void ___del_dma_pool(m_pool_s *p)
380{
381 struct m_pool **pp = &mp0.next;
382
383 while (*pp && *pp != p)
384 pp = &(*pp)->next;
385 if (*pp) {
386 *pp = (*pp)->next;
387 __m_free(&mp0, p, sizeof(*p), "MPOOL");
388 }
389}
390
391static void *__m_calloc_dma(m_bush_t bush, int size, char *name)
392{
393 u_long flags;
394 struct m_pool *mp;
395 void *m = NULL;
396
397 spin_lock_irqsave(&ncr53c8xx_lock, flags);
398 mp = ___get_dma_pool(bush);
399 if (!mp)
400 mp = ___cre_dma_pool(bush);
401 if (mp)
402 m = __m_calloc(mp, size, name);
403 if (mp && !mp->nump)
404 ___del_dma_pool(mp);
405 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
406
407 return m;
408}
409
410static void __m_free_dma(m_bush_t bush, void *m, int size, char *name)
411{
412 u_long flags;
413 struct m_pool *mp;
414
415 spin_lock_irqsave(&ncr53c8xx_lock, flags);
416 mp = ___get_dma_pool(bush);
417 if (mp)
418 __m_free(mp, m, size, name);
419 if (mp && !mp->nump)
420 ___del_dma_pool(mp);
421 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
422}
423
424static m_addr_t __vtobus(m_bush_t bush, void *m)
425{
426 u_long flags;
427 m_pool_s *mp;
428 int hc = VTOB_HASH_CODE(m);
429 m_vtob_s *vp = NULL;
430 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
431
432 spin_lock_irqsave(&ncr53c8xx_lock, flags);
433 mp = ___get_dma_pool(bush);
434 if (mp) {
435 vp = mp->vtob[hc];
436 while (vp && (m_addr_t) vp->vaddr != a)
437 vp = vp->next;
438 }
439 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
440 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
441}
442
443#define _m_calloc_dma(np, s, n) __m_calloc_dma(np->dev, s, n)
444#define _m_free_dma(np, p, s, n) __m_free_dma(np->dev, p, s, n)
445#define m_calloc_dma(s, n) _m_calloc_dma(np, s, n)
446#define m_free_dma(p, s, n) _m_free_dma(np, p, s, n)
447#define _vtobus(np, p) __vtobus(np->dev, p)
448#define vtobus(p) _vtobus(np, p)
449
450/*
451 * Deal with DMA mapping/unmapping.
452 */
453
454/* To keep track of the dma mapping (sg/single) that has been set */
455#define __data_mapped SCp.phase
456#define __data_mapping SCp.have_data_in
457
458static void __unmap_scsi_data(struct device *dev, struct scsi_cmnd *cmd)
459{
460 switch(cmd->__data_mapped) {
461 case 2:
462 dma_unmap_sg(dev, cmd->buffer, cmd->use_sg,
463 cmd->sc_data_direction);
464 break;
465 case 1:
466 dma_unmap_single(dev, cmd->__data_mapping,
467 cmd->request_bufflen,
468 cmd->sc_data_direction);
469 break;
470 }
471 cmd->__data_mapped = 0;
472}
473
474static u_long __map_scsi_single_data(struct device *dev, struct scsi_cmnd *cmd)
475{
476 dma_addr_t mapping;
477
478 if (cmd->request_bufflen == 0)
479 return 0;
480
481 mapping = dma_map_single(dev, cmd->request_buffer,
482 cmd->request_bufflen,
483 cmd->sc_data_direction);
484 cmd->__data_mapped = 1;
485 cmd->__data_mapping = mapping;
486
487 return mapping;
488}
489
490static int __map_scsi_sg_data(struct device *dev, struct scsi_cmnd *cmd)
491{
492 int use_sg;
493
494 if (cmd->use_sg == 0)
495 return 0;
496
497 use_sg = dma_map_sg(dev, cmd->buffer, cmd->use_sg,
498 cmd->sc_data_direction);
499 cmd->__data_mapped = 2;
500 cmd->__data_mapping = use_sg;
501
502 return use_sg;
503}
504
505#define unmap_scsi_data(np, cmd) __unmap_scsi_data(np->dev, cmd)
506#define map_scsi_single_data(np, cmd) __map_scsi_single_data(np->dev, cmd)
507#define map_scsi_sg_data(np, cmd) __map_scsi_sg_data(np->dev, cmd)
508
509/*==========================================================
510**
511** Driver setup.
512**
513** This structure is initialized from linux config
514** options. It can be overridden at boot-up by the boot
515** command line.
516**
517**==========================================================
518*/
519static struct ncr_driver_setup
520 driver_setup = SCSI_NCR_DRIVER_SETUP;
521
522#ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
523static struct ncr_driver_setup
524 driver_safe_setup __initdata = SCSI_NCR_DRIVER_SAFE_SETUP;
525#endif
526
527#define initverbose (driver_setup.verbose)
528#define bootverbose (np->verbose)
529
530
531/*===================================================================
532**
533** Driver setup from the boot command line
534**
535**===================================================================
536*/
537
538#ifdef MODULE
539#define ARG_SEP ' '
540#else
541#define ARG_SEP ','
542#endif
543
544#define OPT_TAGS 1
545#define OPT_MASTER_PARITY 2
546#define OPT_SCSI_PARITY 3
547#define OPT_DISCONNECTION 4
548#define OPT_SPECIAL_FEATURES 5
549#define OPT_UNUSED_1 6
550#define OPT_FORCE_SYNC_NEGO 7
551#define OPT_REVERSE_PROBE 8
552#define OPT_DEFAULT_SYNC 9
553#define OPT_VERBOSE 10
554#define OPT_DEBUG 11
555#define OPT_BURST_MAX 12
556#define OPT_LED_PIN 13
557#define OPT_MAX_WIDE 14
558#define OPT_SETTLE_DELAY 15
559#define OPT_DIFF_SUPPORT 16
560#define OPT_IRQM 17
561#define OPT_PCI_FIX_UP 18
562#define OPT_BUS_CHECK 19
563#define OPT_OPTIMIZE 20
564#define OPT_RECOVERY 21
565#define OPT_SAFE_SETUP 22
566#define OPT_USE_NVRAM 23
567#define OPT_EXCLUDE 24
568#define OPT_HOST_ID 25
569
570#ifdef SCSI_NCR_IARB_SUPPORT
571#define OPT_IARB 26
572#endif
573
574static char setup_token[] __initdata =
575 "tags:" "mpar:"
576 "spar:" "disc:"
577 "specf:" "ultra:"
578 "fsn:" "revprob:"
579 "sync:" "verb:"
580 "debug:" "burst:"
581 "led:" "wide:"
582 "settle:" "diff:"
583 "irqm:" "pcifix:"
584 "buschk:" "optim:"
585 "recovery:"
586 "safe:" "nvram:"
587 "excl:" "hostid:"
588#ifdef SCSI_NCR_IARB_SUPPORT
589 "iarb:"
590#endif
591 ; /* DONNOT REMOVE THIS ';' */
592
593#ifdef MODULE
594#define ARG_SEP ' '
595#else
596#define ARG_SEP ','
597#endif
598
599static int __init get_setup_token(char *p)
600{
601 char *cur = setup_token;
602 char *pc;
603 int i = 0;
604
605 while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
606 ++pc;
607 ++i;
608 if (!strncmp(p, cur, pc - cur))
609 return i;
610 cur = pc;
611 }
612 return 0;
613}
614
615
616static int __init sym53c8xx__setup(char *str)
617{
618#ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
619 char *cur = str;
620 char *pc, *pv;
621 int i, val, c;
622 int xi = 0;
623
624 while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
625 char *pe;
626
627 val = 0;
628 pv = pc;
629 c = *++pv;
630
631 if (c == 'n')
632 val = 0;
633 else if (c == 'y')
634 val = 1;
635 else
636 val = (int) simple_strtoul(pv, &pe, 0);
637
638 switch (get_setup_token(cur)) {
639 case OPT_TAGS:
640 driver_setup.default_tags = val;
641 if (pe && *pe == '/') {
642 i = 0;
643 while (*pe && *pe != ARG_SEP &&
644 i < sizeof(driver_setup.tag_ctrl)-1) {
645 driver_setup.tag_ctrl[i++] = *pe++;
646 }
647 driver_setup.tag_ctrl[i] = '\0';
648 }
649 break;
650 case OPT_MASTER_PARITY:
651 driver_setup.master_parity = val;
652 break;
653 case OPT_SCSI_PARITY:
654 driver_setup.scsi_parity = val;
655 break;
656 case OPT_DISCONNECTION:
657 driver_setup.disconnection = val;
658 break;
659 case OPT_SPECIAL_FEATURES:
660 driver_setup.special_features = val;
661 break;
662 case OPT_FORCE_SYNC_NEGO:
663 driver_setup.force_sync_nego = val;
664 break;
665 case OPT_REVERSE_PROBE:
666 driver_setup.reverse_probe = val;
667 break;
668 case OPT_DEFAULT_SYNC:
669 driver_setup.default_sync = val;
670 break;
671 case OPT_VERBOSE:
672 driver_setup.verbose = val;
673 break;
674 case OPT_DEBUG:
675 driver_setup.debug = val;
676 break;
677 case OPT_BURST_MAX:
678 driver_setup.burst_max = val;
679 break;
680 case OPT_LED_PIN:
681 driver_setup.led_pin = val;
682 break;
683 case OPT_MAX_WIDE:
684 driver_setup.max_wide = val? 1:0;
685 break;
686 case OPT_SETTLE_DELAY:
687 driver_setup.settle_delay = val;
688 break;
689 case OPT_DIFF_SUPPORT:
690 driver_setup.diff_support = val;
691 break;
692 case OPT_IRQM:
693 driver_setup.irqm = val;
694 break;
695 case OPT_PCI_FIX_UP:
696 driver_setup.pci_fix_up = val;
697 break;
698 case OPT_BUS_CHECK:
699 driver_setup.bus_check = val;
700 break;
701 case OPT_OPTIMIZE:
702 driver_setup.optimize = val;
703 break;
704 case OPT_RECOVERY:
705 driver_setup.recovery = val;
706 break;
707 case OPT_USE_NVRAM:
708 driver_setup.use_nvram = val;
709 break;
710 case OPT_SAFE_SETUP:
711 memcpy(&driver_setup, &driver_safe_setup,
712 sizeof(driver_setup));
713 break;
714 case OPT_EXCLUDE:
715 if (xi < SCSI_NCR_MAX_EXCLUDES)
716 driver_setup.excludes[xi++] = val;
717 break;
718 case OPT_HOST_ID:
719 driver_setup.host_id = val;
720 break;
721#ifdef SCSI_NCR_IARB_SUPPORT
722 case OPT_IARB:
723 driver_setup.iarb = val;
724 break;
725#endif
726 default:
727 printk("sym53c8xx_setup: unexpected boot option '%.*s' ignored\n", (int)(pc-cur+1), cur);
728 break;
729 }
730
731 if ((cur = strchr(cur, ARG_SEP)) != NULL)
732 ++cur;
733 }
734#endif /* SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT */
735 return 1;
736}
737
738/*===================================================================
739**
740** Get device queue depth from boot command line.
741**
742**===================================================================
743*/
744#define DEF_DEPTH (driver_setup.default_tags)
745#define ALL_TARGETS -2
746#define NO_TARGET -1
747#define ALL_LUNS -2
748#define NO_LUN -1
749
750static int device_queue_depth(int unit, int target, int lun)
751{
752 int c, h, t, u, v;
753 char *p = driver_setup.tag_ctrl;
754 char *ep;
755
756 h = -1;
757 t = NO_TARGET;
758 u = NO_LUN;
759 while ((c = *p++) != 0) {
760 v = simple_strtoul(p, &ep, 0);
761 switch(c) {
762 case '/':
763 ++h;
764 t = ALL_TARGETS;
765 u = ALL_LUNS;
766 break;
767 case 't':
768 if (t != target)
769 t = (target == v) ? v : NO_TARGET;
770 u = ALL_LUNS;
771 break;
772 case 'u':
773 if (u != lun)
774 u = (lun == v) ? v : NO_LUN;
775 break;
776 case 'q':
777 if (h == unit &&
778 (t == ALL_TARGETS || t == target) &&
779 (u == ALL_LUNS || u == lun))
780 return v;
781 break;
782 case '-':
783 t = ALL_TARGETS;
784 u = ALL_LUNS;
785 break;
786 default:
787 break;
788 }
789 p = ep;
790 }
791 return DEF_DEPTH;
792}
diff --git a/drivers/scsi/sym53c8xx_defs.h b/drivers/scsi/sym53c8xx_defs.h
deleted file mode 100644
index 139cd0e12e62..000000000000
--- a/drivers/scsi/sym53c8xx_defs.h
+++ /dev/null
@@ -1,1320 +0,0 @@
1/******************************************************************************
2** High Performance device driver for the Symbios 53C896 controller.
3**
4** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
5**
6** This driver also supports all the Symbios 53C8XX controller family,
7** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8** revisions of 53C815 controllers.
9**
10** This driver is based on the Linux port of the FreeBSD ncr driver.
11**
12** Copyright (C) 1994 Wolfgang Stanglmeier
13**
14**-----------------------------------------------------------------------------
15**
16** This program is free software; you can redistribute it and/or modify
17** it under the terms of the GNU General Public License as published by
18** the Free Software Foundation; either version 2 of the License, or
19** (at your option) any later version.
20**
21** This program is distributed in the hope that it will be useful,
22** but WITHOUT ANY WARRANTY; without even the implied warranty of
23** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24** GNU General Public License for more details.
25**
26** You should have received a copy of the GNU General Public License
27** along with this program; if not, write to the Free Software
28** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29**
30**-----------------------------------------------------------------------------
31**
32** The Linux port of the FreeBSD ncr driver has been achieved in
33** november 1995 by:
34**
35** Gerard Roudier <groudier@free.fr>
36**
37** Being given that this driver originates from the FreeBSD version, and
38** in order to keep synergy on both, any suggested enhancements and corrections
39** received on Linux are automatically a potential candidate for the FreeBSD
40** version.
41**
42** The original driver has been written for 386bsd and FreeBSD by
43** Wolfgang Stanglmeier <wolf@cologne.de>
44** Stefan Esser <se@mi.Uni-Koeln.de>
45**
46**-----------------------------------------------------------------------------
47**
48** Major contributions:
49** --------------------
50**
51** NVRAM detection and reading.
52** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53**
54** Added support for MIPS big endian systems.
55** Carsten Langgaard, carstenl@mips.com
56** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
57**
58** Added support for HP PARISC big endian systems.
59** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
60**
61*******************************************************************************
62*/
63
64#ifndef SYM53C8XX_DEFS_H
65#define SYM53C8XX_DEFS_H
66
67#include <linux/config.h>
68
69/*
70** If you want a driver as small as possible, donnot define the
71** following options.
72*/
73#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
74#define SCSI_NCR_DEBUG_INFO_SUPPORT
75
76/*
77** To disable integrity checking, do not define the
78** following option.
79*/
80#ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
81# define SCSI_NCR_ENABLE_INTEGRITY_CHECK
82#endif
83
84/* ---------------------------------------------------------------------
85** Take into account kernel configured parameters.
86** Most of these options can be overridden at startup by a command line.
87** ---------------------------------------------------------------------
88*/
89
90/*
91 * For Ultra2 and Ultra3 SCSI support option, use special features.
92 *
93 * Value (default) means:
94 * bit 0 : all features enabled, except:
95 * bit 1 : PCI Write And Invalidate.
96 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
97 *
98 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
99 * enabled by the driver.
100 */
101#define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
102
103#define SCSI_NCR_MAX_SYNC (80)
104
105/*
106 * Allow tags from 2 to 256, default 8
107 */
108#ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
109#if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
110#define SCSI_NCR_MAX_TAGS (2)
111#elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
112#define SCSI_NCR_MAX_TAGS (256)
113#else
114#define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
115#endif
116#else
117#define SCSI_NCR_MAX_TAGS (8)
118#endif
119
120/*
121 * Allow tagged command queuing support if configured with default number
122 * of tags set to max (see above).
123 */
124#ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
125#define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
126#elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
127#define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
128#else
129#define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
130#endif
131
132/*
133 * Immediate arbitration
134 */
135#if defined(CONFIG_SCSI_NCR53C8XX_IARB)
136#define SCSI_NCR_IARB_SUPPORT
137#endif
138
139/*
140 * Sync transfer frequency at startup.
141 * Allow from 5Mhz to 80Mhz default 20 Mhz.
142 */
143#ifndef CONFIG_SCSI_NCR53C8XX_SYNC
144#define CONFIG_SCSI_NCR53C8XX_SYNC (20)
145#elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
146#undef CONFIG_SCSI_NCR53C8XX_SYNC
147#define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
148#endif
149
150#if CONFIG_SCSI_NCR53C8XX_SYNC == 0
151#define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
152#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
153#define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
154#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
155#define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
156#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
157#define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
158#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
159#define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
160#else
161#define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
162#endif
163
164/*
165 * Disallow disconnections at boot-up
166 */
167#ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
168#define SCSI_NCR_SETUP_DISCONNECTION (0)
169#else
170#define SCSI_NCR_SETUP_DISCONNECTION (1)
171#endif
172
173/*
174 * Force synchronous negotiation for all targets
175 */
176#ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
177#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
178#else
179#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
180#endif
181
182/*
183 * Disable master parity checking (flawed hardwares need that)
184 */
185#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
186#define SCSI_NCR_SETUP_MASTER_PARITY (0)
187#else
188#define SCSI_NCR_SETUP_MASTER_PARITY (1)
189#endif
190
191/*
192 * Disable scsi parity checking (flawed devices may need that)
193 */
194#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
195#define SCSI_NCR_SETUP_SCSI_PARITY (0)
196#else
197#define SCSI_NCR_SETUP_SCSI_PARITY (1)
198#endif
199
200/*
201 * Settle time after reset at boot-up
202 */
203#define SCSI_NCR_SETUP_SETTLE_TIME (2)
204
205/*
206** Bridge quirks work-around option defaulted to 1.
207*/
208#ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
209#define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
210#endif
211
212/*
213** Work-around common bridge misbehaviour.
214**
215** - Do not flush posted writes in the opposite
216** direction on read.
217** - May reorder DMA writes to memory.
218**
219** This option should not affect performances
220** significantly, so it is the default.
221*/
222#if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
223#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
224#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
225#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
226
227/*
228** Same as option 1, but also deal with
229** misconfigured interrupts.
230**
231** - Edge triggerred instead of level sensitive.
232** - No interrupt line connected.
233** - IRQ number misconfigured.
234**
235** If no interrupt is delivered, the driver will
236** catch the interrupt conditions 10 times per
237** second. No need to say that this option is
238** not recommended.
239*/
240#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
241#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
242#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
243#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
244#define SCSI_NCR_PCIQ_BROKEN_INTR
245
246/*
247** Some bridge designers decided to flush
248** everything prior to deliver the interrupt.
249** This option tries to deal with such a
250** behaviour.
251*/
252#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
253#define SCSI_NCR_PCIQ_SYNC_ON_INTR
254#endif
255
256/*
257** Other parameters not configurable with "make config"
258** Avoid to change these constants, unless you know what you are doing.
259*/
260
261#define SCSI_NCR_ALWAYS_SIMPLE_TAG
262#define SCSI_NCR_MAX_SCATTER (127)
263#define SCSI_NCR_MAX_TARGET (16)
264
265/*
266** Compute some desirable value for CAN_QUEUE
267** and CMD_PER_LUN.
268** The driver will use lower values if these
269** ones appear to be too large.
270*/
271#define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
272#define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
273
274#define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
275#define SCSI_NCR_TIMER_INTERVAL (HZ)
276
277#if 1 /* defined CONFIG_SCSI_MULTI_LUN */
278#define SCSI_NCR_MAX_LUN (16)
279#else
280#define SCSI_NCR_MAX_LUN (1)
281#endif
282
283/*
284 * IO functions definition for big/little endian CPU support.
285 * For now, the NCR is only supported in little endian addressing mode,
286 */
287
288#ifdef __BIG_ENDIAN
289
290#define inw_l2b inw
291#define inl_l2b inl
292#define outw_b2l outw
293#define outl_b2l outl
294
295#define readb_raw readb
296#define writeb_raw writeb
297
298#if defined(SCSI_NCR_BIG_ENDIAN)
299#define readw_l2b __raw_readw
300#define readl_l2b __raw_readl
301#define writew_b2l __raw_writew
302#define writel_b2l __raw_writel
303#define readw_raw __raw_readw
304#define readl_raw __raw_readl
305#define writew_raw __raw_writew
306#define writel_raw __raw_writel
307#else /* Other big-endian */
308#define readw_l2b readw
309#define readl_l2b readl
310#define writew_b2l writew
311#define writel_b2l writel
312#define readw_raw readw
313#define readl_raw readl
314#define writew_raw writew
315#define writel_raw writel
316#endif
317
318#else /* little endian */
319
320#define inw_raw inw
321#define inl_raw inl
322#define outw_raw outw
323#define outl_raw outl
324
325#define readb_raw readb
326#define readw_raw readw
327#define readl_raw readl
328#define writeb_raw writeb
329#define writew_raw writew
330#define writel_raw writel
331
332#endif
333
334#if !defined(__hppa__) && !defined(__mips__)
335#ifdef SCSI_NCR_BIG_ENDIAN
336#error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
337#endif
338#endif
339
340#define MEMORY_BARRIER() mb()
341
342
343/*
344 * If the NCR uses big endian addressing mode over the
345 * PCI, actual io register addresses for byte and word
346 * accesses must be changed according to lane routing.
347 * Btw, ncr_offb() and ncr_offw() macros only apply to
348 * constants and so donnot generate bloated code.
349 */
350
351#if defined(SCSI_NCR_BIG_ENDIAN)
352
353#define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
354#define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
355
356#else
357
358#define ncr_offb(o) (o)
359#define ncr_offw(o) (o)
360
361#endif
362
363/*
364 * If the CPU and the NCR use same endian-ness addressing,
365 * no byte reordering is needed for script patching.
366 * Macro cpu_to_scr() is to be used for script patching.
367 * Macro scr_to_cpu() is to be used for getting a DWORD
368 * from the script.
369 */
370
371#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
372
373#define cpu_to_scr(dw) cpu_to_le32(dw)
374#define scr_to_cpu(dw) le32_to_cpu(dw)
375
376#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
377
378#define cpu_to_scr(dw) cpu_to_be32(dw)
379#define scr_to_cpu(dw) be32_to_cpu(dw)
380
381#else
382
383#define cpu_to_scr(dw) (dw)
384#define scr_to_cpu(dw) (dw)
385
386#endif
387
388/*
389 * Access to the controller chip.
390 *
391 * If the CPU and the NCR use same endian-ness addressing,
392 * no byte reordering is needed for accessing chip io
393 * registers. Functions suffixed by '_raw' are assumed
394 * to access the chip over the PCI without doing byte
395 * reordering. Functions suffixed by '_l2b' are
396 * assumed to perform little-endian to big-endian byte
397 * reordering, those suffixed by '_b2l' blah, blah,
398 * blah, ...
399 */
400
401/*
402 * MEMORY mapped IO input / output
403 */
404
405#define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
406#define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
407
408#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
409
410#define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
411#define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
412
413#define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
414#define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
415
416#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
417
418#define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
419#define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
420
421#define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
422#define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
423
424#else
425
426#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
427/* Only 8 or 32 bit transfers allowed */
428#define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
429#else
430#define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
431#endif
432#define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
433
434#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
435/* Only 8 or 32 bit transfers allowed */
436#define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
437#else
438#define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
439#endif
440#define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
441
442#endif
443
444#define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
445#define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
446#define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
447
448#define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
449#define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
450#define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
451
452/*
453 * Set bit field ON, OFF
454 */
455
456#define OUTONB(r, m) OUTB(r, INB(r) | (m))
457#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
458#define OUTONW(r, m) OUTW(r, INW(r) | (m))
459#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
460#define OUTONL(r, m) OUTL(r, INL(r) | (m))
461#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
462
463/*
464 * We normally want the chip to have a consistent view
465 * of driver internal data structures when we restart it.
466 * Thus these macros.
467 */
468#define OUTL_DSP(v) \
469 do { \
470 MEMORY_BARRIER(); \
471 OUTL (nc_dsp, (v)); \
472 } while (0)
473
474#define OUTONB_STD() \
475 do { \
476 MEMORY_BARRIER(); \
477 OUTONB (nc_dcntl, (STD|NOCOM)); \
478 } while (0)
479
480
481/*
482** NCR53C8XX devices features table.
483*/
484struct ncr_chip {
485 unsigned short revision_id;
486 unsigned char burst_max; /* log-base-2 of max burst */
487 unsigned char offset_max;
488 unsigned char nr_divisor;
489 unsigned int features;
490#define FE_LED0 (1<<0)
491#define FE_WIDE (1<<1) /* Wide data transfers */
492#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
493#define FE_DBLR (1<<4) /* Clock doubler present */
494#define FE_QUAD (1<<5) /* Clock quadrupler present */
495#define FE_ERL (1<<6) /* Enable read line */
496#define FE_CLSE (1<<7) /* Cache line size enable */
497#define FE_WRIE (1<<8) /* Write & Invalidate enable */
498#define FE_ERMP (1<<9) /* Enable read multiple */
499#define FE_BOF (1<<10) /* Burst opcode fetch */
500#define FE_DFS (1<<11) /* DMA fifo size */
501#define FE_PFEN (1<<12) /* Prefetch enable */
502#define FE_LDSTR (1<<13) /* Load/Store supported */
503#define FE_RAM (1<<14) /* On chip RAM present */
504#define FE_VARCLK (1<<15) /* SCSI clock may vary */
505#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
506#define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
507#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
508#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
509#define FE_LEDC (1<<20) /* Hardware control of LED */
510#define FE_DIFF (1<<21) /* Support Differential SCSI */
511#define FE_66MHZ (1<<23) /* 66MHz PCI Support */
512#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
513#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
514#define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
515#define FE_EHP (1<<27) /* 720: Even host parity */
516#define FE_MUX (1<<28) /* 720: Multiplexed bus */
517#define FE_EA (1<<29) /* 720: Enable Ack */
518
519#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
520#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
521#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
522};
523
524
525/*
526** Driver setup structure.
527**
528** This structure is initialized from linux config options.
529** It can be overridden at boot-up by the boot command line.
530*/
531#define SCSI_NCR_MAX_EXCLUDES 8
532struct ncr_driver_setup {
533 u8 master_parity;
534 u8 scsi_parity;
535 u8 disconnection;
536 u8 special_features;
537 u8 force_sync_nego;
538 u8 reverse_probe;
539 u8 pci_fix_up;
540 u8 use_nvram;
541 u8 verbose;
542 u8 default_tags;
543 u16 default_sync;
544 u16 debug;
545 u8 burst_max;
546 u8 led_pin;
547 u8 max_wide;
548 u8 settle_delay;
549 u8 diff_support;
550 u8 irqm;
551 u8 bus_check;
552 u8 optimize;
553 u8 recovery;
554 u8 host_id;
555 u16 iarb;
556 u32 excludes[SCSI_NCR_MAX_EXCLUDES];
557 char tag_ctrl[100];
558};
559
560/*
561** Initial setup.
562** Can be overriden at startup by a command line.
563*/
564#define SCSI_NCR_DRIVER_SETUP \
565{ \
566 SCSI_NCR_SETUP_MASTER_PARITY, \
567 SCSI_NCR_SETUP_SCSI_PARITY, \
568 SCSI_NCR_SETUP_DISCONNECTION, \
569 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
570 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
571 0, \
572 0, \
573 1, \
574 0, \
575 SCSI_NCR_SETUP_DEFAULT_TAGS, \
576 SCSI_NCR_SETUP_DEFAULT_SYNC, \
577 0x00, \
578 7, \
579 0, \
580 1, \
581 SCSI_NCR_SETUP_SETTLE_TIME, \
582 0, \
583 0, \
584 1, \
585 0, \
586 0, \
587 255, \
588 0x00 \
589}
590
591/*
592** Boot fail safe setup.
593** Override initial setup from boot command line:
594** ncr53c8xx=safe:y
595*/
596#define SCSI_NCR_DRIVER_SAFE_SETUP \
597{ \
598 0, \
599 1, \
600 0, \
601 0, \
602 0, \
603 0, \
604 0, \
605 1, \
606 2, \
607 0, \
608 255, \
609 0x00, \
610 255, \
611 0, \
612 0, \
613 10, \
614 1, \
615 1, \
616 1, \
617 0, \
618 0, \
619 255 \
620}
621
622/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
623
624/*-----------------------------------------------------------------
625**
626** The ncr 53c810 register structure.
627**
628**-----------------------------------------------------------------
629*/
630
631struct ncr_reg {
632/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
633
634/*01*/ u8 nc_scntl1; /* no reset */
635 #define ISCON 0x10 /* connected to scsi */
636 #define CRST 0x08 /* force reset */
637 #define IARB 0x02 /* immediate arbitration */
638
639/*02*/ u8 nc_scntl2; /* no disconnect expected */
640 #define SDU 0x80 /* cmd: disconnect will raise error */
641 #define CHM 0x40 /* sta: chained mode */
642 #define WSS 0x08 /* sta: wide scsi send [W]*/
643 #define WSR 0x01 /* sta: wide scsi received [W]*/
644
645/*03*/ u8 nc_scntl3; /* cnf system clock dependent */
646 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
647 #define ULTRA 0x80 /* cmd: ULTRA enable */
648 /* bits 0-2, 7 rsvd for C1010 */
649
650/*04*/ u8 nc_scid; /* cnf host adapter scsi address */
651 #define RRE 0x40 /* r/w:e enable response to resel. */
652 #define SRE 0x20 /* r/w:e enable response to select */
653
654/*05*/ u8 nc_sxfer; /* ### Sync speed and count */
655 /* bits 6-7 rsvd for C1010 */
656
657/*06*/ u8 nc_sdid; /* ### Destination-ID */
658
659/*07*/ u8 nc_gpreg; /* ??? IO-Pins */
660
661/*08*/ u8 nc_sfbr; /* ### First byte in phase */
662
663/*09*/ u8 nc_socl;
664 #define CREQ 0x80 /* r/w: SCSI-REQ */
665 #define CACK 0x40 /* r/w: SCSI-ACK */
666 #define CBSY 0x20 /* r/w: SCSI-BSY */
667 #define CSEL 0x10 /* r/w: SCSI-SEL */
668 #define CATN 0x08 /* r/w: SCSI-ATN */
669 #define CMSG 0x04 /* r/w: SCSI-MSG */
670 #define CC_D 0x02 /* r/w: SCSI-C_D */
671 #define CI_O 0x01 /* r/w: SCSI-I_O */
672
673/*0a*/ u8 nc_ssid;
674
675/*0b*/ u8 nc_sbcl;
676
677/*0c*/ u8 nc_dstat;
678 #define DFE 0x80 /* sta: dma fifo empty */
679 #define MDPE 0x40 /* int: master data parity error */
680 #define BF 0x20 /* int: script: bus fault */
681 #define ABRT 0x10 /* int: script: command aborted */
682 #define SSI 0x08 /* int: script: single step */
683 #define SIR 0x04 /* int: script: interrupt instruct. */
684 #define IID 0x01 /* int: script: illegal instruct. */
685
686/*0d*/ u8 nc_sstat0;
687 #define ILF 0x80 /* sta: data in SIDL register lsb */
688 #define ORF 0x40 /* sta: data in SODR register lsb */
689 #define OLF 0x20 /* sta: data in SODL register lsb */
690 #define AIP 0x10 /* sta: arbitration in progress */
691 #define LOA 0x08 /* sta: arbitration lost */
692 #define WOA 0x04 /* sta: arbitration won */
693 #define IRST 0x02 /* sta: scsi reset signal */
694 #define SDP 0x01 /* sta: scsi parity signal */
695
696/*0e*/ u8 nc_sstat1;
697 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
698
699/*0f*/ u8 nc_sstat2;
700 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
701 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
702 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
703 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
704 #define LDSC 0x02 /* sta: disconnect & reconnect */
705
706/*10*/ u8 nc_dsa; /* --> Base page */
707/*11*/ u8 nc_dsa1;
708/*12*/ u8 nc_dsa2;
709/*13*/ u8 nc_dsa3;
710
711/*14*/ u8 nc_istat; /* --> Main Command and status */
712 #define CABRT 0x80 /* cmd: abort current operation */
713 #define SRST 0x40 /* mod: reset chip */
714 #define SIGP 0x20 /* r/w: message from host to ncr */
715 #define SEM 0x10 /* r/w: message between host + ncr */
716 #define CON 0x08 /* sta: connected to scsi */
717 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
718 #define SIP 0x02 /* sta: scsi-interrupt */
719 #define DIP 0x01 /* sta: host/script interrupt */
720
721/*15*/ u8 nc_istat1; /* 896 and later cores only */
722 #define FLSH 0x04 /* sta: chip is flushing */
723 #define SRUN 0x02 /* sta: scripts are running */
724 #define SIRQD 0x01 /* r/w: disable INT pin */
725
726/*16*/ u8 nc_mbox0; /* 896 and later cores only */
727/*17*/ u8 nc_mbox1; /* 896 and later cores only */
728
729/*18*/ u8 nc_ctest0;
730 #define EHP 0x04 /* 720 even host parity */
731/*19*/ u8 nc_ctest1;
732
733/*1a*/ u8 nc_ctest2;
734 #define CSIGP 0x40
735 /* bits 0-2,7 rsvd for C1010 */
736
737/*1b*/ u8 nc_ctest3;
738 #define FLF 0x08 /* cmd: flush dma fifo */
739 #define CLF 0x04 /* cmd: clear dma fifo */
740 #define FM 0x02 /* mod: fetch pin mode */
741 #define WRIE 0x01 /* mod: write and invalidate enable */
742 /* bits 4-7 rsvd for C1010 */
743
744/*1c*/ u32 nc_temp; /* ### Temporary stack */
745
746/*20*/ u8 nc_dfifo;
747/*21*/ u8 nc_ctest4;
748 #define MUX 0x80 /* 720 host bus multiplex mode */
749 #define BDIS 0x80 /* mod: burst disable */
750 #define MPEE 0x08 /* mod: master parity error enable */
751
752/*22*/ u8 nc_ctest5;
753 #define DFS 0x20 /* mod: dma fifo size */
754 /* bits 0-1, 3-7 rsvd for C1010 */
755/*23*/ u8 nc_ctest6;
756
757/*24*/ u32 nc_dbc; /* ### Byte count and command */
758/*28*/ u32 nc_dnad; /* ### Next command register */
759/*2c*/ u32 nc_dsp; /* --> Script Pointer */
760/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
761
762/*34*/ u8 nc_scratcha; /* Temporary register a */
763/*35*/ u8 nc_scratcha1;
764/*36*/ u8 nc_scratcha2;
765/*37*/ u8 nc_scratcha3;
766
767/*38*/ u8 nc_dmode;
768 #define BL_2 0x80 /* mod: burst length shift value +2 */
769 #define BL_1 0x40 /* mod: burst length shift value +1 */
770 #define ERL 0x08 /* mod: enable read line */
771 #define ERMP 0x04 /* mod: enable read multiple */
772 #define BOF 0x02 /* mod: burst op code fetch */
773
774/*39*/ u8 nc_dien;
775/*3a*/ u8 nc_sbr;
776
777/*3b*/ u8 nc_dcntl; /* --> Script execution control */
778 #define CLSE 0x80 /* mod: cache line size enable */
779 #define PFF 0x40 /* cmd: pre-fetch flush */
780 #define PFEN 0x20 /* mod: pre-fetch enable */
781 #define EA 0x20 /* mod: 720 enable-ack */
782 #define SSM 0x10 /* mod: single step mode */
783 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
784 #define STD 0x04 /* cmd: start dma mode */
785 #define IRQD 0x02 /* mod: irq disable */
786 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
787 /* bits 0-1 rsvd for C1010 */
788
789/*3c*/ u32 nc_adder;
790
791/*40*/ u16 nc_sien; /* -->: interrupt enable */
792/*42*/ u16 nc_sist; /* <--: interrupt status */
793 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
794 #define STO 0x0400/* sta: timeout (select) */
795 #define GEN 0x0200/* sta: timeout (general) */
796 #define HTH 0x0100/* sta: timeout (handshake) */
797 #define MA 0x80 /* sta: phase mismatch */
798 #define CMP 0x40 /* sta: arbitration complete */
799 #define SEL 0x20 /* sta: selected by another device */
800 #define RSL 0x10 /* sta: reselected by another device*/
801 #define SGE 0x08 /* sta: gross error (over/underflow)*/
802 #define UDC 0x04 /* sta: unexpected disconnect */
803 #define RST 0x02 /* sta: scsi bus reset detected */
804 #define PAR 0x01 /* sta: scsi parity error */
805
806/*44*/ u8 nc_slpar;
807/*45*/ u8 nc_swide;
808/*46*/ u8 nc_macntl;
809/*47*/ u8 nc_gpcntl;
810/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
811/*49*/ u8 nc_stime1; /* cmd: timeout user defined */
812/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
813
814/*4c*/ u8 nc_stest0;
815
816/*4d*/ u8 nc_stest1;
817 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
818 #define DBLEN 0x08 /* clock doubler running */
819 #define DBLSEL 0x04 /* clock doubler selected */
820
821
822/*4e*/ u8 nc_stest2;
823 #define ROF 0x40 /* reset scsi offset (after gross error!) */
824 #define DIF 0x20 /* 720 SCSI differential mode */
825 #define EXT 0x02 /* extended filtering */
826
827/*4f*/ u8 nc_stest3;
828 #define TE 0x80 /* c: tolerAnt enable */
829 #define HSC 0x20 /* c: Halt SCSI Clock */
830 #define CSF 0x02 /* c: clear scsi fifo */
831
832/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
833/*52*/ u8 nc_stest4;
834 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
835 #define SMODE_HVD 0x40 /* High Voltage Differential */
836 #define SMODE_SE 0x80 /* Single Ended */
837 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
838 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
839 /* bits 0-5 rsvd for C1010 */
840
841/*53*/ u8 nc_53_;
842/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
843/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
844 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
845 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
846 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
847 #define DISFC 0x10 /* Disable Auto FIFO Clear */
848 #define DILS 0x02 /* Disable Internal Load/Store */
849 #define DPR 0x01 /* Disable Pipe Req */
850
851/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
852 #define ZMOD 0x80 /* High Impedance Mode */
853 #define DIC 0x10 /* Disable Internal Cycles */
854 #define DDAC 0x08 /* Disable Dual Address Cycle */
855 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
856 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
857 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
858
859/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
860/*5a*/ u16 nc_5a_;
861
862/*5c*/ u8 nc_scr0; /* Working register B */
863/*5d*/ u8 nc_scr1; /* */
864/*5e*/ u8 nc_scr2; /* */
865/*5f*/ u8 nc_scr3; /* */
866
867/*60*/ u8 nc_scrx[64]; /* Working register C-R */
868/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
869/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
870/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
871/*ac*/ u32 nc_drs; /* DSA Relative Selector */
872/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
873/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
874/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
875/*bc*/ u16 nc_scntl4; /* C1010 only */
876 #define U3EN 0x80 /* Enable Ultra 3 */
877 #define AIPEN 0x40 /* Allow check upper byte lanes */
878 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
879 transfer edge */
880 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
881 transfer edge */
882
883/*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
884/*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
885
886/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
887/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
888/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
889/*c9*/ u8 nc_rbc1; /* */
890/*ca*/ u8 nc_rbc2; /* */
891/*cb*/ u8 nc_rbc3; /* */
892
893/*cc*/ u8 nc_ua; /* Updated Address */
894/*cd*/ u8 nc_ua1; /* */
895/*ce*/ u8 nc_ua2; /* */
896/*cf*/ u8 nc_ua3; /* */
897/*d0*/ u32 nc_esa; /* Entry Storage Address */
898/*d4*/ u8 nc_ia; /* Instruction Address */
899/*d5*/ u8 nc_ia1;
900/*d6*/ u8 nc_ia2;
901/*d7*/ u8 nc_ia3;
902/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
903/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
904
905 /* Following for C1010 only */
906/*e0*/ u16 nc_crcpad; /* CRC Value */
907/*e2*/ u8 nc_crccntl0; /* CRC control register */
908 #define SNDCRC 0x10 /* Send CRC Request */
909/*e3*/ u8 nc_crccntl1; /* CRC control register */
910/*e4*/ u32 nc_crcdata; /* CRC data register */
911/*e8*/ u32 nc_e8_; /* rsvd */
912/*ec*/ u32 nc_ec_; /* rsvd */
913/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
914
915};
916
917/*-----------------------------------------------------------
918**
919** Utility macros for the script.
920**
921**-----------------------------------------------------------
922*/
923
924#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
925#define REG(r) REGJ (nc_, r)
926
927typedef u32 ncrcmd;
928
929/*-----------------------------------------------------------
930**
931** SCSI phases
932**
933** DT phases illegal for ncr driver.
934**
935**-----------------------------------------------------------
936*/
937
938#define SCR_DATA_OUT 0x00000000
939#define SCR_DATA_IN 0x01000000
940#define SCR_COMMAND 0x02000000
941#define SCR_STATUS 0x03000000
942#define SCR_DT_DATA_OUT 0x04000000
943#define SCR_DT_DATA_IN 0x05000000
944#define SCR_MSG_OUT 0x06000000
945#define SCR_MSG_IN 0x07000000
946
947#define SCR_ILG_OUT 0x04000000
948#define SCR_ILG_IN 0x05000000
949
950/*-----------------------------------------------------------
951**
952** Data transfer via SCSI.
953**
954**-----------------------------------------------------------
955**
956** MOVE_ABS (LEN)
957** <<start address>>
958**
959** MOVE_IND (LEN)
960** <<dnad_offset>>
961**
962** MOVE_TBL
963** <<dnad_offset>>
964**
965**-----------------------------------------------------------
966*/
967
968#define OPC_MOVE 0x08000000
969
970#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
971#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
972#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
973
974#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
975#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
976#define SCR_CHMOV_TBL (0x10000000)
977
978struct scr_tblmove {
979 u32 size;
980 u32 addr;
981};
982
983/*-----------------------------------------------------------
984**
985** Selection
986**
987**-----------------------------------------------------------
988**
989** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
990** <<alternate_address>>
991**
992** SEL_TBL | << dnad_offset>> [ | REL_JMP]
993** <<alternate_address>>
994**
995**-----------------------------------------------------------
996*/
997
998#define SCR_SEL_ABS 0x40000000
999#define SCR_SEL_ABS_ATN 0x41000000
1000#define SCR_SEL_TBL 0x42000000
1001#define SCR_SEL_TBL_ATN 0x43000000
1002
1003
1004#ifdef SCSI_NCR_BIG_ENDIAN
1005struct scr_tblsel {
1006 u8 sel_scntl3;
1007 u8 sel_id;
1008 u8 sel_sxfer;
1009 u8 sel_scntl4;
1010};
1011#else
1012struct scr_tblsel {
1013 u8 sel_scntl4;
1014 u8 sel_sxfer;
1015 u8 sel_id;
1016 u8 sel_scntl3;
1017};
1018#endif
1019
1020#define SCR_JMP_REL 0x04000000
1021#define SCR_ID(id) (((u32)(id)) << 16)
1022
1023/*-----------------------------------------------------------
1024**
1025** Waiting for Disconnect or Reselect
1026**
1027**-----------------------------------------------------------
1028**
1029** WAIT_DISC
1030** dummy: <<alternate_address>>
1031**
1032** WAIT_RESEL
1033** <<alternate_address>>
1034**
1035**-----------------------------------------------------------
1036*/
1037
1038#define SCR_WAIT_DISC 0x48000000
1039#define SCR_WAIT_RESEL 0x50000000
1040
1041/*-----------------------------------------------------------
1042**
1043** Bit Set / Reset
1044**
1045**-----------------------------------------------------------
1046**
1047** SET (flags {|.. })
1048**
1049** CLR (flags {|.. })
1050**
1051**-----------------------------------------------------------
1052*/
1053
1054#define SCR_SET(f) (0x58000000 | (f))
1055#define SCR_CLR(f) (0x60000000 | (f))
1056
1057#define SCR_CARRY 0x00000400
1058#define SCR_TRG 0x00000200
1059#define SCR_ACK 0x00000040
1060#define SCR_ATN 0x00000008
1061
1062
1063
1064
1065/*-----------------------------------------------------------
1066**
1067** Memory to memory move
1068**
1069**-----------------------------------------------------------
1070**
1071** COPY (bytecount)
1072** << source_address >>
1073** << destination_address >>
1074**
1075** SCR_COPY sets the NO FLUSH option by default.
1076** SCR_COPY_F does not set this option.
1077**
1078** For chips which do not support this option,
1079** ncr_copy_and_bind() will remove this bit.
1080**-----------------------------------------------------------
1081*/
1082
1083#define SCR_NO_FLUSH 0x01000000
1084
1085#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1086#define SCR_COPY_F(n) (0xc0000000 | (n))
1087
1088/*-----------------------------------------------------------
1089**
1090** Register move and binary operations
1091**
1092**-----------------------------------------------------------
1093**
1094** SFBR_REG (reg, op, data) reg = SFBR op data
1095** << 0 >>
1096**
1097** REG_SFBR (reg, op, data) SFBR = reg op data
1098** << 0 >>
1099**
1100** REG_REG (reg, op, data) reg = reg op data
1101** << 0 >>
1102**
1103**-----------------------------------------------------------
1104** On 810A, 860, 825A, 875, 895 and 896 chips the content
1105** of SFBR register can be used as data (SCR_SFBR_DATA).
1106** The 896 has additionnal IO registers starting at
1107** offset 0x80. Bit 7 of register offset is stored in
1108** bit 7 of the SCRIPTS instruction first DWORD.
1109**-----------------------------------------------------------
1110*/
1111
1112#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1113
1114#define SCR_SFBR_REG(reg,op,data) \
1115 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1116
1117#define SCR_REG_SFBR(reg,op,data) \
1118 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1119
1120#define SCR_REG_REG(reg,op,data) \
1121 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1122
1123
1124#define SCR_LOAD 0x00000000
1125#define SCR_SHL 0x01000000
1126#define SCR_OR 0x02000000
1127#define SCR_XOR 0x03000000
1128#define SCR_AND 0x04000000
1129#define SCR_SHR 0x05000000
1130#define SCR_ADD 0x06000000
1131#define SCR_ADDC 0x07000000
1132
1133#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1134
1135/*-----------------------------------------------------------
1136**
1137** FROM_REG (reg) SFBR = reg
1138** << 0 >>
1139**
1140** TO_REG (reg) reg = SFBR
1141** << 0 >>
1142**
1143** LOAD_REG (reg, data) reg = <data>
1144** << 0 >>
1145**
1146** LOAD_SFBR(data) SFBR = <data>
1147** << 0 >>
1148**
1149**-----------------------------------------------------------
1150*/
1151
1152#define SCR_FROM_REG(reg) \
1153 SCR_REG_SFBR(reg,SCR_OR,0)
1154
1155#define SCR_TO_REG(reg) \
1156 SCR_SFBR_REG(reg,SCR_OR,0)
1157
1158#define SCR_LOAD_REG(reg,data) \
1159 SCR_REG_REG(reg,SCR_LOAD,data)
1160
1161#define SCR_LOAD_SFBR(data) \
1162 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1163
1164/*-----------------------------------------------------------
1165**
1166** LOAD from memory to register.
1167** STORE from register to memory.
1168**
1169** Only supported by 810A, 860, 825A, 875, 895 and 896.
1170**
1171**-----------------------------------------------------------
1172**
1173** LOAD_ABS (LEN)
1174** <<start address>>
1175**
1176** LOAD_REL (LEN) (DSA relative)
1177** <<dsa_offset>>
1178**
1179**-----------------------------------------------------------
1180*/
1181
1182#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1183#define SCR_NO_FLUSH2 0x02000000
1184#define SCR_DSA_REL2 0x10000000
1185
1186#define SCR_LOAD_R(reg, how, n) \
1187 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1188
1189#define SCR_STORE_R(reg, how, n) \
1190 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1191
1192#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1193#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1194#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1195#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1196
1197#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1198#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1199#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1200#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1201
1202
1203/*-----------------------------------------------------------
1204**
1205** Waiting for Disconnect or Reselect
1206**
1207**-----------------------------------------------------------
1208**
1209** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1210** <<address>>
1211**
1212** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1213** <<distance>>
1214**
1215** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1216** <<address>>
1217**
1218** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1219** <<distance>>
1220**
1221** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1222** <<dummy>>
1223**
1224** INT [ | IFTRUE/IFFALSE ( ... ) ]
1225** <<ident>>
1226**
1227** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1228** <<ident>>
1229**
1230** Conditions:
1231** WHEN (phase)
1232** IF (phase)
1233** CARRYSET
1234** DATA (data, mask)
1235**
1236**-----------------------------------------------------------
1237*/
1238
1239#define SCR_NO_OP 0x80000000
1240#define SCR_JUMP 0x80080000
1241#define SCR_JUMP64 0x80480000
1242#define SCR_JUMPR 0x80880000
1243#define SCR_CALL 0x88080000
1244#define SCR_CALLR 0x88880000
1245#define SCR_RETURN 0x90080000
1246#define SCR_INT 0x98080000
1247#define SCR_INT_FLY 0x98180000
1248
1249#define IFFALSE(arg) (0x00080000 | (arg))
1250#define IFTRUE(arg) (0x00000000 | (arg))
1251
1252#define WHEN(phase) (0x00030000 | (phase))
1253#define IF(phase) (0x00020000 | (phase))
1254
1255#define DATA(D) (0x00040000 | ((D) & 0xff))
1256#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1257
1258#define CARRYSET (0x00200000)
1259
1260/*-----------------------------------------------------------
1261**
1262** SCSI constants.
1263**
1264**-----------------------------------------------------------
1265*/
1266
1267/*
1268** Messages
1269*/
1270
1271#define M_COMPLETE COMMAND_COMPLETE
1272#define M_EXTENDED EXTENDED_MESSAGE
1273#define M_SAVE_DP SAVE_POINTERS
1274#define M_RESTORE_DP RESTORE_POINTERS
1275#define M_DISCONNECT DISCONNECT
1276#define M_ID_ERROR INITIATOR_ERROR
1277#define M_ABORT ABORT_TASK_SET
1278#define M_REJECT MESSAGE_REJECT
1279#define M_NOOP NOP
1280#define M_PARITY MSG_PARITY_ERROR
1281#define M_LCOMPLETE LINKED_CMD_COMPLETE
1282#define M_FCOMPLETE LINKED_FLG_CMD_COMPLETE
1283#define M_RESET TARGET_RESET
1284#define M_ABORT_TAG ABORT_TASK
1285#define M_CLEAR_QUEUE CLEAR_TASK_SET
1286#define M_INIT_REC INITIATE_RECOVERY
1287#define M_REL_REC RELEASE_RECOVERY
1288#define M_TERMINATE (0x11)
1289#define M_SIMPLE_TAG SIMPLE_QUEUE_TAG
1290#define M_HEAD_TAG HEAD_OF_QUEUE_TAG
1291#define M_ORDERED_TAG ORDERED_QUEUE_TAG
1292#define M_IGN_RESIDUE IGNORE_WIDE_RESIDUE
1293#define M_IDENTIFY (0x80)
1294
1295#define M_X_MODIFY_DP EXTENDED_MODIFY_DATA_POINTER
1296#define M_X_SYNC_REQ EXTENDED_SDTR
1297#define M_X_WIDE_REQ EXTENDED_WDTR
1298#define M_X_PPR_REQ EXTENDED_PPR
1299
1300/*
1301** Status
1302*/
1303
1304#define S_GOOD (0x00)
1305#define S_CHECK_COND (0x02)
1306#define S_COND_MET (0x04)
1307#define S_BUSY (0x08)
1308#define S_INT (0x10)
1309#define S_INT_COND_MET (0x14)
1310#define S_CONFLICT (0x18)
1311#define S_TERMINATED (0x20)
1312#define S_QUEUE_FULL (0x28)
1313#define S_ILLEGAL (0xff)
1314#define S_SENSE (0x80)
1315
1316/*
1317 * End of ncrreg from FreeBSD
1318 */
1319
1320#endif /* defined SYM53C8XX_DEFS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 00:38:06 -0500