diff options
author | Don Brace <don.brace@pmcs.com> | 2015-01-23 17:41:25 -0500 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2015-02-02 12:57:35 -0500 |
commit | 2662cab8984f6075e72e0997065c75ad3def6c95 (patch) | |
tree | da70f7a7b0dbd25349b91ee3c0debe8a9b0b1ff9 /drivers/scsi | |
parent | 3b747298786355c6934b0892fc9ae4ca44105192 (diff) |
hpsa: change how SA controllers are reset
Change how SA controllers are reset by changing PCI power levels.
The hpsa driver was finding the PCI_PM_CTRL_STATE_MASK offset
then reading/writing a bitmask to change the power state. There
are kernel functions that do the same operations. Better to use
the kernel functions.
Signed-off-by: Don Brace <don.brace@pmcs.com>
Reviewed-by: Scott Teel <scott.teel@pmcs.com>
Reviewed-by: Webb Scales <webbnh@hp.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/scsi')
-rw-r--r-- | drivers/scsi/hpsa.c | 28 |
1 files changed, 10 insertions, 18 deletions
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 9edacff962a3..371d0a81d535 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c | |||
@@ -5689,30 +5689,22 @@ static int hpsa_controller_hard_reset(struct pci_dev *pdev, | |||
5689 | * the controller, place the interface device in D3 then to D0, | 5689 | * the controller, place the interface device in D3 then to D0, |
5690 | * this causes a secondary PCI reset which will reset the | 5690 | * this causes a secondary PCI reset which will reset the |
5691 | * controller." */ | 5691 | * controller." */ |
5692 | int pos; | 5692 | |
5693 | u16 pmcsr; | 5693 | int rc = 0; |
5694 | 5694 | ||
5695 | pos = pci_find_capability(pdev, PCI_CAP_ID_PM); | ||
5696 | if (pos == 0) { | ||
5697 | dev_err(&pdev->dev, | ||
5698 | "hpsa_reset_controller: " | ||
5699 | "PCI PM not supported\n"); | ||
5700 | return -ENODEV; | ||
5701 | } | ||
5702 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); | 5695 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); |
5696 | |||
5703 | /* enter the D3hot power management state */ | 5697 | /* enter the D3hot power management state */ |
5704 | pci_read_config_word(pdev, pos + PCI_PM_CTRL, | 5698 | rc = pci_set_power_state(pdev, PCI_D3hot); |
5705 | (__force u16 *)&pmcsr); | 5699 | if (rc) |
5706 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | 5700 | return rc; |
5707 | pmcsr |= (__force u16) PCI_D3hot; | ||
5708 | pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); | ||
5709 | 5701 | ||
5710 | msleep(500); | 5702 | msleep(500); |
5711 | 5703 | ||
5712 | /* enter the D0 power management state */ | 5704 | /* enter the D0 power management state */ |
5713 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | 5705 | rc = pci_set_power_state(pdev, PCI_D0); |
5714 | pmcsr |= (__force u16) PCI_D0; | 5706 | if (rc) |
5715 | pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); | 5707 | return rc; |
5716 | 5708 | ||
5717 | /* | 5709 | /* |
5718 | * The P600 requires a small delay when changing states. | 5710 | * The P600 requires a small delay when changing states. |