diff options
author | Jean Delvare <khali@linux-fr.org> | 2007-10-19 17:22:55 -0400 |
---|---|---|
committer | Adrian Bunk <bunk@kernel.org> | 2007-10-19 17:22:55 -0400 |
commit | c03983ac9b268d4bbb8c2600baba5798aefa9d5d (patch) | |
tree | 09c351d4c6174a7b7ed3357d391ff839143160c4 /drivers/scsi | |
parent | db955170d40601d9925f01712782fbe3ce362b7e (diff) |
Spelling fix: explicitly
From: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'drivers/scsi')
-rw-r--r-- | drivers/scsi/sym53c8xx_2/sym_fw2.h | 2 | ||||
-rw-r--r-- | drivers/scsi/wd33c93.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/scsi/sym53c8xx_2/sym_fw2.h b/drivers/scsi/sym53c8xx_2/sym_fw2.h index 6e5b952312e3..ae1fb179b88e 100644 --- a/drivers/scsi/sym53c8xx_2/sym_fw2.h +++ b/drivers/scsi/sym53c8xx_2/sym_fw2.h | |||
@@ -1781,7 +1781,7 @@ static struct SYM_FWB_SCR SYM_FWB_SCR = { | |||
1781 | * While testing with bogus QUANTUM drives, the C1010 | 1781 | * While testing with bogus QUANTUM drives, the C1010 |
1782 | * sometimes raised a spurious phase mismatch with | 1782 | * sometimes raised a spurious phase mismatch with |
1783 | * WSR and the CHMOV(1) triggered another PM. | 1783 | * WSR and the CHMOV(1) triggered another PM. |
1784 | * Waiting explicitely for the PHASE seemed to avoid | 1784 | * Waiting explicitly for the PHASE seemed to avoid |
1785 | * the nested phase mismatch. Btw, this didn't happen | 1785 | * the nested phase mismatch. Btw, this didn't happen |
1786 | * using my IBM drives. | 1786 | * using my IBM drives. |
1787 | */ | 1787 | */ |
diff --git a/drivers/scsi/wd33c93.h b/drivers/scsi/wd33c93.h index 61ffb860dacc..00123f2383d7 100644 --- a/drivers/scsi/wd33c93.h +++ b/drivers/scsi/wd33c93.h | |||
@@ -155,7 +155,7 @@ | |||
155 | #define WD33C93_FS_12_15 OWNID_FS_12 | 155 | #define WD33C93_FS_12_15 OWNID_FS_12 |
156 | #define WD33C93_FS_16_20 OWNID_FS_16 | 156 | #define WD33C93_FS_16_20 OWNID_FS_16 |
157 | 157 | ||
158 | /* pass input-clock explicitely. accepted mhz values are 8-10,12-20 */ | 158 | /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */ |
159 | #define WD33C93_FS_MHZ(mhz) (mhz) | 159 | #define WD33C93_FS_MHZ(mhz) (mhz) |
160 | 160 | ||
161 | /* Control register */ | 161 | /* Control register */ |