diff options
author | Andrew Vasquez <andrew.vasquez@qlogic.com> | 2005-07-08 20:59:26 -0400 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.(none)> | 2005-07-14 11:15:31 -0400 |
commit | 88c2666351f41a7d4459e79594f687a356f5e57c (patch) | |
tree | a07eb04ead61e0aa61d22cde8963f1b74f9b0891 /drivers/scsi | |
parent | f0883ac6a74b403f0f2e91166ba06227cc4690e6 (diff) |
[SCSI] qla2xxx: Consolidate ISP24xx chip reset logic.
Consolidate ISP24xx chip reset logic.
Consolidate near-duplicate RISC reset logic from
qla24xx_reset_chip() and qla24xx_chip_diag(). Also, after
initiating a soft-reset, insure the firmware has completed
all NVRAM accesses before continuing.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 11 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_init.c | 78 |
2 files changed, 42 insertions, 47 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index a20450e9a479..72bbaa91dc77 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c | |||
@@ -1526,6 +1526,17 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |||
1526 | 1526 | ||
1527 | WRT_REG_DWORD(®->ctrl_status, | 1527 | WRT_REG_DWORD(®->ctrl_status, |
1528 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | 1528 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); |
1529 | RD_REG_DWORD(®->ctrl_status); | ||
1530 | |||
1531 | /* Wait for firmware to complete NVRAM accesses. */ | ||
1532 | udelay(5); | ||
1533 | mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); | ||
1534 | for (cnt = 10000 ; cnt && mb[0]; cnt--) { | ||
1535 | udelay(5); | ||
1536 | mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); | ||
1537 | barrier(); | ||
1538 | } | ||
1539 | |||
1529 | udelay(20); | 1540 | udelay(20); |
1530 | for (cnt = 0; cnt < 30000; cnt++) { | 1541 | for (cnt = 0; cnt < 30000; cnt++) { |
1531 | if ((RD_REG_DWORD(®->ctrl_status) & | 1542 | if ((RD_REG_DWORD(®->ctrl_status) & |
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index 3fd63804319d..1a25714e85c6 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c | |||
@@ -564,20 +564,18 @@ qla2x00_reset_chip(scsi_qla_host_t *ha) | |||
564 | } | 564 | } |
565 | 565 | ||
566 | /** | 566 | /** |
567 | * qla24xx_reset_chip() - Reset ISP24xx chip. | 567 | * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. |
568 | * @ha: HA context | 568 | * @ha: HA context |
569 | * | 569 | * |
570 | * Returns 0 on success. | 570 | * Returns 0 on success. |
571 | */ | 571 | */ |
572 | void | 572 | static inline void |
573 | qla24xx_reset_chip(scsi_qla_host_t *ha) | 573 | qla24xx_reset_risc(scsi_qla_host_t *ha) |
574 | { | 574 | { |
575 | unsigned long flags = 0; | 575 | unsigned long flags = 0; |
576 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 576 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
577 | uint32_t cnt, d2; | 577 | uint32_t cnt, d2; |
578 | 578 | ||
579 | ha->isp_ops.disable_intrs(ha); | ||
580 | |||
581 | spin_lock_irqsave(&ha->hardware_lock, flags); | 579 | spin_lock_irqsave(&ha->hardware_lock, flags); |
582 | 580 | ||
583 | /* Reset RISC. */ | 581 | /* Reset RISC. */ |
@@ -591,6 +589,17 @@ qla24xx_reset_chip(scsi_qla_host_t *ha) | |||
591 | 589 | ||
592 | WRT_REG_DWORD(®->ctrl_status, | 590 | WRT_REG_DWORD(®->ctrl_status, |
593 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | 591 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); |
592 | RD_REG_DWORD(®->ctrl_status); | ||
593 | |||
594 | /* Wait for firmware to complete NVRAM accesses. */ | ||
595 | udelay(5); | ||
596 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | ||
597 | for (cnt = 10000 ; cnt && d2; cnt--) { | ||
598 | udelay(5); | ||
599 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | ||
600 | barrier(); | ||
601 | } | ||
602 | |||
594 | udelay(20); | 603 | udelay(20); |
595 | d2 = RD_REG_DWORD(®->ctrl_status); | 604 | d2 = RD_REG_DWORD(®->ctrl_status); |
596 | for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { | 605 | for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { |
@@ -619,6 +628,21 @@ qla24xx_reset_chip(scsi_qla_host_t *ha) | |||
619 | } | 628 | } |
620 | 629 | ||
621 | /** | 630 | /** |
631 | * qla24xx_reset_chip() - Reset ISP24xx chip. | ||
632 | * @ha: HA context | ||
633 | * | ||
634 | * Returns 0 on success. | ||
635 | */ | ||
636 | void | ||
637 | qla24xx_reset_chip(scsi_qla_host_t *ha) | ||
638 | { | ||
639 | ha->isp_ops.disable_intrs(ha); | ||
640 | |||
641 | /* Perform RISC reset. */ | ||
642 | qla24xx_reset_risc(ha); | ||
643 | } | ||
644 | |||
645 | /** | ||
622 | * qla2x00_chip_diag() - Test chip for proper operation. | 646 | * qla2x00_chip_diag() - Test chip for proper operation. |
623 | * @ha: HA context | 647 | * @ha: HA context |
624 | * | 648 | * |
@@ -753,49 +777,9 @@ int | |||
753 | qla24xx_chip_diag(scsi_qla_host_t *ha) | 777 | qla24xx_chip_diag(scsi_qla_host_t *ha) |
754 | { | 778 | { |
755 | int rval; | 779 | int rval; |
756 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | ||
757 | unsigned long flags = 0; | ||
758 | uint32_t cnt, d2; | ||
759 | |||
760 | spin_lock_irqsave(&ha->hardware_lock, flags); | ||
761 | 780 | ||
762 | /* Reset RISC. */ | 781 | /* Perform RISC reset. */ |
763 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | 782 | qla24xx_reset_risc(ha); |
764 | for (cnt = 0; cnt < 30000; cnt++) { | ||
765 | if ((RD_REG_DWORD(®->ctrl_status) & | ||
766 | CSRX_DMA_ACTIVE) == 0) | ||
767 | break; | ||
768 | |||
769 | udelay(10); | ||
770 | } | ||
771 | |||
772 | WRT_REG_DWORD(®->ctrl_status, | ||
773 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | ||
774 | udelay(20); | ||
775 | d2 = RD_REG_DWORD(®->ctrl_status); | ||
776 | for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { | ||
777 | udelay(5); | ||
778 | d2 = RD_REG_DWORD(®->ctrl_status); | ||
779 | barrier(); | ||
780 | } | ||
781 | |||
782 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | ||
783 | RD_REG_DWORD(®->hccr); | ||
784 | |||
785 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | ||
786 | RD_REG_DWORD(®->hccr); | ||
787 | |||
788 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | ||
789 | RD_REG_DWORD(®->hccr); | ||
790 | |||
791 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | ||
792 | for (cnt = 6000000 ; cnt && d2; cnt--) { | ||
793 | udelay(5); | ||
794 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | ||
795 | barrier(); | ||
796 | } | ||
797 | |||
798 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
799 | 783 | ||
800 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; | 784 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; |
801 | 785 | ||