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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/scsi/tmscsim.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/scsi/tmscsim.h')
-rw-r--r--drivers/scsi/tmscsim.h565
1 files changed, 565 insertions, 0 deletions
diff --git a/drivers/scsi/tmscsim.h b/drivers/scsi/tmscsim.h
new file mode 100644
index 000000000000..d4495272fb40
--- /dev/null
+++ b/drivers/scsi/tmscsim.h
@@ -0,0 +1,565 @@
1/***********************************************************************
2;* File Name : TMSCSIM.H *
3;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter *
4;* Device Driver *
5;***********************************************************************/
6/* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */
7
8#ifndef _TMSCSIM_H
9#define _TMSCSIM_H
10
11#include <linux/types.h>
12#include <linux/config.h>
13
14#define SCSI_IRQ_NONE 255
15
16#define MAX_ADAPTER_NUM 4
17#define MAX_SG_LIST_BUF 16 /* Not used */
18#define MAX_SCSI_ID 8
19#define MAX_SRB_CNT 50 /* Max number of started commands */
20
21#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
22
23#define pci_dma_lo32(a) (a & 0xffffffff)
24
25typedef u8 UCHAR; /* 8 bits */
26typedef u16 USHORT; /* 16 bits */
27typedef u32 UINT; /* 32 bits */
28typedef unsigned long ULONG; /* 32/64 bits */
29
30
31/*
32;-----------------------------------------------------------------------
33; SCSI Request Block
34;-----------------------------------------------------------------------
35*/
36struct dc390_srb
37{
38//u8 CmdBlock[12];
39
40struct dc390_srb *pNextSRB;
41struct dc390_dcb *pSRBDCB;
42struct scsi_cmnd *pcmd;
43struct scatterlist *pSegmentList;
44
45struct scatterlist Segmentx; /* make a one entry of S/G list table */
46
47unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A*/
48unsigned long SGToBeXferLen; /*; to be xfer length */
49unsigned long TotalXferredLen;
50unsigned long SavedTotXLen;
51unsigned long Saved_Ptr;
52u32 SRBState;
53
54u8 SRBStatus;
55u8 SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */
56 /*; b4-settimeout,b5-Residual valid */
57u8 AdaptStatus;
58u8 TargetStatus;
59
60u8 ScsiPhase;
61s8 TagNumber;
62u8 SGIndex;
63u8 SGcount;
64
65u8 MsgCnt;
66u8 EndMessage;
67u8 SavedSGCount;
68
69u8 MsgInBuf[6];
70u8 MsgOutBuf[6];
71
72//u8 IORBFlag; /*;81h-Reset, 2-retry */
73};
74
75
76/*
77;-----------------------------------------------------------------------
78; Device Control Block
79;-----------------------------------------------------------------------
80*/
81struct dc390_dcb
82{
83struct dc390_dcb *pNextDCB;
84struct dc390_acb *pDCBACB;
85
86/* Queued SRBs */
87struct dc390_srb *pGoingSRB;
88struct dc390_srb *pGoingLast;
89struct dc390_srb *pActiveSRB;
90u8 GoingSRBCnt;
91
92u32 TagMask;
93
94u8 TargetID; /*; SCSI Target ID (SCSI Only) */
95u8 TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
96u8 DevMode;
97u8 DCBFlag;
98
99u8 CtrlR1;
100u8 CtrlR3;
101u8 CtrlR4;
102
103u8 SyncMode; /*; 0:async mode */
104u8 NegoPeriod; /*;for nego. */
105u8 SyncPeriod; /*;for reg. */
106u8 SyncOffset; /*;for reg. and nego.(low nibble) */
107};
108
109
110/*
111;-----------------------------------------------------------------------
112; Adapter Control Block
113;-----------------------------------------------------------------------
114*/
115struct dc390_acb
116{
117struct Scsi_Host *pScsiHost;
118u16 IOPortBase;
119u8 IRQLevel;
120u8 status;
121
122u8 SRBCount;
123u8 AdapterIndex; /*; nth Adapter this driver */
124u8 DCBCnt;
125
126u8 TagMaxNum;
127u8 ACBFlag;
128u8 Gmode2;
129u8 scan_devices;
130
131struct dc390_dcb *pLinkDCB;
132struct dc390_dcb *pLastDCB;
133struct dc390_dcb *pDCBRunRobin;
134
135struct dc390_dcb *pActiveDCB;
136struct dc390_srb *pFreeSRB;
137struct dc390_srb *pTmpSRB;
138
139u8 msgin123[4];
140u8 Connected;
141u8 pad;
142
143#if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0)
144spinlock_t lock;
145#endif
146u8 sel_timeout;
147u8 glitch_cfg;
148
149u8 MsgLen;
150u8 Ignore_IRQ; /* Not used */
151
152struct pci_dev *pdev;
153
154unsigned long Cmds;
155u32 SelLost;
156u32 SelConn;
157u32 CmdInQ;
158u32 CmdOutOfSRB;
159
160struct dc390_srb TmpSRB;
161struct dc390_srb SRB_array[MAX_SRB_CNT]; /* 50 SRBs */
162};
163
164
165/*;-----------------------------------------------------------------------*/
166
167
168#define BIT31 0x80000000
169#define BIT30 0x40000000
170#define BIT29 0x20000000
171#define BIT28 0x10000000
172#define BIT27 0x08000000
173#define BIT26 0x04000000
174#define BIT25 0x02000000
175#define BIT24 0x01000000
176#define BIT23 0x00800000
177#define BIT22 0x00400000
178#define BIT21 0x00200000
179#define BIT20 0x00100000
180#define BIT19 0x00080000
181#define BIT18 0x00040000
182#define BIT17 0x00020000
183#define BIT16 0x00010000
184#define BIT15 0x00008000
185#define BIT14 0x00004000
186#define BIT13 0x00002000
187#define BIT12 0x00001000
188#define BIT11 0x00000800
189#define BIT10 0x00000400
190#define BIT9 0x00000200
191#define BIT8 0x00000100
192#define BIT7 0x00000080
193#define BIT6 0x00000040
194#define BIT5 0x00000020
195#define BIT4 0x00000010
196#define BIT3 0x00000008
197#define BIT2 0x00000004
198#define BIT1 0x00000002
199#define BIT0 0x00000001
200
201/*;---UnitCtrlFlag */
202#define UNIT_ALLOCATED BIT0
203#define UNIT_INFO_CHANGED BIT1
204#define FORMATING_MEDIA BIT2
205#define UNIT_RETRY BIT3
206
207/*;---UnitFlags */
208#define DASD_SUPPORT BIT0
209#define SCSI_SUPPORT BIT1
210#define ASPI_SUPPORT BIT2
211
212/*;----SRBState machine definition */
213#define SRB_FREE 0
214#define SRB_WAIT BIT0
215#define SRB_READY BIT1
216#define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
217#define SRB_MSGIN BIT3
218#define SRB_MSGIN_MULTI BIT4
219#define SRB_COMMAND BIT5
220#define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
221#define SRB_DISCONNECT BIT7
222#define SRB_DATA_XFER BIT8
223#define SRB_XFERPAD BIT9
224#define SRB_STATUS BIT10
225#define SRB_COMPLETED BIT11
226#define SRB_ABORT_SENT BIT12
227#define DO_SYNC_NEGO BIT13
228#define SRB_UNEXPECT_RESEL BIT14
229
230/*;---SRBstatus */
231#define SRB_OK BIT0
232#define ABORTION BIT1
233#define OVER_RUN BIT2
234#define UNDER_RUN BIT3
235#define PARITY_ERROR BIT4
236#define SRB_ERROR BIT5
237
238/*;---ACBFlag */
239#define RESET_DEV BIT0
240#define RESET_DETECT BIT1
241#define RESET_DONE BIT2
242
243/*;---DCBFlag */
244#define ABORT_DEV_ BIT0
245
246/*;---SRBFlag */
247#define DATAOUT BIT7
248#define DATAIN BIT6
249#define RESIDUAL_VALID BIT5
250#define ENABLE_TIMER BIT4
251#define RESET_DEV0 BIT2
252#define ABORT_DEV BIT1
253#define AUTO_REQSENSE BIT0
254
255/*;---Adapter status */
256#define H_STATUS_GOOD 0
257#define H_SEL_TIMEOUT 0x11
258#define H_OVER_UNDER_RUN 0x12
259#define H_UNEXP_BUS_FREE 0x13
260#define H_TARGET_PHASE_F 0x14
261#define H_INVALID_CCB_OP 0x16
262#define H_LINK_CCB_BAD 0x17
263#define H_BAD_TARGET_DIR 0x18
264#define H_DUPLICATE_CCB 0x19
265#define H_BAD_CCB_OR_SG 0x1A
266#define H_ABORT 0x0FF
267
268/*; SCSI Status byte codes*/
269/* The values defined in include/scsi/scsi.h, to be shifted << 1 */
270
271#define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
272#define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
273#define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
274
275/* cmd->result */
276#define RES_TARGET 0x000000FF /* Target State */
277#define RES_TARGET_LNX STATUS_MASK /* Only official ... */
278#define RES_ENDMSG 0x0000FF00 /* End Message */
279#define RES_DID 0x00FF0000 /* DID_ codes */
280#define RES_DRV 0xFF000000 /* DRIVER_ codes */
281
282#define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt))
283#define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)<<1)
284
285#define SET_RES_TARGET(who, tgt) do { who &= ~RES_TARGET; who |= (int)(tgt); } while (0)
286#define SET_RES_TARGET_LNX(who, tgt) do { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; } while (0)
287#define SET_RES_MSG(who, msg) do { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; } while (0)
288#define SET_RES_DID(who, did) do { who &= ~RES_DID; who |= (int)(did) << 16; } while (0)
289#define SET_RES_DRV(who, drv) do { who &= ~RES_DRV; who |= (int)(drv) << 24; } while (0)
290
291/*;---Sync_Mode */
292#define SYNC_DISABLE 0
293#define SYNC_ENABLE BIT0
294#define SYNC_NEGO_DONE BIT1
295#define WIDE_ENABLE BIT2 /* Not used ;-) */
296#define WIDE_NEGO_DONE BIT3 /* Not used ;-) */
297#define EN_TAG_QUEUEING BIT4
298#define EN_ATN_STOP BIT5
299
300#define SYNC_NEGO_OFFSET 15
301
302/*;---SCSI bus phase*/
303#define SCSI_DATA_OUT 0
304#define SCSI_DATA_IN 1
305#define SCSI_COMMAND 2
306#define SCSI_STATUS_ 3
307#define SCSI_NOP0 4
308#define SCSI_NOP1 5
309#define SCSI_MSG_OUT 6
310#define SCSI_MSG_IN 7
311
312/*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */
313#define ABORT_TAG 0x0d
314
315/*
316 * SISC query queue
317 */
318typedef struct {
319 dma_addr_t saved_dma_handle;
320} dc390_cmd_scp_t;
321
322/*
323;==========================================================
324; EEPROM byte offset
325;==========================================================
326*/
327typedef struct _EEprom
328{
329u8 EE_MODE1;
330u8 EE_SPEED;
331u8 xx1;
332u8 xx2;
333} EEprom, *PEEprom;
334
335#define REAL_EE_ADAPT_SCSI_ID 64
336#define REAL_EE_MODE2 65
337#define REAL_EE_DELAY 66
338#define REAL_EE_TAG_CMD_NUM 67
339
340#define EE_ADAPT_SCSI_ID 32
341#define EE_MODE2 33
342#define EE_DELAY 34
343#define EE_TAG_CMD_NUM 35
344
345#define EE_LEN 40
346
347/*; EE_MODE1 bits definition*/
348#define PARITY_CHK_ BIT0
349#define SYNC_NEGO_ BIT1
350#define EN_DISCONNECT_ BIT2
351#define SEND_START_ BIT3
352#define TAG_QUEUEING_ BIT4
353
354/*; EE_MODE2 bits definition*/
355#define MORE2_DRV BIT0
356#define GREATER_1G BIT1
357#define RST_SCSI_BUS BIT2
358#define ACTIVE_NEGATION BIT3
359#define NO_SEEK BIT4
360#define LUN_CHECK BIT5
361
362#define ENABLE_CE 1
363#define DISABLE_CE 0
364#define EEPROM_READ 0x80
365
366/*
367;==========================================================
368; AMD 53C974 Registers bit Definition
369;==========================================================
370*/
371/*
372;====================
373; SCSI Register
374;====================
375*/
376
377/*; Command Reg.(+0CH) (rw) */
378#define DMA_COMMAND BIT7
379#define NOP_CMD 0
380#define CLEAR_FIFO_CMD 1
381#define RST_DEVICE_CMD 2
382#define RST_SCSI_BUS_CMD 3
383
384#define INFO_XFER_CMD 0x10
385#define INITIATOR_CMD_CMPLTE 0x11
386#define MSG_ACCEPTED_CMD 0x12
387#define XFER_PAD_BYTE 0x18
388#define SET_ATN_CMD 0x1A
389#define RESET_ATN_CMD 0x1B
390
391#define SEL_WO_ATN 0x41 /* currently not used */
392#define SEL_W_ATN 0x42
393#define SEL_W_ATN_STOP 0x43
394#define SEL_W_ATN3 0x46
395#define EN_SEL_RESEL 0x44
396#define DIS_SEL_RESEL 0x45 /* currently not used */
397#define RESEL 0x40 /* " */
398#define RESEL_ATN3 0x47 /* " */
399
400#define DATA_XFER_CMD INFO_XFER_CMD
401
402
403/*; SCSI Status Reg.(+10H) (r) */
404#define INTERRUPT BIT7
405#define ILLEGAL_OP_ERR BIT6
406#define PARITY_ERR BIT5
407#define COUNT_2_ZERO BIT4
408#define GROUP_CODE_VALID BIT3
409#define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
410/* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
411
412/*; Interrupt Status Reg.(+14H) (r) */
413#define SCSI_RESET BIT7
414#define INVALID_CMD BIT6
415#define DISCONNECTED BIT5
416#define SERVICE_REQUEST BIT4
417#define SUCCESSFUL_OP BIT3
418#define RESELECTED BIT2
419#define SEL_ATTENTION BIT1
420#define SELECTED BIT0
421
422/*; Internal State Reg.(+18H) (r) */
423#define SYNC_OFFSET_FLAG BIT3
424#define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
425/* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
426
427/*; Clock Factor Reg.(+24H) (w) */
428#define CLK_FREQ_40MHZ 0
429#define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
430#define CLK_FREQ_30MHZ (BIT2+BIT1)
431#define CLK_FREQ_25MHZ (BIT2+BIT0)
432#define CLK_FREQ_20MHZ BIT2
433#define CLK_FREQ_15MHZ (BIT1+BIT0)
434#define CLK_FREQ_10MHZ BIT1
435
436/*; Control Reg. 1(+20H) (rw) */
437#define EXTENDED_TIMING BIT7
438#define DIS_INT_ON_SCSI_RST BIT6
439#define PARITY_ERR_REPO BIT4
440#define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */
441
442/*; Control Reg. 2(+2CH) (rw) */
443#define EN_FEATURE BIT6
444#define EN_SCSI2_CMD BIT3
445
446/*; Control Reg. 3(+30H) (rw) */
447#define ID_MSG_CHECK BIT7
448#define EN_QTAG_MSG BIT6
449#define EN_GRP2_CMD BIT5
450#define FAST_SCSI BIT4 /* ;10MB/SEC */
451#define FAST_CLK BIT3 /* ;25 - 40 MHZ */
452
453/*; Control Reg. 4(+34H) (rw) */
454#define EATER_12NS 0
455#define EATER_25NS BIT7
456#define EATER_35NS BIT6
457#define EATER_0NS (BIT7+BIT6)
458#define REDUCED_POWER BIT5
459#define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */
460#define NEGATE_REQACKDATA BIT2
461#define NEGATE_REQACK BIT3
462
463#define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
464#define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
465
466/*
467;====================
468; DMA Register
469;====================
470*/
471/*; DMA Command Reg.(+40H) (rw) */
472#define READ_DIRECTION BIT7
473#define WRITE_DIRECTION 0
474#define EN_DMA_INT BIT6
475#define EN_PAGE_INT BIT5 /* page transfer interrupt enable */
476#define MAP_TO_MDL BIT4
477#define DIAGNOSTIC BIT2
478#define DMA_IDLE_CMD 0
479#define DMA_BLAST_CMD BIT0
480#define DMA_ABORT_CMD BIT1
481#define DMA_START_CMD (BIT1+BIT0)
482
483/*; DMA Status Reg.(+54H) (r) */
484#define PCI_MS_ABORT BIT6
485#define BLAST_COMPLETE BIT5
486#define SCSI_INTERRUPT BIT4
487#define DMA_XFER_DONE BIT3
488#define DMA_XFER_ABORT BIT2
489#define DMA_XFER_ERROR BIT1
490#define POWER_DOWN BIT0
491
492/*; DMA SCSI Bus and Ctrl.(+70H) */
493#define EN_INT_ON_PCI_ABORT BIT25
494#define WRT_ERASE_DMA_STAT BIT24
495#define PW_DOWN_CTRL BIT21
496#define SCSI_BUSY BIT20
497#define SCLK BIT19
498#define SCAM BIT18
499#define SCSI_LINES 0x0003ffff
500
501/*
502;==========================================================
503; SCSI Chip register address offset
504;==========================================================
505;Registers are rw unless declared otherwise
506*/
507#define CtcReg_Low 0x00 /* r curr. transfer count */
508#define CtcReg_Mid 0x04 /* r */
509#define CtcReg_High 0x38 /* r */
510#define ScsiFifo 0x08
511#define ScsiCmd 0x0C
512#define Scsi_Status 0x10 /* r */
513#define INT_Status 0x14 /* r */
514#define Sync_Period 0x18 /* w */
515#define Sync_Offset 0x1C /* w */
516#define Clk_Factor 0x24 /* w */
517#define CtrlReg1 0x20
518#define CtrlReg2 0x2C
519#define CtrlReg3 0x30
520#define CtrlReg4 0x34
521#define DMA_Cmd 0x40
522#define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */
523#define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */
524#define DMA_Wk_ByteCntr 0x4C /* r working byte counter */
525#define DMA_Wk_AddrCntr 0x50 /* r working address counter */
526#define DMA_Status 0x54 /* r */
527#define DMA_MDL_Addr 0x58 /* rw starting MDL address */
528#define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */
529#define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */
530
531#define StcReg_Low CtcReg_Low /* w start transfer count */
532#define StcReg_Mid CtcReg_Mid /* w */
533#define StcReg_High CtcReg_High /* w */
534#define Scsi_Dest_ID Scsi_Status /* w */
535#define Scsi_TimeOut INT_Status /* w */
536#define Intern_State Sync_Period /* r */
537#define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */
538
539
540#define DC390_read8(address) \
541 (inb (pACB->IOPortBase + (address)))
542
543#define DC390_read8_(address, base) \
544 (inb ((u16)(base) + (address)))
545
546#define DC390_read16(address) \
547 (inw (pACB->IOPortBase + (address)))
548
549#define DC390_read32(address) \
550 (inl (pACB->IOPortBase + (address)))
551
552#define DC390_write8(address,value) \
553 outb ((value), pACB->IOPortBase + (address))
554
555#define DC390_write8_(address,value,base) \
556 outb ((value), (u16)(base) + (address))
557
558#define DC390_write16(address,value) \
559 outw ((value), pACB->IOPortBase + (address))
560
561#define DC390_write32(address,value) \
562 outl ((value), pACB->IOPortBase + (address))
563
564
565#endif /* _TMSCSIM_H */