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authorJeff Garzik <jgarzik@pobox.com>2005-08-29 15:59:42 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-08-29 15:59:42 -0400
commit70d374ea9907036e15574a5ce89219edd5baee10 (patch)
treeb858bb4a841eb91b1d91b41c33698d05fa7bfb37 /drivers/scsi/sata_svw.c
parentaa7e16d6b88b3b38db0d2ee49ed5e44e7b2045ec (diff)
parentbf4e70e54cf31dcca48d279c7f7e71328eebe749 (diff)
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'drivers/scsi/sata_svw.c')
-rw-r--r--drivers/scsi/sata_svw.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/scsi/sata_svw.c b/drivers/scsi/sata_svw.c
index 3884a3cce75c..19d3bb3b0fb6 100644
--- a/drivers/scsi/sata_svw.c
+++ b/drivers/scsi/sata_svw.c
@@ -200,18 +200,18 @@ static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
200 /* start host DMA transaction */ 200 /* start host DMA transaction */
201 dmactl = readb(mmio + ATA_DMA_CMD); 201 dmactl = readb(mmio + ATA_DMA_CMD);
202 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); 202 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
203 /* There is a race condition in certain SATA controllers that can 203 /* There is a race condition in certain SATA controllers that can
204 be seen when the r/w command is given to the controller before the 204 be seen when the r/w command is given to the controller before the
205 host DMA is started. On a Read command, the controller would initiate 205 host DMA is started. On a Read command, the controller would initiate
206 the command to the drive even before it sees the DMA start. When there 206 the command to the drive even before it sees the DMA start. When there
207 are very fast drives connected to the controller, or when the data request 207 are very fast drives connected to the controller, or when the data request
208 hits in the drive cache, there is the possibility that the drive returns a part 208 hits in the drive cache, there is the possibility that the drive returns a part
209 or all of the requested data to the controller before the DMA start is issued. 209 or all of the requested data to the controller before the DMA start is issued.
210 In this case, the controller would become confused as to what to do with the data. 210 In this case, the controller would become confused as to what to do with the data.
211 In the worst case when all the data is returned back to the controller, the 211 In the worst case when all the data is returned back to the controller, the
212 controller could hang. In other cases it could return partial data returning 212 controller could hang. In other cases it could return partial data returning
213 in data corruption. This problem has been seen in PPC systems and can also appear 213 in data corruption. This problem has been seen in PPC systems and can also appear
214 on an system with very fast disks, where the SATA controller is sitting behind a 214 on an system with very fast disks, where the SATA controller is sitting behind a
215 number of bridges, and hence there is significant latency between the r/w command 215 number of bridges, and hence there is significant latency between the r/w command
216 and the start command. */ 216 and the start command. */
217 /* issue r/w command if the access is to ATA*/ 217 /* issue r/w command if the access is to ATA*/
@@ -219,7 +219,7 @@ static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
219 ap->ops->exec_command(ap, &qc->tf); 219 ap->ops->exec_command(ap, &qc->tf);
220} 220}
221 221
222 222
223static u8 k2_stat_check_status(struct ata_port *ap) 223static u8 k2_stat_check_status(struct ata_port *ap)
224{ 224{
225 return readl((void *) ap->ioaddr.status_addr); 225 return readl((void *) ap->ioaddr.status_addr);