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authorJeff Garzik <jgarzik@pobox.com>2005-07-31 13:13:24 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-07-31 13:13:24 -0400
commit8a60a07129fad60bba779a2a4038c7518b167fc7 (patch)
tree3bec0fea8b4c98c51d8865d5144068420f0fd09f /drivers/scsi/sata_svw.c
parent541134cfe7af179f45458b68421ee1da7bab9cba (diff)
libata: trim trailing whitespace.
Also, fixup a tabs-to-spaces block of code in ata_piix.
Diffstat (limited to 'drivers/scsi/sata_svw.c')
-rw-r--r--drivers/scsi/sata_svw.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/scsi/sata_svw.c b/drivers/scsi/sata_svw.c
index 858e07185dbd..6fd2ce1ffcd8 100644
--- a/drivers/scsi/sata_svw.c
+++ b/drivers/scsi/sata_svw.c
@@ -195,18 +195,18 @@ static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
195 /* start host DMA transaction */ 195 /* start host DMA transaction */
196 dmactl = readb(mmio + ATA_DMA_CMD); 196 dmactl = readb(mmio + ATA_DMA_CMD);
197 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); 197 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
198 /* There is a race condition in certain SATA controllers that can 198 /* There is a race condition in certain SATA controllers that can
199 be seen when the r/w command is given to the controller before the 199 be seen when the r/w command is given to the controller before the
200 host DMA is started. On a Read command, the controller would initiate 200 host DMA is started. On a Read command, the controller would initiate
201 the command to the drive even before it sees the DMA start. When there 201 the command to the drive even before it sees the DMA start. When there
202 are very fast drives connected to the controller, or when the data request 202 are very fast drives connected to the controller, or when the data request
203 hits in the drive cache, there is the possibility that the drive returns a part 203 hits in the drive cache, there is the possibility that the drive returns a part
204 or all of the requested data to the controller before the DMA start is issued. 204 or all of the requested data to the controller before the DMA start is issued.
205 In this case, the controller would become confused as to what to do with the data. 205 In this case, the controller would become confused as to what to do with the data.
206 In the worst case when all the data is returned back to the controller, the 206 In the worst case when all the data is returned back to the controller, the
207 controller could hang. In other cases it could return partial data returning 207 controller could hang. In other cases it could return partial data returning
208 in data corruption. This problem has been seen in PPC systems and can also appear 208 in data corruption. This problem has been seen in PPC systems and can also appear
209 on an system with very fast disks, where the SATA controller is sitting behind a 209 on an system with very fast disks, where the SATA controller is sitting behind a
210 number of bridges, and hence there is significant latency between the r/w command 210 number of bridges, and hence there is significant latency between the r/w command
211 and the start command. */ 211 and the start command. */
212 /* issue r/w command if the access is to ATA*/ 212 /* issue r/w command if the access is to ATA*/
@@ -214,7 +214,7 @@ static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
214 ap->ops->exec_command(ap, &qc->tf); 214 ap->ops->exec_command(ap, &qc->tf);
215} 215}
216 216
217 217
218static u8 k2_stat_check_status(struct ata_port *ap) 218static u8 k2_stat_check_status(struct ata_port *ap)
219{ 219{
220 return readl((void *) ap->ioaddr.status_addr); 220 return readl((void *) ap->ioaddr.status_addr);