diff options
author | Jeff Garzik <jgarzik@pobox.com> | 2005-09-08 23:07:29 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-09-08 23:07:29 -0400 |
commit | 8add788574694c5aed04fcb281a5c999e40cd8f6 (patch) | |
tree | 9a28fed2e305c69f9c226e330c7541082809a6a2 /drivers/scsi/sata_sis.c | |
parent | 03981f2427c767cfcd917cb51197c43fe68ba5db (diff) |
[libata] minor fixes
* sata_mv: remove pci_intx(), now that the same function is in PCI core
* sata_sis: fix variable initialization bug, trim trailing whitespace
Diffstat (limited to 'drivers/scsi/sata_sis.c')
-rw-r--r-- | drivers/scsi/sata_sis.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/scsi/sata_sis.c b/drivers/scsi/sata_sis.c index 2bd3f11ac010..a63f93186e41 100644 --- a/drivers/scsi/sata_sis.c +++ b/drivers/scsi/sata_sis.c | |||
@@ -55,7 +55,7 @@ enum { | |||
55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ | 55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | 56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ |
57 | SIS_PMR = 0x90, /* port mapping register */ | 57 | SIS_PMR = 0x90, /* port mapping register */ |
58 | SIS_PMR_COMBINED = 0x30, | 58 | SIS_PMR_COMBINED = 0x30, |
59 | 59 | ||
60 | /* random bits */ | 60 | /* random bits */ |
61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | 61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ |
@@ -147,11 +147,13 @@ static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, | |||
147 | { | 147 | { |
148 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); | 148 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); |
149 | 149 | ||
150 | if (port_no) | 150 | if (port_no) { |
151 | if (device == 0x182) | 151 | if (device == 0x182) |
152 | addr += SIS182_SATA1_OFS; | 152 | addr += SIS182_SATA1_OFS; |
153 | else | 153 | else |
154 | addr += SIS180_SATA1_OFS; | 154 | addr += SIS180_SATA1_OFS; |
155 | } | ||
156 | |||
155 | return addr; | 157 | return addr; |
156 | } | 158 | } |
157 | 159 | ||
@@ -166,10 +168,10 @@ static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |||
166 | return 0xffffffff; | 168 | return 0xffffffff; |
167 | 169 | ||
168 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | 170 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
169 | 171 | ||
170 | pci_read_config_dword(pdev, cfg_addr, &val); | 172 | pci_read_config_dword(pdev, cfg_addr, &val); |
171 | 173 | ||
172 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | 174 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
173 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); | 175 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
174 | 176 | ||
175 | return val|val2; | 177 | return val|val2; |
@@ -185,7 +187,7 @@ static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) | |||
185 | return; | 187 | return; |
186 | 188 | ||
187 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | 189 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
188 | 190 | ||
189 | pci_write_config_dword(pdev, cfg_addr, val); | 191 | pci_write_config_dword(pdev, cfg_addr, val); |
190 | 192 | ||
191 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | 193 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
@@ -195,7 +197,7 @@ static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) | |||
195 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | 197 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) |
196 | { | 198 | { |
197 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | 199 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
198 | u32 val,val2; | 200 | u32 val, val2 = 0; |
199 | u8 pmr; | 201 | u8 pmr; |
200 | 202 | ||
201 | if (sc_reg > SCR_CONTROL) | 203 | if (sc_reg > SCR_CONTROL) |
@@ -209,9 +211,9 @@ static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
209 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | 211 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
210 | 212 | ||
211 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | 213 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
212 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); | 214 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
213 | 215 | ||
214 | return val|val2; | 216 | return val | val2; |
215 | } | 217 | } |
216 | 218 | ||
217 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | 219 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
@@ -223,7 +225,7 @@ static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |||
223 | return; | 225 | return; |
224 | 226 | ||
225 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | 227 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
226 | 228 | ||
227 | if (ap->flags & SIS_FLAG_CFGSCR) | 229 | if (ap->flags & SIS_FLAG_CFGSCR) |
228 | sis_scr_cfg_write(ap, sc_reg, val); | 230 | sis_scr_cfg_write(ap, sc_reg, val); |
229 | else { | 231 | else { |