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authorJeff Garzik <jeff@garzik.org>2006-03-22 23:50:50 -0500
committerJeff Garzik <jeff@garzik.org>2006-03-22 23:50:50 -0500
commit10ad05df14fb5b6ac1fcdaa312a9c13e77627a97 (patch)
treef2a5fd8d251d42eda6cc2ce7a4012138df1a447c /drivers/scsi/sata_nv.c
parent142877b07fe1ef1816513b20f65a51c6ffcadb8b (diff)
[libata sata_nv] cleanups: convert #defines to enums; remove in-file history
Diffstat (limited to 'drivers/scsi/sata_nv.c')
-rw-r--r--drivers/scsi/sata_nv.c124
1 files changed, 49 insertions, 75 deletions
diff --git a/drivers/scsi/sata_nv.c b/drivers/scsi/sata_nv.c
index e5b20c6afc18..834003eb36a7 100644
--- a/drivers/scsi/sata_nv.c
+++ b/drivers/scsi/sata_nv.c
@@ -29,34 +29,6 @@
29 * NV-specific details such as register offsets, SATA phy location, 29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc. 30 * hotplug info, etc.
31 * 31 *
32 * 0.10
33 * - Fixed spurious interrupts issue seen with the Maxtor 6H500F0 500GB
34 * drive. Also made the check_hotplug() callbacks return whether there
35 * was a hotplug interrupt or not. This was not the source of the
36 * spurious interrupts, but is the right thing to do anyway.
37 *
38 * 0.09
39 * - Fixed bug introduced by 0.08's MCP51 and MCP55 support.
40 *
41 * 0.08
42 * - Added support for MCP51 and MCP55.
43 *
44 * 0.07
45 * - Added support for RAID class code.
46 *
47 * 0.06
48 * - Added generic SATA support by using a pci_device_id that filters on
49 * the IDE storage class code.
50 *
51 * 0.03
52 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
53 * mmio_base, which is only set for the CK804/MCP04 case.
54 *
55 * 0.02
56 * - Added support for CK804 SATA controller.
57 *
58 * 0.01
59 * - Initial revision.
60 */ 32 */
61 33
62#include <linux/config.h> 34#include <linux/config.h>
@@ -74,53 +46,55 @@
74#define DRV_NAME "sata_nv" 46#define DRV_NAME "sata_nv"
75#define DRV_VERSION "0.8" 47#define DRV_VERSION "0.8"
76 48
77#define NV_PORTS 2 49enum {
78#define NV_PIO_MASK 0x1f 50 NV_PORTS = 2,
79#define NV_MWDMA_MASK 0x07 51 NV_PIO_MASK = 0x1f,
80#define NV_UDMA_MASK 0x7f 52 NV_MWDMA_MASK = 0x07,
81#define NV_PORT0_SCR_REG_OFFSET 0x00 53 NV_UDMA_MASK = 0x7f,
82#define NV_PORT1_SCR_REG_OFFSET 0x40 54 NV_PORT0_SCR_REG_OFFSET = 0x00,
83 55 NV_PORT1_SCR_REG_OFFSET = 0x40,
84#define NV_INT_STATUS 0x10 56
85#define NV_INT_STATUS_CK804 0x440 57 NV_INT_STATUS = 0x10,
86#define NV_INT_STATUS_PDEV_INT 0x01 58 NV_INT_STATUS_CK804 = 0x440,
87#define NV_INT_STATUS_PDEV_PM 0x02 59 NV_INT_STATUS_PDEV_INT = 0x01,
88#define NV_INT_STATUS_PDEV_ADDED 0x04 60 NV_INT_STATUS_PDEV_PM = 0x02,
89#define NV_INT_STATUS_PDEV_REMOVED 0x08 61 NV_INT_STATUS_PDEV_ADDED = 0x04,
90#define NV_INT_STATUS_SDEV_INT 0x10 62 NV_INT_STATUS_PDEV_REMOVED = 0x08,
91#define NV_INT_STATUS_SDEV_PM 0x20 63 NV_INT_STATUS_SDEV_INT = 0x10,
92#define NV_INT_STATUS_SDEV_ADDED 0x40 64 NV_INT_STATUS_SDEV_PM = 0x20,
93#define NV_INT_STATUS_SDEV_REMOVED 0x80 65 NV_INT_STATUS_SDEV_ADDED = 0x40,
94#define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \ 66 NV_INT_STATUS_SDEV_REMOVED = 0x80,
95 NV_INT_STATUS_PDEV_REMOVED) 67 NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED |
96#define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \ 68 NV_INT_STATUS_PDEV_REMOVED),
97 NV_INT_STATUS_SDEV_REMOVED) 69 NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED |
98#define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \ 70 NV_INT_STATUS_SDEV_REMOVED),
99 NV_INT_STATUS_SDEV_HOTPLUG) 71 NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG |
100 72 NV_INT_STATUS_SDEV_HOTPLUG),
101#define NV_INT_ENABLE 0x11 73
102#define NV_INT_ENABLE_CK804 0x441 74 NV_INT_ENABLE = 0x11,
103#define NV_INT_ENABLE_PDEV_MASK 0x01 75 NV_INT_ENABLE_CK804 = 0x441,
104#define NV_INT_ENABLE_PDEV_PM 0x02 76 NV_INT_ENABLE_PDEV_MASK = 0x01,
105#define NV_INT_ENABLE_PDEV_ADDED 0x04 77 NV_INT_ENABLE_PDEV_PM = 0x02,
106#define NV_INT_ENABLE_PDEV_REMOVED 0x08 78 NV_INT_ENABLE_PDEV_ADDED = 0x04,
107#define NV_INT_ENABLE_SDEV_MASK 0x10 79 NV_INT_ENABLE_PDEV_REMOVED = 0x08,
108#define NV_INT_ENABLE_SDEV_PM 0x20 80 NV_INT_ENABLE_SDEV_MASK = 0x10,
109#define NV_INT_ENABLE_SDEV_ADDED 0x40 81 NV_INT_ENABLE_SDEV_PM = 0x20,
110#define NV_INT_ENABLE_SDEV_REMOVED 0x80 82 NV_INT_ENABLE_SDEV_ADDED = 0x40,
111#define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \ 83 NV_INT_ENABLE_SDEV_REMOVED = 0x80,
112 NV_INT_ENABLE_PDEV_REMOVED) 84 NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED |
113#define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \ 85 NV_INT_ENABLE_PDEV_REMOVED),
114 NV_INT_ENABLE_SDEV_REMOVED) 86 NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED |
115#define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \ 87 NV_INT_ENABLE_SDEV_REMOVED),
116 NV_INT_ENABLE_SDEV_HOTPLUG) 88 NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG |
117 89 NV_INT_ENABLE_SDEV_HOTPLUG),
118#define NV_INT_CONFIG 0x12 90
119#define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI 91 NV_INT_CONFIG = 0x12,
120 92 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
121// For PCI config register 20 93
122#define NV_MCP_SATA_CFG_20 0x50 94 // For PCI config register 20
123#define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04 95 NV_MCP_SATA_CFG_20 = 0x50,
96 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
97};
124 98
125static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 99static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
126static irqreturn_t nv_interrupt (int irq, void *dev_instance, 100static irqreturn_t nv_interrupt (int irq, void *dev_instance,
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 00:19:53 -0400