diff options
author | Jeff Garzik <jgarzik@pobox.com> | 2005-11-12 09:50:49 -0500 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-11-12 09:50:49 -0500 |
commit | 095fec887eaa1c38d17c0c929a6733c744a9fa1f (patch) | |
tree | 514d030ed343eab5c8aea18efea472b7ca6d393c /drivers/scsi/sata_mv.c | |
parent | 02eaa66629a29cd5712fe81a360c3ab5b1fc9531 (diff) |
[libata sata_mv] minor fixes
- clear SError and EDMA irq cause registers, after re-init'ing the phy
- move enums with type suffix 'U' to their own enum
Diffstat (limited to 'drivers/scsi/sata_mv.c')
-rw-r--r-- | drivers/scsi/sata_mv.c | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/drivers/scsi/sata_mv.c b/drivers/scsi/sata_mv.c index 257c128f4aaa..82d1750e779b 100644 --- a/drivers/scsi/sata_mv.c +++ b/drivers/scsi/sata_mv.c | |||
@@ -72,11 +72,6 @@ enum { | |||
72 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), | 72 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
73 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), | 73 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), |
74 | 74 | ||
75 | /* Our DMA boundary is determined by an ePRD being unable to handle | ||
76 | * anything larger than 64KB | ||
77 | */ | ||
78 | MV_DMA_BOUNDARY = 0xffffU, | ||
79 | |||
80 | MV_PORTS_PER_HC = 4, | 75 | MV_PORTS_PER_HC = 4, |
81 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ | 76 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ |
82 | MV_PORT_HC_SHIFT = 2, | 77 | MV_PORT_HC_SHIFT = 2, |
@@ -192,7 +187,6 @@ enum { | |||
192 | 187 | ||
193 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, | 188 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
194 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ | 189 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ |
195 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, | ||
196 | 190 | ||
197 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, | 191 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, |
198 | EDMA_REQ_Q_PTR_SHIFT = 5, | 192 | EDMA_REQ_Q_PTR_SHIFT = 5, |
@@ -200,7 +194,6 @@ enum { | |||
200 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, | 194 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, |
201 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, | 195 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, |
202 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ | 196 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ |
203 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, | ||
204 | EDMA_RSP_Q_PTR_SHIFT = 3, | 197 | EDMA_RSP_Q_PTR_SHIFT = 3, |
205 | 198 | ||
206 | EDMA_CMD_OFS = 0x28, | 199 | EDMA_CMD_OFS = 0x28, |
@@ -216,6 +209,17 @@ enum { | |||
216 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), | 209 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), |
217 | }; | 210 | }; |
218 | 211 | ||
212 | enum { | ||
213 | /* Our DMA boundary is determined by an ePRD being unable to handle | ||
214 | * anything larger than 64KB | ||
215 | */ | ||
216 | MV_DMA_BOUNDARY = 0xffffU, | ||
217 | |||
218 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, | ||
219 | |||
220 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, | ||
221 | }; | ||
222 | |||
219 | /* Command ReQuest Block: 32B */ | 223 | /* Command ReQuest Block: 32B */ |
220 | struct mv_crqb { | 224 | struct mv_crqb { |
221 | u32 sg_addr; | 225 | u32 sg_addr; |
@@ -1215,6 +1219,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance, | |||
1215 | */ | 1219 | */ |
1216 | static void mv_phy_reset(struct ata_port *ap) | 1220 | static void mv_phy_reset(struct ata_port *ap) |
1217 | { | 1221 | { |
1222 | struct mv_port_priv *pp = ap->private_data; | ||
1218 | void __iomem *port_mmio = mv_ap_base(ap); | 1223 | void __iomem *port_mmio = mv_ap_base(ap); |
1219 | struct ata_taskfile tf; | 1224 | struct ata_taskfile tf; |
1220 | struct ata_device *dev = &ap->device[0]; | 1225 | struct ata_device *dev = &ap->device[0]; |
@@ -1232,7 +1237,7 @@ static void mv_phy_reset(struct ata_port *ap) | |||
1232 | */ | 1237 | */ |
1233 | writelfl(0, port_mmio + EDMA_CMD_OFS); | 1238 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
1234 | 1239 | ||
1235 | VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " | 1240 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
1236 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), | 1241 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1237 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | 1242 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); |
1238 | 1243 | ||
@@ -1247,7 +1252,9 @@ static void mv_phy_reset(struct ata_port *ap) | |||
1247 | break; | 1252 | break; |
1248 | } while (time_before(jiffies, timeout)); | 1253 | } while (time_before(jiffies, timeout)); |
1249 | 1254 | ||
1250 | VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | 1255 | mv_scr_write(ap, SCR_ERROR, mv_scr_read(ap, SCR_ERROR)); |
1256 | |||
1257 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | ||
1251 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), | 1258 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1252 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | 1259 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); |
1253 | 1260 | ||
@@ -1271,7 +1278,12 @@ static void mv_phy_reset(struct ata_port *ap) | |||
1271 | VPRINTK("Port disabled post-sig: No device present.\n"); | 1278 | VPRINTK("Port disabled post-sig: No device present.\n"); |
1272 | ata_port_disable(ap); | 1279 | ata_port_disable(ap); |
1273 | } | 1280 | } |
1274 | VPRINTK("EXIT\n"); | 1281 | |
1282 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | ||
1283 | |||
1284 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | ||
1285 | |||
1286 | printk("EXIT\n"); | ||
1275 | } | 1287 | } |
1276 | 1288 | ||
1277 | /** | 1289 | /** |