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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-02 22:01:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-02 22:01:32 -0400
commit3151367f8778a1789d6f6e6f6c642681b6cd6d64 (patch)
tree1869d5429a25abd994ae94079808b8db060ec6f3 /drivers/scsi/qla4xxx/ql4_nx.c
parent16642a2e7be23bbda013fc32d8f6c68982eab603 (diff)
parentfe709ed827d370e6b0c0a9f9456da1c22bdcd118 (diff)
Merge tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull first round of SCSI updates from James Bottomley: "This is a large set of updates, mostly for drivers (qla2xxx [including support for new 83xx based card], qla4xxx, mpt2sas, bfa, zfcp, hpsa, be2iscsi, isci, lpfc, ipr, ibmvfc, ibmvscsi, megaraid_sas). There's also a rework for tape adding virtually unlimited numbers of tape drives plus a set of dif fixes for sd and a fix for a live lock on hot remove of SCSI devices. This round includes a signed tag pull of isci-for-3.6 Signed-off-by: James Bottomley <JBottomley@Parallels.com>" Fix up trivial conflict in drivers/scsi/qla2xxx/qla_nx.c due to new PCI helper function use in a function that was removed by this pull. * tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (198 commits) [SCSI] st: remove st_mutex [SCSI] sd: Ensure we correctly disable devices with unknown protection type [SCSI] hpsa: gen8plus Smart Array IDs [SCSI] qla4xxx: Update driver version to 5.03.00-k1 [SCSI] qla4xxx: Disable generating pause frames for ISP83XX [SCSI] qla4xxx: Fix double clearing of risc_intr for ISP83XX [SCSI] qla4xxx: IDC implementation for Loopback [SCSI] qla4xxx: update copyrights in LICENSE.qla4xxx [SCSI] qla4xxx: Fix panic while rmmod [SCSI] qla4xxx: Fail probe_adapter if IRQ allocation fails [SCSI] qla4xxx: Prevent MSI/MSI-X falling back to INTx for ISP82XX [SCSI] qla4xxx: Update idc reg in case of PCI AER [SCSI] qla4xxx: Fix double IDC locking in qla4_8xxx_error_recovery [SCSI] qla4xxx: Clear interrupt while unloading driver for ISP83XX [SCSI] qla4xxx: Print correct IDC version [SCSI] qla4xxx: Added new mbox cmd to pass driver version to FW [SCSI] scsi_dh_alua: Enable STPG for unavailable ports [SCSI] scsi_remove_target: fix softlockup regression on hot remove [SCSI] ibmvscsi: Fix host config length field overflow [SCSI] ibmvscsi: Remove backend abstraction ...
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_nx.c')
-rw-r--r--drivers/scsi/qla4xxx/ql4_nx.c1432
1 files changed, 957 insertions, 475 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index 807bf76f1b6a..499a92db1cf6 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * QLogic iSCSI HBA Driver 2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation 3 * Copyright (c) 2003-2012 QLogic Corporation
4 * 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details. 5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */ 6 */
@@ -10,6 +10,7 @@
10#include <linux/ratelimit.h> 10#include <linux/ratelimit.h>
11#include "ql4_def.h" 11#include "ql4_def.h"
12#include "ql4_glbl.h" 12#include "ql4_glbl.h"
13#include "ql4_inline.h"
13 14
14#include <asm-generic/io-64-nonatomic-lo-hi.h> 15#include <asm-generic/io-64-nonatomic-lo-hi.h>
15 16
@@ -27,7 +28,7 @@
27#define CRB_BLK(off) ((off >> 20) & 0x3f) 28#define CRB_BLK(off) ((off >> 20) & 0x3f)
28#define CRB_SUBBLK(off) ((off >> 16) & 0xf) 29#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
29#define CRB_WINDOW_2M (0x130060) 30#define CRB_WINDOW_2M (0x130060)
30#define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 31#define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
31 ((off) & 0xf0000)) 32 ((off) & 0xf0000))
32#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 33#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
@@ -51,7 +52,7 @@ static int qla4_8xxx_crb_table_initialized;
51 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 52 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
52 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 53 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
53static void 54static void
54qla4_8xxx_crb_addr_transform_setup(void) 55qla4_82xx_crb_addr_transform_setup(void)
55{ 56{
56 qla4_8xxx_crb_addr_transform(XDMA); 57 qla4_8xxx_crb_addr_transform(XDMA);
57 qla4_8xxx_crb_addr_transform(TIMR); 58 qla4_8xxx_crb_addr_transform(TIMR);
@@ -268,7 +269,7 @@ static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
268/* 269/*
269 * top 12 bits of crb internal address (hub, agent) 270 * top 12 bits of crb internal address (hub, agent)
270 */ 271 */
271static unsigned qla4_8xxx_crb_hub_agt[64] = { 272static unsigned qla4_82xx_crb_hub_agt[64] = {
272 0, 273 0,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
@@ -353,7 +354,7 @@ static char *qdev_state[] = {
353 * side effect: lock crb window 354 * side effect: lock crb window
354 */ 355 */
355static void 356static void
356qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 357qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
357{ 358{
358 u32 win_read; 359 u32 win_read;
359 360
@@ -373,96 +374,115 @@ qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
373} 374}
374 375
375void 376void
376qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 377qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
377{ 378{
378 unsigned long flags = 0; 379 unsigned long flags = 0;
379 int rv; 380 int rv;
380 381
381 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 382 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
382 383
383 BUG_ON(rv == -1); 384 BUG_ON(rv == -1);
384 385
385 if (rv == 1) { 386 if (rv == 1) {
386 write_lock_irqsave(&ha->hw_lock, flags); 387 write_lock_irqsave(&ha->hw_lock, flags);
387 qla4_8xxx_crb_win_lock(ha); 388 qla4_82xx_crb_win_lock(ha);
388 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 389 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
389 } 390 }
390 391
391 writel(data, (void __iomem *)off); 392 writel(data, (void __iomem *)off);
392 393
393 if (rv == 1) { 394 if (rv == 1) {
394 qla4_8xxx_crb_win_unlock(ha); 395 qla4_82xx_crb_win_unlock(ha);
395 write_unlock_irqrestore(&ha->hw_lock, flags); 396 write_unlock_irqrestore(&ha->hw_lock, flags);
396 } 397 }
397} 398}
398 399
399int 400uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
400qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
401{ 401{
402 unsigned long flags = 0; 402 unsigned long flags = 0;
403 int rv; 403 int rv;
404 u32 data; 404 u32 data;
405 405
406 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 406 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
407 407
408 BUG_ON(rv == -1); 408 BUG_ON(rv == -1);
409 409
410 if (rv == 1) { 410 if (rv == 1) {
411 write_lock_irqsave(&ha->hw_lock, flags); 411 write_lock_irqsave(&ha->hw_lock, flags);
412 qla4_8xxx_crb_win_lock(ha); 412 qla4_82xx_crb_win_lock(ha);
413 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 413 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
414 } 414 }
415 data = readl((void __iomem *)off); 415 data = readl((void __iomem *)off);
416 416
417 if (rv == 1) { 417 if (rv == 1) {
418 qla4_8xxx_crb_win_unlock(ha); 418 qla4_82xx_crb_win_unlock(ha);
419 write_unlock_irqrestore(&ha->hw_lock, flags); 419 write_unlock_irqrestore(&ha->hw_lock, flags);
420 } 420 }
421 return data; 421 return data;
422} 422}
423 423
424/* Minidump related functions */ 424/* Minidump related functions */
425static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off, 425int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
426 u32 data, uint8_t flag)
427{ 426{
428 uint32_t win_read, off_value, rval = QLA_SUCCESS; 427 uint32_t win_read, off_value;
428 int rval = QLA_SUCCESS;
429 429
430 off_value = off & 0xFFFF0000; 430 off_value = off & 0xFFFF0000;
431 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 431 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
432 432
433 /* Read back value to make sure write has gone through before trying 433 /*
434 * Read back value to make sure write has gone through before trying
434 * to use it. 435 * to use it.
435 */ 436 */
436 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 437 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
437 if (win_read != off_value) { 438 if (win_read != off_value) {
438 DEBUG2(ql4_printk(KERN_INFO, ha, 439 DEBUG2(ql4_printk(KERN_INFO, ha,
439 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 440 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
440 __func__, off_value, win_read, off)); 441 __func__, off_value, win_read, off));
441 return QLA_ERROR; 442 rval = QLA_ERROR;
443 } else {
444 off_value = off & 0x0000FFFF;
445 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
446 ha->nx_pcibase));
442 } 447 }
448 return rval;
449}
443 450
444 off_value = off & 0x0000FFFF; 451int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
452{
453 uint32_t win_read, off_value;
454 int rval = QLA_SUCCESS;
455
456 off_value = off & 0xFFFF0000;
457 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
445 458
446 if (flag) 459 /* Read back value to make sure write has gone through before trying
460 * to use it.
461 */
462 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
463 if (win_read != off_value) {
464 DEBUG2(ql4_printk(KERN_INFO, ha,
465 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
466 __func__, off_value, win_read, off));
467 rval = QLA_ERROR;
468 } else {
469 off_value = off & 0x0000FFFF;
447 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 470 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
448 ha->nx_pcibase)); 471 ha->nx_pcibase));
449 else 472 }
450 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
451 ha->nx_pcibase));
452
453 return rval; 473 return rval;
454} 474}
455 475
456#define CRB_WIN_LOCK_TIMEOUT 100000000 476#define CRB_WIN_LOCK_TIMEOUT 100000000
457 477
458int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha) 478int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
459{ 479{
460 int i; 480 int i;
461 int done = 0, timeout = 0; 481 int done = 0, timeout = 0;
462 482
463 while (!done) { 483 while (!done) {
464 /* acquire semaphore3 from PCI HW block */ 484 /* acquire semaphore3 from PCI HW block */
465 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 485 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
466 if (done == 1) 486 if (done == 1)
467 break; 487 break;
468 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 488 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
@@ -478,32 +498,32 @@ int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
478 cpu_relax(); /*This a nop instr on i386*/ 498 cpu_relax(); /*This a nop instr on i386*/
479 } 499 }
480 } 500 }
481 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 501 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
482 return 0; 502 return 0;
483} 503}
484 504
485void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha) 505void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
486{ 506{
487 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 507 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
488} 508}
489 509
490#define IDC_LOCK_TIMEOUT 100000000 510#define IDC_LOCK_TIMEOUT 100000000
491 511
492/** 512/**
493 * qla4_8xxx_idc_lock - hw_lock 513 * qla4_82xx_idc_lock - hw_lock
494 * @ha: pointer to adapter structure 514 * @ha: pointer to adapter structure
495 * 515 *
496 * General purpose lock used to synchronize access to 516 * General purpose lock used to synchronize access to
497 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 517 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
498 **/ 518 **/
499int qla4_8xxx_idc_lock(struct scsi_qla_host *ha) 519int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
500{ 520{
501 int i; 521 int i;
502 int done = 0, timeout = 0; 522 int done = 0, timeout = 0;
503 523
504 while (!done) { 524 while (!done) {
505 /* acquire semaphore5 from PCI HW block */ 525 /* acquire semaphore5 from PCI HW block */
506 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
507 if (done == 1) 527 if (done == 1)
508 break; 528 break;
509 if (timeout >= IDC_LOCK_TIMEOUT) 529 if (timeout >= IDC_LOCK_TIMEOUT)
@@ -522,13 +542,13 @@ int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
522 return 0; 542 return 0;
523} 543}
524 544
525void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha) 545void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
526{ 546{
527 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
528} 548}
529 549
530int 550int
531qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 551qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
532{ 552{
533 struct crb_128M_2M_sub_block_map *m; 553 struct crb_128M_2M_sub_block_map *m;
534 554
@@ -562,44 +582,40 @@ qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
562 return 1; 582 return 1;
563} 583}
564 584
565/* PCI Windowing for DDR regions. */
566#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
567 (((addr) <= (high)) && ((addr) >= (low)))
568
569/* 585/*
570* check memory access boundary. 586* check memory access boundary.
571* used by test agent. support ddr access only for now 587* used by test agent. support ddr access only for now
572*/ 588*/
573static unsigned long 589static unsigned long
574qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha, 590qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
575 unsigned long long addr, int size) 591 unsigned long long addr, int size)
576{ 592{
577 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 593 if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
578 QLA82XX_ADDR_DDR_NET_MAX) || 594 QLA8XXX_ADDR_DDR_NET_MAX) ||
579 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, 595 !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
580 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || 596 QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
581 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 597 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
582 return 0; 598 return 0;
583 } 599 }
584 return 1; 600 return 1;
585} 601}
586 602
587static int qla4_8xxx_pci_set_window_warning_count; 603static int qla4_82xx_pci_set_window_warning_count;
588 604
589static unsigned long 605static unsigned long
590qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 606qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
591{ 607{
592 int window; 608 int window;
593 u32 win_read; 609 u32 win_read;
594 610
595 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 611 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
596 QLA82XX_ADDR_DDR_NET_MAX)) { 612 QLA8XXX_ADDR_DDR_NET_MAX)) {
597 /* DDR network side */ 613 /* DDR network side */
598 window = MN_WIN(addr); 614 window = MN_WIN(addr);
599 ha->ddr_mn_window = window; 615 ha->ddr_mn_window = window;
600 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 616 qla4_82xx_wr_32(ha, ha->mn_win_crb |
601 QLA82XX_PCI_CRBSPACE, window); 617 QLA82XX_PCI_CRBSPACE, window);
602 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 618 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
603 QLA82XX_PCI_CRBSPACE); 619 QLA82XX_PCI_CRBSPACE);
604 if ((win_read << 17) != window) { 620 if ((win_read << 17) != window) {
605 ql4_printk(KERN_WARNING, ha, 621 ql4_printk(KERN_WARNING, ha,
@@ -607,8 +623,8 @@ qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
607 __func__, window, win_read); 623 __func__, window, win_read);
608 } 624 }
609 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 625 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
610 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 626 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
611 QLA82XX_ADDR_OCM0_MAX)) { 627 QLA8XXX_ADDR_OCM0_MAX)) {
612 unsigned int temp1; 628 unsigned int temp1;
613 /* if bits 19:18&17:11 are on */ 629 /* if bits 19:18&17:11 are on */
614 if ((addr & 0x00ff800) == 0xff800) { 630 if ((addr & 0x00ff800) == 0xff800) {
@@ -618,9 +634,9 @@ qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
618 634
619 window = OCM_WIN(addr); 635 window = OCM_WIN(addr);
620 ha->ddr_mn_window = window; 636 ha->ddr_mn_window = window;
621 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 637 qla4_82xx_wr_32(ha, ha->mn_win_crb |
622 QLA82XX_PCI_CRBSPACE, window); 638 QLA82XX_PCI_CRBSPACE, window);
623 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 639 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
624 QLA82XX_PCI_CRBSPACE); 640 QLA82XX_PCI_CRBSPACE);
625 temp1 = ((window & 0x1FF) << 7) | 641 temp1 = ((window & 0x1FF) << 7) |
626 ((window & 0x0FFFE0000) >> 17); 642 ((window & 0x0FFFE0000) >> 17);
@@ -630,14 +646,14 @@ qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
630 } 646 }
631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 647 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
632 648
633 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 649 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
634 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 650 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
635 /* QDR network side */ 651 /* QDR network side */
636 window = MS_WIN(addr); 652 window = MS_WIN(addr);
637 ha->qdr_sn_window = window; 653 ha->qdr_sn_window = window;
638 qla4_8xxx_wr_32(ha, ha->ms_win_crb | 654 qla4_82xx_wr_32(ha, ha->ms_win_crb |
639 QLA82XX_PCI_CRBSPACE, window); 655 QLA82XX_PCI_CRBSPACE, window);
640 win_read = qla4_8xxx_rd_32(ha, 656 win_read = qla4_82xx_rd_32(ha,
641 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 657 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
642 if (win_read != window) { 658 if (win_read != window) {
643 printk("%s: Written MSwin (0x%x) != Read " 659 printk("%s: Written MSwin (0x%x) != Read "
@@ -650,8 +666,8 @@ qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
650 * peg gdb frequently accesses memory that doesn't exist, 666 * peg gdb frequently accesses memory that doesn't exist,
651 * this limits the chit chat so debugging isn't slowed down. 667 * this limits the chit chat so debugging isn't slowed down.
652 */ 668 */
653 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) || 669 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
654 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) { 670 (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
655 printk("%s: Warning:%s Unknown address range!\n", 671 printk("%s: Warning:%s Unknown address range!\n",
656 __func__, DRIVER_NAME); 672 __func__, DRIVER_NAME);
657 } 673 }
@@ -661,7 +677,7 @@ qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
661} 677}
662 678
663/* check if address is in the same windows as the previous access */ 679/* check if address is in the same windows as the previous access */
664static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha, 680static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
665 unsigned long long addr) 681 unsigned long long addr)
666{ 682{
667 int window; 683 int window;
@@ -669,20 +685,20 @@ static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
669 685
670 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 686 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
671 687
672 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 688 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
673 QLA82XX_ADDR_DDR_NET_MAX)) { 689 QLA8XXX_ADDR_DDR_NET_MAX)) {
674 /* DDR network side */ 690 /* DDR network side */
675 BUG(); /* MN access can not come here */ 691 BUG(); /* MN access can not come here */
676 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 692 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
677 QLA82XX_ADDR_OCM0_MAX)) { 693 QLA8XXX_ADDR_OCM0_MAX)) {
678 return 1; 694 return 1;
679 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 695 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
680 QLA82XX_ADDR_OCM1_MAX)) { 696 QLA8XXX_ADDR_OCM1_MAX)) {
681 return 1; 697 return 1;
682 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 698 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
683 qdr_max)) { 699 qdr_max)) {
684 /* QDR network side */ 700 /* QDR network side */
685 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 701 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
686 if (ha->qdr_sn_window == window) 702 if (ha->qdr_sn_window == window)
687 return 1; 703 return 1;
688 } 704 }
@@ -690,7 +706,7 @@ static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
690 return 0; 706 return 0;
691} 707}
692 708
693static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha, 709static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
694 u64 off, void *data, int size) 710 u64 off, void *data, int size)
695{ 711{
696 unsigned long flags; 712 unsigned long flags;
@@ -707,9 +723,9 @@ static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
707 * If attempting to access unknown address or straddle hw windows, 723 * If attempting to access unknown address or straddle hw windows,
708 * do not access. 724 * do not access.
709 */ 725 */
710 start = qla4_8xxx_pci_set_window(ha, off); 726 start = qla4_82xx_pci_set_window(ha, off);
711 if ((start == -1UL) || 727 if ((start == -1UL) ||
712 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 728 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
713 write_unlock_irqrestore(&ha->hw_lock, flags); 729 write_unlock_irqrestore(&ha->hw_lock, flags);
714 printk(KERN_ERR"%s out of bound pci memory access. " 730 printk(KERN_ERR"%s out of bound pci memory access. "
715 "offset is 0x%llx\n", DRIVER_NAME, off); 731 "offset is 0x%llx\n", DRIVER_NAME, off);
@@ -763,7 +779,7 @@ static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
763} 779}
764 780
765static int 781static int
766qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 782qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
767 void *data, int size) 783 void *data, int size)
768{ 784{
769 unsigned long flags; 785 unsigned long flags;
@@ -780,9 +796,9 @@ qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
780 * If attempting to access unknown address or straddle hw windows, 796 * If attempting to access unknown address or straddle hw windows,
781 * do not access. 797 * do not access.
782 */ 798 */
783 start = qla4_8xxx_pci_set_window(ha, off); 799 start = qla4_82xx_pci_set_window(ha, off);
784 if ((start == -1UL) || 800 if ((start == -1UL) ||
785 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 801 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
786 write_unlock_irqrestore(&ha->hw_lock, flags); 802 write_unlock_irqrestore(&ha->hw_lock, flags);
787 printk(KERN_ERR"%s out of bound pci memory access. " 803 printk(KERN_ERR"%s out of bound pci memory access. "
788 "offset is 0x%llx\n", DRIVER_NAME, off); 804 "offset is 0x%llx\n", DRIVER_NAME, off);
@@ -835,13 +851,13 @@ qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
835#define MTU_FUDGE_FACTOR 100 851#define MTU_FUDGE_FACTOR 100
836 852
837static unsigned long 853static unsigned long
838qla4_8xxx_decode_crb_addr(unsigned long addr) 854qla4_82xx_decode_crb_addr(unsigned long addr)
839{ 855{
840 int i; 856 int i;
841 unsigned long base_addr, offset, pci_base; 857 unsigned long base_addr, offset, pci_base;
842 858
843 if (!qla4_8xxx_crb_table_initialized) 859 if (!qla4_8xxx_crb_table_initialized)
844 qla4_8xxx_crb_addr_transform_setup(); 860 qla4_82xx_crb_addr_transform_setup();
845 861
846 pci_base = ADDR_ERROR; 862 pci_base = ADDR_ERROR;
847 base_addr = addr & 0xfff00000; 863 base_addr = addr & 0xfff00000;
@@ -860,10 +876,10 @@ qla4_8xxx_decode_crb_addr(unsigned long addr)
860} 876}
861 877
862static long rom_max_timeout = 100; 878static long rom_max_timeout = 100;
863static long qla4_8xxx_rom_lock_timeout = 100; 879static long qla4_82xx_rom_lock_timeout = 100;
864 880
865static int 881static int
866qla4_8xxx_rom_lock(struct scsi_qla_host *ha) 882qla4_82xx_rom_lock(struct scsi_qla_host *ha)
867{ 883{
868 int i; 884 int i;
869 int done = 0, timeout = 0; 885 int done = 0, timeout = 0;
@@ -871,10 +887,10 @@ qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
871 while (!done) { 887 while (!done) {
872 /* acquire semaphore2 from PCI HW block */ 888 /* acquire semaphore2 from PCI HW block */
873 889
874 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 890 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
875 if (done == 1) 891 if (done == 1)
876 break; 892 break;
877 if (timeout >= qla4_8xxx_rom_lock_timeout) 893 if (timeout >= qla4_82xx_rom_lock_timeout)
878 return -1; 894 return -1;
879 895
880 timeout++; 896 timeout++;
@@ -887,24 +903,24 @@ qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
887 cpu_relax(); /*This a nop instr on i386*/ 903 cpu_relax(); /*This a nop instr on i386*/
888 } 904 }
889 } 905 }
890 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 906 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
891 return 0; 907 return 0;
892} 908}
893 909
894static void 910static void
895qla4_8xxx_rom_unlock(struct scsi_qla_host *ha) 911qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
896{ 912{
897 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 913 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
898} 914}
899 915
900static int 916static int
901qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha) 917qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
902{ 918{
903 long timeout = 0; 919 long timeout = 0;
904 long done = 0 ; 920 long done = 0 ;
905 921
906 while (done == 0) { 922 while (done == 0) {
907 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 923 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
908 done &= 2; 924 done &= 2;
909 timeout++; 925 timeout++;
910 if (timeout >= rom_max_timeout) { 926 if (timeout >= rom_max_timeout) {
@@ -917,40 +933,41 @@ qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
917} 933}
918 934
919static int 935static int
920qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 936qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
921{ 937{
922 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 938 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
923 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 939 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
924 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 940 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
925 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 941 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
926 if (qla4_8xxx_wait_rom_done(ha)) { 942 if (qla4_82xx_wait_rom_done(ha)) {
927 printk("%s: Error waiting for rom done\n", DRIVER_NAME); 943 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
928 return -1; 944 return -1;
929 } 945 }
930 /* reset abyte_cnt and dummy_byte_cnt */ 946 /* reset abyte_cnt and dummy_byte_cnt */
931 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 947 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
932 udelay(10); 948 udelay(10);
933 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 949 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
934 950
935 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 951 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
936 return 0; 952 return 0;
937} 953}
938 954
939static int 955static int
940qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 956qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
941{ 957{
942 int ret, loops = 0; 958 int ret, loops = 0;
943 959
944 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 960 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
945 udelay(100); 961 udelay(100);
946 loops++; 962 loops++;
947 } 963 }
948 if (loops >= 50000) { 964 if (loops >= 50000) {
949 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME); 965 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
966 DRIVER_NAME);
950 return -1; 967 return -1;
951 } 968 }
952 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp); 969 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
953 qla4_8xxx_rom_unlock(ha); 970 qla4_82xx_rom_unlock(ha);
954 return ret; 971 return ret;
955} 972}
956 973
@@ -959,7 +976,7 @@ qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
959 * to put the ISP into operational state 976 * to put the ISP into operational state
960 **/ 977 **/
961static int 978static int
962qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 979qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
963{ 980{
964 int addr, val; 981 int addr, val;
965 int i ; 982 int i ;
@@ -973,68 +990,68 @@ qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
973 }; 990 };
974 991
975 /* Halt all the indiviual PEGs and other blocks of the ISP */ 992 /* Halt all the indiviual PEGs and other blocks of the ISP */
976 qla4_8xxx_rom_lock(ha); 993 qla4_82xx_rom_lock(ha);
977 994
978 /* disable all I2Q */ 995 /* disable all I2Q */
979 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 996 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
980 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 997 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
981 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 998 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
982 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 999 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
983 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1000 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
984 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1001 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
985 1002
986 /* disable all niu interrupts */ 1003 /* disable all niu interrupts */
987 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1004 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
988 /* disable xge rx/tx */ 1005 /* disable xge rx/tx */
989 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1006 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
990 /* disable xg1 rx/tx */ 1007 /* disable xg1 rx/tx */
991 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1008 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
992 /* disable sideband mac */ 1009 /* disable sideband mac */
993 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1010 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
994 /* disable ap0 mac */ 1011 /* disable ap0 mac */
995 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1012 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
996 /* disable ap1 mac */ 1013 /* disable ap1 mac */
997 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1014 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
998 1015
999 /* halt sre */ 1016 /* halt sre */
1000 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1017 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1001 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1018 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1002 1019
1003 /* halt epg */ 1020 /* halt epg */
1004 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1021 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1005 1022
1006 /* halt timers */ 1023 /* halt timers */
1007 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1024 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1008 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1025 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1009 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1026 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1010 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1027 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1011 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1028 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1012 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1029 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1013 1030
1014 /* halt pegs */ 1031 /* halt pegs */
1015 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1032 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1016 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1033 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1017 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1034 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1018 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1035 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1019 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1036 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1020 msleep(5); 1037 msleep(5);
1021 1038
1022 /* big hammer */ 1039 /* big hammer */
1023 if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1040 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1024 /* don't reset CAM block on reset */ 1041 /* don't reset CAM block on reset */
1025 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1042 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1026 else 1043 else
1027 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1044 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1028 1045
1029 qla4_8xxx_rom_unlock(ha); 1046 qla4_82xx_rom_unlock(ha);
1030 1047
1031 /* Read the signature value from the flash. 1048 /* Read the signature value from the flash.
1032 * Offset 0: Contain signature (0xcafecafe) 1049 * Offset 0: Contain signature (0xcafecafe)
1033 * Offset 4: Offset and number of addr/value pairs 1050 * Offset 4: Offset and number of addr/value pairs
1034 * that present in CRB initialize sequence 1051 * that present in CRB initialize sequence
1035 */ 1052 */
1036 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1053 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1037 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) { 1054 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1038 ql4_printk(KERN_WARNING, ha, 1055 ql4_printk(KERN_WARNING, ha,
1039 "[ERROR] Reading crb_init area: n: %08x\n", n); 1056 "[ERROR] Reading crb_init area: n: %08x\n", n);
1040 return -1; 1057 return -1;
@@ -1065,8 +1082,8 @@ qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
1065 } 1082 }
1066 1083
1067 for (i = 0; i < n; i++) { 1084 for (i = 0; i < n; i++) {
1068 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1085 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1069 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1086 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1070 0) { 1087 0) {
1071 kfree(buf); 1088 kfree(buf);
1072 return -1; 1089 return -1;
@@ -1080,7 +1097,7 @@ qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
1080 /* Translate internal CRB initialization 1097 /* Translate internal CRB initialization
1081 * address to PCI bus address 1098 * address to PCI bus address
1082 */ 1099 */
1083 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) + 1100 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1084 QLA82XX_PCI_CRBSPACE; 1101 QLA82XX_PCI_CRBSPACE;
1085 /* Not all CRB addr/value pair to be written, 1102 /* Not all CRB addr/value pair to be written,
1086 * some of them are skipped 1103 * some of them are skipped
@@ -1125,7 +1142,7 @@ qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
1125 continue; 1142 continue;
1126 } 1143 }
1127 1144
1128 qla4_8xxx_wr_32(ha, off, buf[i].data); 1145 qla4_82xx_wr_32(ha, off, buf[i].data);
1129 1146
1130 /* ISP requires much bigger delay to settle down, 1147 /* ISP requires much bigger delay to settle down,
1131 * else crb_window returns 0xffffffff 1148 * else crb_window returns 0xffffffff
@@ -1142,25 +1159,25 @@ qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
1142 kfree(buf); 1159 kfree(buf);
1143 1160
1144 /* Resetting the data and instruction cache */ 1161 /* Resetting the data and instruction cache */
1145 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1162 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1146 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1163 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1147 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1164 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1148 1165
1149 /* Clear all protocol processing engines */ 1166 /* Clear all protocol processing engines */
1150 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1167 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1151 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1168 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1152 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1169 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1153 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1170 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1154 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1171 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1155 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1172 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1156 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1173 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1157 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1174 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1158 1175
1159 return 0; 1176 return 0;
1160} 1177}
1161 1178
1162static int 1179static int
1163qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1180qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1164{ 1181{
1165 int i, rval = 0; 1182 int i, rval = 0;
1166 long size = 0; 1183 long size = 0;
@@ -1175,14 +1192,14 @@ qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1175 ha->host_no, __func__, flashaddr, image_start)); 1192 ha->host_no, __func__, flashaddr, image_start));
1176 1193
1177 for (i = 0; i < size; i++) { 1194 for (i = 0; i < size; i++) {
1178 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1195 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1179 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4, 1196 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1180 (int *)&high))) { 1197 (int *)&high))) {
1181 rval = -1; 1198 rval = -1;
1182 goto exit_load_from_flash; 1199 goto exit_load_from_flash;
1183 } 1200 }
1184 data = ((u64)high << 32) | low ; 1201 data = ((u64)high << 32) | low ;
1185 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8); 1202 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1186 if (rval) 1203 if (rval)
1187 goto exit_load_from_flash; 1204 goto exit_load_from_flash;
1188 1205
@@ -1197,20 +1214,20 @@ qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1197 udelay(100); 1214 udelay(100);
1198 1215
1199 read_lock(&ha->hw_lock); 1216 read_lock(&ha->hw_lock);
1200 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1217 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1201 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1218 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1202 read_unlock(&ha->hw_lock); 1219 read_unlock(&ha->hw_lock);
1203 1220
1204exit_load_from_flash: 1221exit_load_from_flash:
1205 return rval; 1222 return rval;
1206} 1223}
1207 1224
1208static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1225static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1209{ 1226{
1210 u32 rst; 1227 u32 rst;
1211 1228
1212 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1229 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1213 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1230 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1214 printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1231 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1215 __func__); 1232 __func__);
1216 return QLA_ERROR; 1233 return QLA_ERROR;
@@ -1223,12 +1240,12 @@ static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1223 * To get around this, QM is brought out of reset. 1240 * To get around this, QM is brought out of reset.
1224 */ 1241 */
1225 1242
1226 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1243 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1227 /* unreset qm */ 1244 /* unreset qm */
1228 rst &= ~(1 << 28); 1245 rst &= ~(1 << 28);
1229 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1246 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1230 1247
1231 if (qla4_8xxx_load_from_flash(ha, image_start)) { 1248 if (qla4_82xx_load_from_flash(ha, image_start)) {
1232 printk("%s: Error trying to load fw from flash!\n", __func__); 1249 printk("%s: Error trying to load fw from flash!\n", __func__);
1233 return QLA_ERROR; 1250 return QLA_ERROR;
1234 } 1251 }
@@ -1237,7 +1254,7 @@ static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1237} 1254}
1238 1255
1239int 1256int
1240qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha, 1257qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1241 u64 off, void *data, int size) 1258 u64 off, void *data, int size)
1242{ 1259{
1243 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1260 int i, j = 0, k, start, end, loop, sz[2], off0[2];
@@ -1249,12 +1266,12 @@ qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1249 * If not MN, go check for MS or invalid. 1266 * If not MN, go check for MS or invalid.
1250 */ 1267 */
1251 1268
1252 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1269 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1253 mem_crb = QLA82XX_CRB_QDR_NET; 1270 mem_crb = QLA82XX_CRB_QDR_NET;
1254 else { 1271 else {
1255 mem_crb = QLA82XX_CRB_DDR_NET; 1272 mem_crb = QLA82XX_CRB_DDR_NET;
1256 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1273 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1257 return qla4_8xxx_pci_mem_read_direct(ha, 1274 return qla4_82xx_pci_mem_read_direct(ha,
1258 off, data, size); 1275 off, data, size);
1259 } 1276 }
1260 1277
@@ -1270,16 +1287,16 @@ qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1270 1287
1271 for (i = 0; i < loop; i++) { 1288 for (i = 0; i < loop; i++) {
1272 temp = off8 + (i << shift_amount); 1289 temp = off8 + (i << shift_amount);
1273 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1290 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1274 temp = 0; 1291 temp = 0;
1275 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1292 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1276 temp = MIU_TA_CTL_ENABLE; 1293 temp = MIU_TA_CTL_ENABLE;
1277 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1294 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1278 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1295 temp = MIU_TA_CTL_START_ENABLE;
1279 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1296 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1280 1297
1281 for (j = 0; j < MAX_CTL_CHECK; j++) { 1298 for (j = 0; j < MAX_CTL_CHECK; j++) {
1282 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1299 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1283 if ((temp & MIU_TA_CTL_BUSY) == 0) 1300 if ((temp & MIU_TA_CTL_BUSY) == 0)
1284 break; 1301 break;
1285 } 1302 }
@@ -1294,7 +1311,7 @@ qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1294 start = off0[i] >> 2; 1311 start = off0[i] >> 2;
1295 end = (off0[i] + sz[i] - 1) >> 2; 1312 end = (off0[i] + sz[i] - 1) >> 2;
1296 for (k = start; k <= end; k++) { 1313 for (k = start; k <= end; k++) {
1297 temp = qla4_8xxx_rd_32(ha, 1314 temp = qla4_82xx_rd_32(ha,
1298 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1315 mem_crb + MIU_TEST_AGT_RDDATA(k));
1299 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1316 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1300 } 1317 }
@@ -1328,7 +1345,7 @@ qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1328} 1345}
1329 1346
1330int 1347int
1331qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, 1348qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1332 u64 off, void *data, int size) 1349 u64 off, void *data, int size)
1333{ 1350{
1334 int i, j, ret = 0, loop, sz[2], off0; 1351 int i, j, ret = 0, loop, sz[2], off0;
@@ -1339,12 +1356,12 @@ qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1339 /* 1356 /*
1340 * If not MN, go check for MS or invalid. 1357 * If not MN, go check for MS or invalid.
1341 */ 1358 */
1342 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1359 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1343 mem_crb = QLA82XX_CRB_QDR_NET; 1360 mem_crb = QLA82XX_CRB_QDR_NET;
1344 else { 1361 else {
1345 mem_crb = QLA82XX_CRB_DDR_NET; 1362 mem_crb = QLA82XX_CRB_DDR_NET;
1346 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1363 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1347 return qla4_8xxx_pci_mem_write_direct(ha, 1364 return qla4_82xx_pci_mem_write_direct(ha,
1348 off, data, size); 1365 off, data, size);
1349 } 1366 }
1350 1367
@@ -1359,7 +1376,7 @@ qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1359 startword = (off & 0xf)/8; 1376 startword = (off & 0xf)/8;
1360 1377
1361 for (i = 0; i < loop; i++) { 1378 for (i = 0; i < loop; i++) {
1362 if (qla4_8xxx_pci_mem_read_2M(ha, off8 + 1379 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1363 (i << shift_amount), &word[i * scale], 8)) 1380 (i << shift_amount), &word[i * scale], 8))
1364 return -1; 1381 return -1;
1365 } 1382 }
@@ -1395,27 +1412,27 @@ qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1395 1412
1396 for (i = 0; i < loop; i++) { 1413 for (i = 0; i < loop; i++) {
1397 temp = off8 + (i << shift_amount); 1414 temp = off8 + (i << shift_amount);
1398 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1415 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399 temp = 0; 1416 temp = 0;
1400 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1417 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401 temp = word[i * scale] & 0xffffffff; 1418 temp = word[i * scale] & 0xffffffff;
1402 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1419 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403 temp = (word[i * scale] >> 32) & 0xffffffff; 1420 temp = (word[i * scale] >> 32) & 0xffffffff;
1404 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1421 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405 temp = word[i*scale + 1] & 0xffffffff; 1422 temp = word[i*scale + 1] & 0xffffffff;
1406 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1423 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1407 temp); 1424 temp);
1408 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1425 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1409 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1426 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1410 temp); 1427 temp);
1411 1428
1412 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1429 temp = MIU_TA_CTL_WRITE_ENABLE;
1413 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1430 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1414 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1431 temp = MIU_TA_CTL_WRITE_START;
1415 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1432 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1416 1433
1417 for (j = 0; j < MAX_CTL_CHECK; j++) { 1434 for (j = 0; j < MAX_CTL_CHECK; j++) {
1418 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1435 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419 if ((temp & MIU_TA_CTL_BUSY) == 0) 1436 if ((temp & MIU_TA_CTL_BUSY) == 0)
1420 break; 1437 break;
1421 } 1438 }
@@ -1433,14 +1450,14 @@ qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1433 return ret; 1450 return ret;
1434} 1451}
1435 1452
1436static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1453static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1437{ 1454{
1438 u32 val = 0; 1455 u32 val = 0;
1439 int retries = 60; 1456 int retries = 60;
1440 1457
1441 if (!pegtune_val) { 1458 if (!pegtune_val) {
1442 do { 1459 do {
1443 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE); 1460 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1444 if ((val == PHAN_INITIALIZE_COMPLETE) || 1461 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1445 (val == PHAN_INITIALIZE_ACK)) 1462 (val == PHAN_INITIALIZE_ACK))
1446 return 0; 1463 return 0;
@@ -1450,7 +1467,7 @@ static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1450 } while (--retries); 1467 } while (--retries);
1451 1468
1452 if (!retries) { 1469 if (!retries) {
1453 pegtune_val = qla4_8xxx_rd_32(ha, 1470 pegtune_val = qla4_82xx_rd_32(ha,
1454 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1471 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1455 printk(KERN_WARNING "%s: init failed, " 1472 printk(KERN_WARNING "%s: init failed, "
1456 "pegtune_val = %x\n", __func__, pegtune_val); 1473 "pegtune_val = %x\n", __func__, pegtune_val);
@@ -1460,21 +1477,21 @@ static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1460 return 0; 1477 return 0;
1461} 1478}
1462 1479
1463static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha) 1480static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1464{ 1481{
1465 uint32_t state = 0; 1482 uint32_t state = 0;
1466 int loops = 0; 1483 int loops = 0;
1467 1484
1468 /* Window 1 call */ 1485 /* Window 1 call */
1469 read_lock(&ha->hw_lock); 1486 read_lock(&ha->hw_lock);
1470 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1487 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1471 read_unlock(&ha->hw_lock); 1488 read_unlock(&ha->hw_lock);
1472 1489
1473 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1490 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1474 udelay(100); 1491 udelay(100);
1475 /* Window 1 call */ 1492 /* Window 1 call */
1476 read_lock(&ha->hw_lock); 1493 read_lock(&ha->hw_lock);
1477 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1494 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1478 read_unlock(&ha->hw_lock); 1495 read_unlock(&ha->hw_lock);
1479 1496
1480 loops++; 1497 loops++;
@@ -1494,11 +1511,21 @@ qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1494{ 1511{
1495 uint32_t drv_active; 1512 uint32_t drv_active;
1496 1513
1497 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1514 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1498 drv_active |= (1 << (ha->func_num * 4)); 1515
1516 /*
1517 * For ISP8324, drv_active register has 1 bit per function,
1518 * shift 1 by func_num to set a bit for the function.
1519 * For ISP8022, drv_active has 4 bits per function
1520 */
1521 if (is_qla8032(ha))
1522 drv_active |= (1 << ha->func_num);
1523 else
1524 drv_active |= (1 << (ha->func_num * 4));
1525
1499 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1526 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1500 __func__, ha->host_no, drv_active); 1527 __func__, ha->host_no, drv_active);
1501 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1528 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1502} 1529}
1503 1530
1504void 1531void
@@ -1506,50 +1533,87 @@ qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1506{ 1533{
1507 uint32_t drv_active; 1534 uint32_t drv_active;
1508 1535
1509 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1536 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1510 drv_active &= ~(1 << (ha->func_num * 4)); 1537
1538 /*
1539 * For ISP8324, drv_active register has 1 bit per function,
1540 * shift 1 by func_num to set a bit for the function.
1541 * For ISP8022, drv_active has 4 bits per function
1542 */
1543 if (is_qla8032(ha))
1544 drv_active &= ~(1 << (ha->func_num));
1545 else
1546 drv_active &= ~(1 << (ha->func_num * 4));
1547
1511 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1548 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1512 __func__, ha->host_no, drv_active); 1549 __func__, ha->host_no, drv_active);
1513 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1550 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1514} 1551}
1515 1552
1516static inline int 1553inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1517qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1518{ 1554{
1519 uint32_t drv_state, drv_active; 1555 uint32_t drv_state, drv_active;
1520 int rval; 1556 int rval;
1521 1557
1522 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1558 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1523 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1559 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1524 rval = drv_state & (1 << (ha->func_num * 4)); 1560
1561 /*
1562 * For ISP8324, drv_active register has 1 bit per function,
1563 * shift 1 by func_num to set a bit for the function.
1564 * For ISP8022, drv_active has 4 bits per function
1565 */
1566 if (is_qla8032(ha))
1567 rval = drv_state & (1 << ha->func_num);
1568 else
1569 rval = drv_state & (1 << (ha->func_num * 4));
1570
1525 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 1571 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1526 rval = 1; 1572 rval = 1;
1527 1573
1528 return rval; 1574 return rval;
1529} 1575}
1530 1576
1531static inline void 1577void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1532qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1533{ 1578{
1534 uint32_t drv_state; 1579 uint32_t drv_state;
1535 1580
1536 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1581 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1537 drv_state |= (1 << (ha->func_num * 4)); 1582
1583 /*
1584 * For ISP8324, drv_active register has 1 bit per function,
1585 * shift 1 by func_num to set a bit for the function.
1586 * For ISP8022, drv_active has 4 bits per function
1587 */
1588 if (is_qla8032(ha))
1589 drv_state |= (1 << ha->func_num);
1590 else
1591 drv_state |= (1 << (ha->func_num * 4));
1592
1538 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1593 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1539 __func__, ha->host_no, drv_state); 1594 __func__, ha->host_no, drv_state);
1540 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1595 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1541} 1596}
1542 1597
1543static inline void 1598void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1544qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1545{ 1599{
1546 uint32_t drv_state; 1600 uint32_t drv_state;
1547 1601
1548 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1602 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1549 drv_state &= ~(1 << (ha->func_num * 4)); 1603
1604 /*
1605 * For ISP8324, drv_active register has 1 bit per function,
1606 * shift 1 by func_num to set a bit for the function.
1607 * For ISP8022, drv_active has 4 bits per function
1608 */
1609 if (is_qla8032(ha))
1610 drv_state &= ~(1 << ha->func_num);
1611 else
1612 drv_state &= ~(1 << (ha->func_num * 4));
1613
1550 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1614 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1551 __func__, ha->host_no, drv_state); 1615 __func__, ha->host_no, drv_state);
1552 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1616 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1553} 1617}
1554 1618
1555static inline void 1619static inline void
@@ -1557,33 +1621,43 @@ qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1557{ 1621{
1558 uint32_t qsnt_state; 1622 uint32_t qsnt_state;
1559 1623
1560 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1624 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1561 qsnt_state |= (2 << (ha->func_num * 4)); 1625
1562 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1626 /*
1627 * For ISP8324, drv_active register has 1 bit per function,
1628 * shift 1 by func_num to set a bit for the function.
1629 * For ISP8022, drv_active has 4 bits per function.
1630 */
1631 if (is_qla8032(ha))
1632 qsnt_state |= (1 << ha->func_num);
1633 else
1634 qsnt_state |= (2 << (ha->func_num * 4));
1635
1636 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1563} 1637}
1564 1638
1565 1639
1566static int 1640static int
1567qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1641qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1568{ 1642{
1569 uint16_t lnk; 1643 uint16_t lnk;
1570 1644
1571 /* scrub dma mask expansion register */ 1645 /* scrub dma mask expansion register */
1572 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1646 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1573 1647
1574 /* Overwrite stale initialization register values */ 1648 /* Overwrite stale initialization register values */
1575 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1649 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1576 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1650 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1577 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1651 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1578 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1652 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1579 1653
1580 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) { 1654 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1581 printk("%s: Error trying to start fw!\n", __func__); 1655 printk("%s: Error trying to start fw!\n", __func__);
1582 return QLA_ERROR; 1656 return QLA_ERROR;
1583 } 1657 }
1584 1658
1585 /* Handshake with the card before we register the devices. */ 1659 /* Handshake with the card before we register the devices. */
1586 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1660 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1587 printk("%s: Error during card handshake!\n", __func__); 1661 printk("%s: Error during card handshake!\n", __func__);
1588 return QLA_ERROR; 1662 return QLA_ERROR;
1589 } 1663 }
@@ -1593,11 +1667,10 @@ qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1593 ha->link_width = (lnk >> 4) & 0x3f; 1667 ha->link_width = (lnk >> 4) & 0x3f;
1594 1668
1595 /* Synchronize with Receive peg */ 1669 /* Synchronize with Receive peg */
1596 return qla4_8xxx_rcvpeg_ready(ha); 1670 return qla4_82xx_rcvpeg_ready(ha);
1597} 1671}
1598 1672
1599static int 1673int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1600qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1601{ 1674{
1602 int rval = QLA_ERROR; 1675 int rval = QLA_ERROR;
1603 1676
@@ -1615,7 +1688,7 @@ qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1615 1688
1616 ql4_printk(KERN_INFO, ha, 1689 ql4_printk(KERN_INFO, ha,
1617 "FW: Attempting to load firmware from flash...\n"); 1690 "FW: Attempting to load firmware from flash...\n");
1618 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw); 1691 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1619 1692
1620 if (rval != QLA_SUCCESS) { 1693 if (rval != QLA_SUCCESS) {
1621 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1694 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
@@ -1626,9 +1699,9 @@ qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1626 return rval; 1699 return rval;
1627} 1700}
1628 1701
1629static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha) 1702void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1630{ 1703{
1631 if (qla4_8xxx_rom_lock(ha)) { 1704 if (qla4_82xx_rom_lock(ha)) {
1632 /* Someone else is holding the lock. */ 1705 /* Someone else is holding the lock. */
1633 dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1706 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1634 } 1707 }
@@ -1638,25 +1711,25 @@ static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1638 * else died while holding it. 1711 * else died while holding it.
1639 * In either case, unlock. 1712 * In either case, unlock.
1640 */ 1713 */
1641 qla4_8xxx_rom_unlock(ha); 1714 qla4_82xx_rom_unlock(ha);
1642} 1715}
1643 1716
1644static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 1717static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1645 struct qla82xx_minidump_entry_hdr *entry_hdr, 1718 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1646 uint32_t **d_ptr) 1719 uint32_t **d_ptr)
1647{ 1720{
1648 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 1721 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1649 struct qla82xx_minidump_entry_crb *crb_hdr; 1722 struct qla8xxx_minidump_entry_crb *crb_hdr;
1650 uint32_t *data_ptr = *d_ptr; 1723 uint32_t *data_ptr = *d_ptr;
1651 1724
1652 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1725 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1653 crb_hdr = (struct qla82xx_minidump_entry_crb *)entry_hdr; 1726 crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1654 r_addr = crb_hdr->addr; 1727 r_addr = crb_hdr->addr;
1655 r_stride = crb_hdr->crb_strd.addr_stride; 1728 r_stride = crb_hdr->crb_strd.addr_stride;
1656 loop_cnt = crb_hdr->op_count; 1729 loop_cnt = crb_hdr->op_count;
1657 1730
1658 for (i = 0; i < loop_cnt; i++) { 1731 for (i = 0; i < loop_cnt; i++) {
1659 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1732 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1660 *data_ptr++ = cpu_to_le32(r_addr); 1733 *data_ptr++ = cpu_to_le32(r_addr);
1661 *data_ptr++ = cpu_to_le32(r_value); 1734 *data_ptr++ = cpu_to_le32(r_value);
1662 r_addr += r_stride; 1735 r_addr += r_stride;
@@ -1665,19 +1738,19 @@ static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1665} 1738}
1666 1739
1667static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 1740static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1668 struct qla82xx_minidump_entry_hdr *entry_hdr, 1741 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1669 uint32_t **d_ptr) 1742 uint32_t **d_ptr)
1670{ 1743{
1671 uint32_t addr, r_addr, c_addr, t_r_addr; 1744 uint32_t addr, r_addr, c_addr, t_r_addr;
1672 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1745 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1673 unsigned long p_wait, w_time, p_mask; 1746 unsigned long p_wait, w_time, p_mask;
1674 uint32_t c_value_w, c_value_r; 1747 uint32_t c_value_w, c_value_r;
1675 struct qla82xx_minidump_entry_cache *cache_hdr; 1748 struct qla8xxx_minidump_entry_cache *cache_hdr;
1676 int rval = QLA_ERROR; 1749 int rval = QLA_ERROR;
1677 uint32_t *data_ptr = *d_ptr; 1750 uint32_t *data_ptr = *d_ptr;
1678 1751
1679 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1752 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1680 cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr; 1753 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
1681 1754
1682 loop_count = cache_hdr->op_count; 1755 loop_count = cache_hdr->op_count;
1683 r_addr = cache_hdr->read_addr; 1756 r_addr = cache_hdr->read_addr;
@@ -1691,16 +1764,16 @@ static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1691 p_mask = cache_hdr->cache_ctrl.poll_mask; 1764 p_mask = cache_hdr->cache_ctrl.poll_mask;
1692 1765
1693 for (i = 0; i < loop_count; i++) { 1766 for (i = 0; i < loop_count; i++) {
1694 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1767 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1695 1768
1696 if (c_value_w) 1769 if (c_value_w)
1697 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1770 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1698 1771
1699 if (p_mask) { 1772 if (p_mask) {
1700 w_time = jiffies + p_wait; 1773 w_time = jiffies + p_wait;
1701 do { 1774 do {
1702 c_value_r = qla4_8xxx_md_rw_32(ha, c_addr, 1775 ha->isp_ops->rd_reg_indirect(ha, c_addr,
1703 0, 0); 1776 &c_value_r);
1704 if ((c_value_r & p_mask) == 0) { 1777 if ((c_value_r & p_mask) == 0) {
1705 break; 1778 break;
1706 } else if (time_after_eq(jiffies, w_time)) { 1779 } else if (time_after_eq(jiffies, w_time)) {
@@ -1712,7 +1785,7 @@ static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1712 1785
1713 addr = r_addr; 1786 addr = r_addr;
1714 for (k = 0; k < r_cnt; k++) { 1787 for (k = 0; k < r_cnt; k++) {
1715 r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1788 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1716 *data_ptr++ = cpu_to_le32(r_value); 1789 *data_ptr++ = cpu_to_le32(r_value);
1717 addr += cache_hdr->read_ctrl.read_addr_stride; 1790 addr += cache_hdr->read_ctrl.read_addr_stride;
1718 } 1791 }
@@ -1724,9 +1797,9 @@ static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1724} 1797}
1725 1798
1726static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 1799static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1727 struct qla82xx_minidump_entry_hdr *entry_hdr) 1800 struct qla8xxx_minidump_entry_hdr *entry_hdr)
1728{ 1801{
1729 struct qla82xx_minidump_entry_crb *crb_entry; 1802 struct qla8xxx_minidump_entry_crb *crb_entry;
1730 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 1803 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
1731 uint32_t crb_addr; 1804 uint32_t crb_addr;
1732 unsigned long wtime; 1805 unsigned long wtime;
@@ -1736,58 +1809,59 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1736 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1809 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1737 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 1810 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1738 ha->fw_dump_tmplt_hdr; 1811 ha->fw_dump_tmplt_hdr;
1739 crb_entry = (struct qla82xx_minidump_entry_crb *)entry_hdr; 1812 crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1740 1813
1741 crb_addr = crb_entry->addr; 1814 crb_addr = crb_entry->addr;
1742 for (i = 0; i < crb_entry->op_count; i++) { 1815 for (i = 0; i < crb_entry->op_count; i++) {
1743 opcode = crb_entry->crb_ctrl.opcode; 1816 opcode = crb_entry->crb_ctrl.opcode;
1744 if (opcode & QLA82XX_DBG_OPCODE_WR) { 1817 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
1745 qla4_8xxx_md_rw_32(ha, crb_addr, 1818 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
1746 crb_entry->value_1, 1); 1819 crb_entry->value_1);
1747 opcode &= ~QLA82XX_DBG_OPCODE_WR; 1820 opcode &= ~QLA8XXX_DBG_OPCODE_WR;
1748 } 1821 }
1749 if (opcode & QLA82XX_DBG_OPCODE_RW) { 1822 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
1750 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1823 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1751 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1824 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1752 opcode &= ~QLA82XX_DBG_OPCODE_RW; 1825 opcode &= ~QLA8XXX_DBG_OPCODE_RW;
1753 } 1826 }
1754 if (opcode & QLA82XX_DBG_OPCODE_AND) { 1827 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
1755 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1828 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1756 read_value &= crb_entry->value_2; 1829 read_value &= crb_entry->value_2;
1757 opcode &= ~QLA82XX_DBG_OPCODE_AND; 1830 opcode &= ~QLA8XXX_DBG_OPCODE_AND;
1758 if (opcode & QLA82XX_DBG_OPCODE_OR) { 1831 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
1759 read_value |= crb_entry->value_3; 1832 read_value |= crb_entry->value_3;
1760 opcode &= ~QLA82XX_DBG_OPCODE_OR; 1833 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
1761 } 1834 }
1762 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1835 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1763 } 1836 }
1764 if (opcode & QLA82XX_DBG_OPCODE_OR) { 1837 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
1765 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1838 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1766 read_value |= crb_entry->value_3; 1839 read_value |= crb_entry->value_3;
1767 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1840 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1768 opcode &= ~QLA82XX_DBG_OPCODE_OR; 1841 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
1769 } 1842 }
1770 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 1843 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
1771 poll_time = crb_entry->crb_strd.poll_timeout; 1844 poll_time = crb_entry->crb_strd.poll_timeout;
1772 wtime = jiffies + poll_time; 1845 wtime = jiffies + poll_time;
1773 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1846 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1774 1847
1775 do { 1848 do {
1776 if ((read_value & crb_entry->value_2) == 1849 if ((read_value & crb_entry->value_2) ==
1777 crb_entry->value_1) 1850 crb_entry->value_1) {
1778 break; 1851 break;
1779 else if (time_after_eq(jiffies, wtime)) { 1852 } else if (time_after_eq(jiffies, wtime)) {
1780 /* capturing dump failed */ 1853 /* capturing dump failed */
1781 rval = QLA_ERROR; 1854 rval = QLA_ERROR;
1782 break; 1855 break;
1783 } else 1856 } else {
1784 read_value = qla4_8xxx_md_rw_32(ha, 1857 ha->isp_ops->rd_reg_indirect(ha,
1785 crb_addr, 0, 0); 1858 crb_addr, &read_value);
1859 }
1786 } while (1); 1860 } while (1);
1787 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 1861 opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
1788 } 1862 }
1789 1863
1790 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 1864 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
1791 if (crb_entry->crb_strd.state_index_a) { 1865 if (crb_entry->crb_strd.state_index_a) {
1792 index = crb_entry->crb_strd.state_index_a; 1866 index = crb_entry->crb_strd.state_index_a;
1793 addr = tmplt_hdr->saved_state_array[index]; 1867 addr = tmplt_hdr->saved_state_array[index];
@@ -1795,13 +1869,13 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1795 addr = crb_addr; 1869 addr = crb_addr;
1796 } 1870 }
1797 1871
1798 read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1872 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
1799 index = crb_entry->crb_ctrl.state_index_v; 1873 index = crb_entry->crb_ctrl.state_index_v;
1800 tmplt_hdr->saved_state_array[index] = read_value; 1874 tmplt_hdr->saved_state_array[index] = read_value;
1801 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 1875 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
1802 } 1876 }
1803 1877
1804 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 1878 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
1805 if (crb_entry->crb_strd.state_index_a) { 1879 if (crb_entry->crb_strd.state_index_a) {
1806 index = crb_entry->crb_strd.state_index_a; 1880 index = crb_entry->crb_strd.state_index_a;
1807 addr = tmplt_hdr->saved_state_array[index]; 1881 addr = tmplt_hdr->saved_state_array[index];
@@ -1817,11 +1891,11 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1817 read_value = crb_entry->value_1; 1891 read_value = crb_entry->value_1;
1818 } 1892 }
1819 1893
1820 qla4_8xxx_md_rw_32(ha, addr, read_value, 1); 1894 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
1821 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 1895 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
1822 } 1896 }
1823 1897
1824 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 1898 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
1825 index = crb_entry->crb_ctrl.state_index_v; 1899 index = crb_entry->crb_ctrl.state_index_v;
1826 read_value = tmplt_hdr->saved_state_array[index]; 1900 read_value = tmplt_hdr->saved_state_array[index];
1827 read_value <<= crb_entry->crb_ctrl.shl; 1901 read_value <<= crb_entry->crb_ctrl.shl;
@@ -1831,7 +1905,7 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1831 read_value |= crb_entry->value_3; 1905 read_value |= crb_entry->value_3;
1832 read_value += crb_entry->value_1; 1906 read_value += crb_entry->value_1;
1833 tmplt_hdr->saved_state_array[index] = read_value; 1907 tmplt_hdr->saved_state_array[index] = read_value;
1834 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 1908 opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
1835 } 1909 }
1836 crb_addr += crb_entry->crb_strd.addr_stride; 1910 crb_addr += crb_entry->crb_strd.addr_stride;
1837 } 1911 }
@@ -1840,15 +1914,15 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1840} 1914}
1841 1915
1842static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 1916static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
1843 struct qla82xx_minidump_entry_hdr *entry_hdr, 1917 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1844 uint32_t **d_ptr) 1918 uint32_t **d_ptr)
1845{ 1919{
1846 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 1920 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1847 struct qla82xx_minidump_entry_rdocm *ocm_hdr; 1921 struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
1848 uint32_t *data_ptr = *d_ptr; 1922 uint32_t *data_ptr = *d_ptr;
1849 1923
1850 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1924 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1851 ocm_hdr = (struct qla82xx_minidump_entry_rdocm *)entry_hdr; 1925 ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
1852 r_addr = ocm_hdr->read_addr; 1926 r_addr = ocm_hdr->read_addr;
1853 r_stride = ocm_hdr->read_addr_stride; 1927 r_stride = ocm_hdr->read_addr_stride;
1854 loop_cnt = ocm_hdr->op_count; 1928 loop_cnt = ocm_hdr->op_count;
@@ -1863,20 +1937,20 @@ static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
1863 r_addr += r_stride; 1937 r_addr += r_stride;
1864 } 1938 }
1865 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 1939 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
1866 __func__, (loop_cnt * sizeof(uint32_t)))); 1940 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
1867 *d_ptr = data_ptr; 1941 *d_ptr = data_ptr;
1868} 1942}
1869 1943
1870static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 1944static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1871 struct qla82xx_minidump_entry_hdr *entry_hdr, 1945 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1872 uint32_t **d_ptr) 1946 uint32_t **d_ptr)
1873{ 1947{
1874 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 1948 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
1875 struct qla82xx_minidump_entry_mux *mux_hdr; 1949 struct qla8xxx_minidump_entry_mux *mux_hdr;
1876 uint32_t *data_ptr = *d_ptr; 1950 uint32_t *data_ptr = *d_ptr;
1877 1951
1878 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1952 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1879 mux_hdr = (struct qla82xx_minidump_entry_mux *)entry_hdr; 1953 mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
1880 r_addr = mux_hdr->read_addr; 1954 r_addr = mux_hdr->read_addr;
1881 s_addr = mux_hdr->select_addr; 1955 s_addr = mux_hdr->select_addr;
1882 s_stride = mux_hdr->select_value_stride; 1956 s_stride = mux_hdr->select_value_stride;
@@ -1884,8 +1958,8 @@ static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1884 loop_cnt = mux_hdr->op_count; 1958 loop_cnt = mux_hdr->op_count;
1885 1959
1886 for (i = 0; i < loop_cnt; i++) { 1960 for (i = 0; i < loop_cnt; i++) {
1887 qla4_8xxx_md_rw_32(ha, s_addr, s_value, 1); 1961 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
1888 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1962 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1889 *data_ptr++ = cpu_to_le32(s_value); 1963 *data_ptr++ = cpu_to_le32(s_value);
1890 *data_ptr++ = cpu_to_le32(r_value); 1964 *data_ptr++ = cpu_to_le32(r_value);
1891 s_value += s_stride; 1965 s_value += s_stride;
@@ -1894,16 +1968,16 @@ static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1894} 1968}
1895 1969
1896static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 1970static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1897 struct qla82xx_minidump_entry_hdr *entry_hdr, 1971 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1898 uint32_t **d_ptr) 1972 uint32_t **d_ptr)
1899{ 1973{
1900 uint32_t addr, r_addr, c_addr, t_r_addr; 1974 uint32_t addr, r_addr, c_addr, t_r_addr;
1901 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1975 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1902 uint32_t c_value_w; 1976 uint32_t c_value_w;
1903 struct qla82xx_minidump_entry_cache *cache_hdr; 1977 struct qla8xxx_minidump_entry_cache *cache_hdr;
1904 uint32_t *data_ptr = *d_ptr; 1978 uint32_t *data_ptr = *d_ptr;
1905 1979
1906 cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr; 1980 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
1907 loop_count = cache_hdr->op_count; 1981 loop_count = cache_hdr->op_count;
1908 r_addr = cache_hdr->read_addr; 1982 r_addr = cache_hdr->read_addr;
1909 c_addr = cache_hdr->control_addr; 1983 c_addr = cache_hdr->control_addr;
@@ -1914,11 +1988,11 @@ static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1914 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1988 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1915 1989
1916 for (i = 0; i < loop_count; i++) { 1990 for (i = 0; i < loop_count; i++) {
1917 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1991 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1918 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1992 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1919 addr = r_addr; 1993 addr = r_addr;
1920 for (k = 0; k < r_cnt; k++) { 1994 for (k = 0; k < r_cnt; k++) {
1921 r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1995 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1922 *data_ptr++ = cpu_to_le32(r_value); 1996 *data_ptr++ = cpu_to_le32(r_value);
1923 addr += cache_hdr->read_ctrl.read_addr_stride; 1997 addr += cache_hdr->read_ctrl.read_addr_stride;
1924 } 1998 }
@@ -1928,27 +2002,27 @@ static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1928} 2002}
1929 2003
1930static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 2004static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
1931 struct qla82xx_minidump_entry_hdr *entry_hdr, 2005 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1932 uint32_t **d_ptr) 2006 uint32_t **d_ptr)
1933{ 2007{
1934 uint32_t s_addr, r_addr; 2008 uint32_t s_addr, r_addr;
1935 uint32_t r_stride, r_value, r_cnt, qid = 0; 2009 uint32_t r_stride, r_value, r_cnt, qid = 0;
1936 uint32_t i, k, loop_cnt; 2010 uint32_t i, k, loop_cnt;
1937 struct qla82xx_minidump_entry_queue *q_hdr; 2011 struct qla8xxx_minidump_entry_queue *q_hdr;
1938 uint32_t *data_ptr = *d_ptr; 2012 uint32_t *data_ptr = *d_ptr;
1939 2013
1940 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2014 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1941 q_hdr = (struct qla82xx_minidump_entry_queue *)entry_hdr; 2015 q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
1942 s_addr = q_hdr->select_addr; 2016 s_addr = q_hdr->select_addr;
1943 r_cnt = q_hdr->rd_strd.read_addr_cnt; 2017 r_cnt = q_hdr->rd_strd.read_addr_cnt;
1944 r_stride = q_hdr->rd_strd.read_addr_stride; 2018 r_stride = q_hdr->rd_strd.read_addr_stride;
1945 loop_cnt = q_hdr->op_count; 2019 loop_cnt = q_hdr->op_count;
1946 2020
1947 for (i = 0; i < loop_cnt; i++) { 2021 for (i = 0; i < loop_cnt; i++) {
1948 qla4_8xxx_md_rw_32(ha, s_addr, qid, 1); 2022 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
1949 r_addr = q_hdr->read_addr; 2023 r_addr = q_hdr->read_addr;
1950 for (k = 0; k < r_cnt; k++) { 2024 for (k = 0; k < r_cnt; k++) {
1951 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 2025 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1952 *data_ptr++ = cpu_to_le32(r_value); 2026 *data_ptr++ = cpu_to_le32(r_value);
1953 r_addr += r_stride; 2027 r_addr += r_stride;
1954 } 2028 }
@@ -1960,17 +2034,17 @@ static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
1960#define MD_DIRECT_ROM_WINDOW 0x42110030 2034#define MD_DIRECT_ROM_WINDOW 0x42110030
1961#define MD_DIRECT_ROM_READ_BASE 0x42150000 2035#define MD_DIRECT_ROM_READ_BASE 0x42150000
1962 2036
1963static void qla4_8xxx_minidump_process_rdrom(struct scsi_qla_host *ha, 2037static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
1964 struct qla82xx_minidump_entry_hdr *entry_hdr, 2038 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1965 uint32_t **d_ptr) 2039 uint32_t **d_ptr)
1966{ 2040{
1967 uint32_t r_addr, r_value; 2041 uint32_t r_addr, r_value;
1968 uint32_t i, loop_cnt; 2042 uint32_t i, loop_cnt;
1969 struct qla82xx_minidump_entry_rdrom *rom_hdr; 2043 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
1970 uint32_t *data_ptr = *d_ptr; 2044 uint32_t *data_ptr = *d_ptr;
1971 2045
1972 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2046 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1973 rom_hdr = (struct qla82xx_minidump_entry_rdrom *)entry_hdr; 2047 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
1974 r_addr = rom_hdr->read_addr; 2048 r_addr = rom_hdr->read_addr;
1975 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 2049 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
1976 2050
@@ -1979,11 +2053,11 @@ static void qla4_8xxx_minidump_process_rdrom(struct scsi_qla_host *ha,
1979 __func__, r_addr, loop_cnt)); 2053 __func__, r_addr, loop_cnt));
1980 2054
1981 for (i = 0; i < loop_cnt; i++) { 2055 for (i = 0; i < loop_cnt; i++) {
1982 qla4_8xxx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 2056 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
1983 (r_addr & 0xFFFF0000), 1); 2057 (r_addr & 0xFFFF0000));
1984 r_value = qla4_8xxx_md_rw_32(ha, 2058 ha->isp_ops->rd_reg_indirect(ha,
1985 MD_DIRECT_ROM_READ_BASE + 2059 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
1986 (r_addr & 0x0000FFFF), 0, 0); 2060 &r_value);
1987 *data_ptr++ = cpu_to_le32(r_value); 2061 *data_ptr++ = cpu_to_le32(r_value);
1988 r_addr += sizeof(uint32_t); 2062 r_addr += sizeof(uint32_t);
1989 } 2063 }
@@ -1995,17 +2069,17 @@ static void qla4_8xxx_minidump_process_rdrom(struct scsi_qla_host *ha,
1995#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 2069#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1996 2070
1997static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 2071static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
1998 struct qla82xx_minidump_entry_hdr *entry_hdr, 2072 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1999 uint32_t **d_ptr) 2073 uint32_t **d_ptr)
2000{ 2074{
2001 uint32_t r_addr, r_value, r_data; 2075 uint32_t r_addr, r_value, r_data;
2002 uint32_t i, j, loop_cnt; 2076 uint32_t i, j, loop_cnt;
2003 struct qla82xx_minidump_entry_rdmem *m_hdr; 2077 struct qla8xxx_minidump_entry_rdmem *m_hdr;
2004 unsigned long flags; 2078 unsigned long flags;
2005 uint32_t *data_ptr = *d_ptr; 2079 uint32_t *data_ptr = *d_ptr;
2006 2080
2007 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2081 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2008 m_hdr = (struct qla82xx_minidump_entry_rdmem *)entry_hdr; 2082 m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
2009 r_addr = m_hdr->read_addr; 2083 r_addr = m_hdr->read_addr;
2010 loop_cnt = m_hdr->read_data_size/16; 2084 loop_cnt = m_hdr->read_data_size/16;
2011 2085
@@ -2033,17 +2107,19 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2033 2107
2034 write_lock_irqsave(&ha->hw_lock, flags); 2108 write_lock_irqsave(&ha->hw_lock, flags);
2035 for (i = 0; i < loop_cnt; i++) { 2109 for (i = 0; i < loop_cnt; i++) {
2036 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 2110 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2111 r_addr);
2037 r_value = 0; 2112 r_value = 0;
2038 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 2113 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2114 r_value);
2039 r_value = MIU_TA_CTL_ENABLE; 2115 r_value = MIU_TA_CTL_ENABLE;
2040 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2116 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2041 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 2117 r_value = MIU_TA_CTL_START_ENABLE;
2042 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2118 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2043 2119
2044 for (j = 0; j < MAX_CTL_CHECK; j++) { 2120 for (j = 0; j < MAX_CTL_CHECK; j++) {
2045 r_value = qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, 2121 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2046 0, 0); 2122 &r_value);
2047 if ((r_value & MIU_TA_CTL_BUSY) == 0) 2123 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2048 break; 2124 break;
2049 } 2125 }
@@ -2057,9 +2133,9 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2057 } 2133 }
2058 2134
2059 for (j = 0; j < 4; j++) { 2135 for (j = 0; j < 4; j++) {
2060 r_data = qla4_8xxx_md_rw_32(ha, 2136 ha->isp_ops->rd_reg_indirect(ha,
2061 MD_MIU_TEST_AGT_RDDATA[j], 2137 MD_MIU_TEST_AGT_RDDATA[j],
2062 0, 0); 2138 &r_data);
2063 *data_ptr++ = cpu_to_le32(r_data); 2139 *data_ptr++ = cpu_to_le32(r_data);
2064 } 2140 }
2065 2141
@@ -2074,25 +2150,215 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2074 return QLA_SUCCESS; 2150 return QLA_SUCCESS;
2075} 2151}
2076 2152
2077static void ql4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 2153static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2078 struct qla82xx_minidump_entry_hdr *entry_hdr, 2154 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2079 int index) 2155 int index)
2080{ 2156{
2081 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 2157 entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
2082 DEBUG2(ql4_printk(KERN_INFO, ha, 2158 DEBUG2(ql4_printk(KERN_INFO, ha,
2083 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2159 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2084 ha->host_no, index, entry_hdr->entry_type, 2160 ha->host_no, index, entry_hdr->entry_type,
2085 entry_hdr->d_ctrl.entry_capture_mask)); 2161 entry_hdr->d_ctrl.entry_capture_mask));
2086} 2162}
2087 2163
2164/* ISP83xx functions to process new minidump entries... */
2165static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2166 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2167 uint32_t **d_ptr)
2168{
2169 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2170 uint16_t s_stride, i;
2171 uint32_t *data_ptr = *d_ptr;
2172 uint32_t rval = QLA_SUCCESS;
2173 struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2174
2175 pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2176 s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2177 r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2178 s_value = le32_to_cpu(pollrd_hdr->select_value);
2179 s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2180
2181 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2182 poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2183
2184 for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2185 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2186 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2187 while (1) {
2188 ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2189
2190 if ((r_value & poll_mask) != 0) {
2191 break;
2192 } else {
2193 msleep(1);
2194 if (--poll_wait == 0) {
2195 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2196 __func__);
2197 rval = QLA_ERROR;
2198 goto exit_process_pollrd;
2199 }
2200 }
2201 }
2202 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2203 *data_ptr++ = cpu_to_le32(s_value);
2204 *data_ptr++ = cpu_to_le32(r_value);
2205 s_value += s_stride;
2206 }
2207
2208 *d_ptr = data_ptr;
2209
2210exit_process_pollrd:
2211 return rval;
2212}
2213
2214static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2215 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2216 uint32_t **d_ptr)
2217{
2218 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2219 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2220 struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2221 uint32_t *data_ptr = *d_ptr;
2222
2223 rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2224 sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2225 sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2226 sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2227 sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2228 sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2229 read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2230
2231 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2232 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2233 t_sel_val = sel_val1 & sel_val_mask;
2234 *data_ptr++ = cpu_to_le32(t_sel_val);
2235
2236 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2237 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2238
2239 *data_ptr++ = cpu_to_le32(data);
2240
2241 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2242 t_sel_val = sel_val2 & sel_val_mask;
2243 *data_ptr++ = cpu_to_le32(t_sel_val);
2244
2245 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2246 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2247
2248 *data_ptr++ = cpu_to_le32(data);
2249
2250 sel_val1 += rdmux2_hdr->select_value_stride;
2251 sel_val2 += rdmux2_hdr->select_value_stride;
2252 }
2253
2254 *d_ptr = data_ptr;
2255}
2256
2257static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2258 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2259 uint32_t **d_ptr)
2260{
2261 uint32_t poll_wait, poll_mask, r_value, data;
2262 uint32_t addr_1, addr_2, value_1, value_2;
2263 uint32_t *data_ptr = *d_ptr;
2264 uint32_t rval = QLA_SUCCESS;
2265 struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2266
2267 poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2268 addr_1 = le32_to_cpu(poll_hdr->addr_1);
2269 addr_2 = le32_to_cpu(poll_hdr->addr_2);
2270 value_1 = le32_to_cpu(poll_hdr->value_1);
2271 value_2 = le32_to_cpu(poll_hdr->value_2);
2272 poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2273
2274 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2275
2276 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2277 while (1) {
2278 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2279
2280 if ((r_value & poll_mask) != 0) {
2281 break;
2282 } else {
2283 msleep(1);
2284 if (--poll_wait == 0) {
2285 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2286 __func__);
2287 rval = QLA_ERROR;
2288 goto exit_process_pollrdmwr;
2289 }
2290 }
2291 }
2292
2293 ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2294 data &= le32_to_cpu(poll_hdr->modify_mask);
2295 ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2296 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2297
2298 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2299 while (1) {
2300 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2301
2302 if ((r_value & poll_mask) != 0) {
2303 break;
2304 } else {
2305 msleep(1);
2306 if (--poll_wait == 0) {
2307 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2308 __func__);
2309 rval = QLA_ERROR;
2310 goto exit_process_pollrdmwr;
2311 }
2312 }
2313 }
2314
2315 *data_ptr++ = cpu_to_le32(addr_2);
2316 *data_ptr++ = cpu_to_le32(data);
2317 *d_ptr = data_ptr;
2318
2319exit_process_pollrdmwr:
2320 return rval;
2321}
2322
2323static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2324 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2325 uint32_t **d_ptr)
2326{
2327 uint32_t fl_addr, u32_count, rval;
2328 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2329 uint32_t *data_ptr = *d_ptr;
2330
2331 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2332 fl_addr = le32_to_cpu(rom_hdr->read_addr);
2333 u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2334
2335 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2336 __func__, fl_addr, u32_count));
2337
2338 rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2339 (u8 *)(data_ptr), u32_count);
2340
2341 if (rval == QLA_ERROR) {
2342 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2343 __func__, u32_count);
2344 goto exit_process_rdrom;
2345 }
2346
2347 data_ptr += u32_count;
2348 *d_ptr = data_ptr;
2349
2350exit_process_rdrom:
2351 return rval;
2352}
2353
2088/** 2354/**
2089 * qla82xx_collect_md_data - Retrieve firmware minidump data. 2355 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2090 * @ha: pointer to adapter structure 2356 * @ha: pointer to adapter structure
2091 **/ 2357 **/
2092static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 2358static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2093{ 2359{
2094 int num_entry_hdr = 0; 2360 int num_entry_hdr = 0;
2095 struct qla82xx_minidump_entry_hdr *entry_hdr; 2361 struct qla8xxx_minidump_entry_hdr *entry_hdr;
2096 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2362 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2097 uint32_t *data_ptr; 2363 uint32_t *data_ptr;
2098 uint32_t data_collected = 0; 2364 uint32_t data_collected = 0;
@@ -2128,10 +2394,14 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2128 timestamp = (u32)(jiffies_to_msecs(now) / 1000); 2394 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2129 tmplt_hdr->driver_timestamp = timestamp; 2395 tmplt_hdr->driver_timestamp = timestamp;
2130 2396
2131 entry_hdr = (struct qla82xx_minidump_entry_hdr *) 2397 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2132 (((uint8_t *)ha->fw_dump_tmplt_hdr) + 2398 (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2133 tmplt_hdr->first_entry_offset); 2399 tmplt_hdr->first_entry_offset);
2134 2400
2401 if (is_qla8032(ha))
2402 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
2403 tmplt_hdr->ocm_window_reg[ha->func_num];
2404
2135 /* Walk through the entry headers - validate/perform required action */ 2405 /* Walk through the entry headers - validate/perform required action */
2136 for (i = 0; i < num_entry_hdr; i++) { 2406 for (i = 0; i < num_entry_hdr; i++) {
2137 if (data_collected >= ha->fw_dump_size) { 2407 if (data_collected >= ha->fw_dump_size) {
@@ -2144,7 +2414,7 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2144 if (!(entry_hdr->d_ctrl.entry_capture_mask & 2414 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2145 ha->fw_dump_capture_mask)) { 2415 ha->fw_dump_capture_mask)) {
2146 entry_hdr->d_ctrl.driver_flags |= 2416 entry_hdr->d_ctrl.driver_flags |=
2147 QLA82XX_DBG_SKIPPED_FLAG; 2417 QLA8XXX_DBG_SKIPPED_FLAG;
2148 goto skip_nxt_entry; 2418 goto skip_nxt_entry;
2149 } 2419 }
2150 2420
@@ -2157,65 +2427,105 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2157 * debug data 2427 * debug data
2158 */ 2428 */
2159 switch (entry_hdr->entry_type) { 2429 switch (entry_hdr->entry_type) {
2160 case QLA82XX_RDEND: 2430 case QLA8XXX_RDEND:
2161 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2431 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2162 break; 2432 break;
2163 case QLA82XX_CNTRL: 2433 case QLA8XXX_CNTRL:
2164 rval = qla4_8xxx_minidump_process_control(ha, 2434 rval = qla4_8xxx_minidump_process_control(ha,
2165 entry_hdr); 2435 entry_hdr);
2166 if (rval != QLA_SUCCESS) { 2436 if (rval != QLA_SUCCESS) {
2167 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2437 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2168 goto md_failed; 2438 goto md_failed;
2169 } 2439 }
2170 break; 2440 break;
2171 case QLA82XX_RDCRB: 2441 case QLA8XXX_RDCRB:
2172 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 2442 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2173 &data_ptr); 2443 &data_ptr);
2174 break; 2444 break;
2175 case QLA82XX_RDMEM: 2445 case QLA8XXX_RDMEM:
2176 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 2446 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2177 &data_ptr); 2447 &data_ptr);
2178 if (rval != QLA_SUCCESS) { 2448 if (rval != QLA_SUCCESS) {
2179 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2449 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2180 goto md_failed; 2450 goto md_failed;
2181 } 2451 }
2182 break; 2452 break;
2183 case QLA82XX_BOARD: 2453 case QLA8XXX_BOARD:
2184 case QLA82XX_RDROM: 2454 case QLA8XXX_RDROM:
2185 qla4_8xxx_minidump_process_rdrom(ha, entry_hdr, 2455 if (is_qla8022(ha)) {
2186 &data_ptr); 2456 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2457 &data_ptr);
2458 } else if (is_qla8032(ha)) {
2459 rval = qla4_83xx_minidump_process_rdrom(ha,
2460 entry_hdr,
2461 &data_ptr);
2462 if (rval != QLA_SUCCESS)
2463 qla4_8xxx_mark_entry_skipped(ha,
2464 entry_hdr,
2465 i);
2466 }
2187 break; 2467 break;
2188 case QLA82XX_L2DTG: 2468 case QLA8XXX_L2DTG:
2189 case QLA82XX_L2ITG: 2469 case QLA8XXX_L2ITG:
2190 case QLA82XX_L2DAT: 2470 case QLA8XXX_L2DAT:
2191 case QLA82XX_L2INS: 2471 case QLA8XXX_L2INS:
2192 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 2472 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2193 &data_ptr); 2473 &data_ptr);
2194 if (rval != QLA_SUCCESS) { 2474 if (rval != QLA_SUCCESS) {
2195 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2475 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2196 goto md_failed; 2476 goto md_failed;
2197 } 2477 }
2198 break; 2478 break;
2199 case QLA82XX_L1DAT: 2479 case QLA8XXX_L1DTG:
2200 case QLA82XX_L1INS: 2480 case QLA8XXX_L1ITG:
2481 case QLA8XXX_L1DAT:
2482 case QLA8XXX_L1INS:
2201 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 2483 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2202 &data_ptr); 2484 &data_ptr);
2203 break; 2485 break;
2204 case QLA82XX_RDOCM: 2486 case QLA8XXX_RDOCM:
2205 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 2487 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2206 &data_ptr); 2488 &data_ptr);
2207 break; 2489 break;
2208 case QLA82XX_RDMUX: 2490 case QLA8XXX_RDMUX:
2209 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 2491 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2210 &data_ptr); 2492 &data_ptr);
2211 break; 2493 break;
2212 case QLA82XX_QUEUE: 2494 case QLA8XXX_QUEUE:
2213 qla4_8xxx_minidump_process_queue(ha, entry_hdr, 2495 qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2214 &data_ptr); 2496 &data_ptr);
2215 break; 2497 break;
2216 case QLA82XX_RDNOP: 2498 case QLA83XX_POLLRD:
2499 if (!is_qla8032(ha)) {
2500 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2501 break;
2502 }
2503 rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
2504 &data_ptr);
2505 if (rval != QLA_SUCCESS)
2506 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2507 break;
2508 case QLA83XX_RDMUX2:
2509 if (!is_qla8032(ha)) {
2510 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2511 break;
2512 }
2513 qla83xx_minidump_process_rdmux2(ha, entry_hdr,
2514 &data_ptr);
2515 break;
2516 case QLA83XX_POLLRDMWR:
2517 if (!is_qla8032(ha)) {
2518 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2519 break;
2520 }
2521 rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
2522 &data_ptr);
2523 if (rval != QLA_SUCCESS)
2524 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2525 break;
2526 case QLA8XXX_RDNOP:
2217 default: 2527 default:
2218 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2528 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2219 break; 2529 break;
2220 } 2530 }
2221 2531
@@ -2224,7 +2534,7 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2224 ha->fw_dump_tmplt_size)); 2534 ha->fw_dump_tmplt_size));
2225skip_nxt_entry: 2535skip_nxt_entry:
2226 /* next entry in the template */ 2536 /* next entry in the template */
2227 entry_hdr = (struct qla82xx_minidump_entry_hdr *) 2537 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2228 (((uint8_t *)entry_hdr) + 2538 (((uint8_t *)entry_hdr) +
2229 entry_hdr->entry_size); 2539 entry_hdr->entry_size);
2230 } 2540 }
@@ -2264,33 +2574,45 @@ static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2264 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 2574 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2265} 2575}
2266 2576
2577void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
2578{
2579 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2580 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2581 if (!qla4_8xxx_collect_md_data(ha)) {
2582 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2583 set_bit(AF_82XX_FW_DUMPED, &ha->flags);
2584 } else {
2585 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
2586 __func__);
2587 }
2588 }
2589}
2590
2267/** 2591/**
2268 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 2592 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2269 * @ha: pointer to adapter structure 2593 * @ha: pointer to adapter structure
2270 * 2594 *
2271 * Note: IDC lock must be held upon entry 2595 * Note: IDC lock must be held upon entry
2272 **/ 2596 **/
2273static int 2597int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2274qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2275{ 2598{
2276 int rval = QLA_ERROR; 2599 int rval = QLA_ERROR;
2277 int i, timeout; 2600 int i, timeout;
2278 uint32_t old_count, count; 2601 uint32_t old_count, count, idc_ctrl;
2279 int need_reset = 0, peg_stuck = 1; 2602 int need_reset = 0, peg_stuck = 1;
2280 2603
2281 need_reset = qla4_8xxx_need_reset(ha); 2604 need_reset = ha->isp_ops->need_reset(ha);
2282 2605 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2283 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2284 2606
2285 for (i = 0; i < 10; i++) { 2607 for (i = 0; i < 10; i++) {
2286 timeout = msleep_interruptible(200); 2608 timeout = msleep_interruptible(200);
2287 if (timeout) { 2609 if (timeout) {
2288 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2610 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2289 QLA82XX_DEV_FAILED); 2611 QLA8XXX_DEV_FAILED);
2290 return rval; 2612 return rval;
2291 } 2613 }
2292 2614
2293 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2615 count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2294 if (count != old_count) 2616 if (count != old_count)
2295 peg_stuck = 0; 2617 peg_stuck = 0;
2296 } 2618 }
@@ -2298,13 +2620,13 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2298 if (need_reset) { 2620 if (need_reset) {
2299 /* We are trying to perform a recovery here. */ 2621 /* We are trying to perform a recovery here. */
2300 if (peg_stuck) 2622 if (peg_stuck)
2301 qla4_8xxx_rom_lock_recovery(ha); 2623 ha->isp_ops->rom_lock_recovery(ha);
2302 goto dev_initialize; 2624 goto dev_initialize;
2303 } else { 2625 } else {
2304 /* Start of day for this ha context. */ 2626 /* Start of day for this ha context. */
2305 if (peg_stuck) { 2627 if (peg_stuck) {
2306 /* Either we are the first or recovery in progress. */ 2628 /* Either we are the first or recovery in progress. */
2307 qla4_8xxx_rom_lock_recovery(ha); 2629 ha->isp_ops->rom_lock_recovery(ha);
2308 goto dev_initialize; 2630 goto dev_initialize;
2309 } else { 2631 } else {
2310 /* Firmware already running. */ 2632 /* Firmware already running. */
@@ -2316,46 +2638,53 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2316dev_initialize: 2638dev_initialize:
2317 /* set to DEV_INITIALIZING */ 2639 /* set to DEV_INITIALIZING */
2318 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 2640 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2319 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2641 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2642 QLA8XXX_DEV_INITIALIZING);
2320 2643
2321 /* Driver that sets device state to initializating sets IDC version */ 2644 /*
2322 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2645 * For ISP8324, if IDC_CTRL GRACEFUL_RESET_BIT1 is set, reset it after
2323 2646 * device goes to INIT state.
2324 qla4_8xxx_idc_unlock(ha); 2647 */
2325 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 2648 if (is_qla8032(ha)) {
2326 !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 2649 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
2327 if (!qla4_8xxx_collect_md_data(ha)) { 2650 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
2328 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 2651 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL,
2329 } else { 2652 (idc_ctrl & ~GRACEFUL_RESET_BIT1));
2330 ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n"); 2653 set_bit(AF_83XX_NO_FW_DUMP, &ha->flags);
2331 clear_bit(AF_82XX_FW_DUMPED, &ha->flags);
2332 } 2654 }
2333 } 2655 }
2334 rval = qla4_8xxx_try_start_fw(ha); 2656
2335 qla4_8xxx_idc_lock(ha); 2657 ha->isp_ops->idc_unlock(ha);
2658
2659 if (is_qla8022(ha))
2660 qla4_8xxx_get_minidump(ha);
2661
2662 rval = ha->isp_ops->restart_firmware(ha);
2663 ha->isp_ops->idc_lock(ha);
2336 2664
2337 if (rval != QLA_SUCCESS) { 2665 if (rval != QLA_SUCCESS) {
2338 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 2666 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2339 qla4_8xxx_clear_drv_active(ha); 2667 qla4_8xxx_clear_drv_active(ha);
2340 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2668 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2669 QLA8XXX_DEV_FAILED);
2341 return rval; 2670 return rval;
2342 } 2671 }
2343 2672
2344dev_ready: 2673dev_ready:
2345 ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 2674 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2346 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2675 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2347 2676
2348 return rval; 2677 return rval;
2349} 2678}
2350 2679
2351/** 2680/**
2352 * qla4_8xxx_need_reset_handler - Code to start reset sequence 2681 * qla4_82xx_need_reset_handler - Code to start reset sequence
2353 * @ha: pointer to adapter structure 2682 * @ha: pointer to adapter structure
2354 * 2683 *
2355 * Note: IDC lock must be held upon entry 2684 * Note: IDC lock must be held upon entry
2356 **/ 2685 **/
2357static void 2686static void
2358qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha) 2687qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2359{ 2688{
2360 uint32_t dev_state, drv_state, drv_active; 2689 uint32_t dev_state, drv_state, drv_active;
2361 uint32_t active_mask = 0xFFFFFFFF; 2690 uint32_t active_mask = 0xFFFFFFFF;
@@ -2365,12 +2694,12 @@ qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
2365 "Performing ISP error recovery\n"); 2694 "Performing ISP error recovery\n");
2366 2695
2367 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 2696 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2368 qla4_8xxx_idc_unlock(ha); 2697 qla4_82xx_idc_unlock(ha);
2369 ha->isp_ops->disable_intrs(ha); 2698 ha->isp_ops->disable_intrs(ha);
2370 qla4_8xxx_idc_lock(ha); 2699 qla4_82xx_idc_lock(ha);
2371 } 2700 }
2372 2701
2373 if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) { 2702 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2374 DEBUG2(ql4_printk(KERN_INFO, ha, 2703 DEBUG2(ql4_printk(KERN_INFO, ha,
2375 "%s(%ld): reset acknowledged\n", 2704 "%s(%ld): reset acknowledged\n",
2376 __func__, ha->host_no)); 2705 __func__, ha->host_no));
@@ -2382,8 +2711,8 @@ qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
2382 /* wait for 10 seconds for reset ack from all functions */ 2711 /* wait for 10 seconds for reset ack from all functions */
2383 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 2712 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2384 2713
2385 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2714 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2386 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2715 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2387 2716
2388 ql4_printk(KERN_INFO, ha, 2717 ql4_printk(KERN_INFO, ha,
2389 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2718 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
@@ -2401,31 +2730,31 @@ qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
2401 * When reset_owner times out, check which functions 2730 * When reset_owner times out, check which functions
2402 * acked/did not ack 2731 * acked/did not ack
2403 */ 2732 */
2404 if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) { 2733 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2405 ql4_printk(KERN_INFO, ha, 2734 ql4_printk(KERN_INFO, ha,
2406 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2735 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2407 __func__, ha->host_no, drv_state, 2736 __func__, ha->host_no, drv_state,
2408 drv_active); 2737 drv_active);
2409 } 2738 }
2410 qla4_8xxx_idc_unlock(ha); 2739 qla4_82xx_idc_unlock(ha);
2411 msleep(1000); 2740 msleep(1000);
2412 qla4_8xxx_idc_lock(ha); 2741 qla4_82xx_idc_lock(ha);
2413 2742
2414 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2743 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2415 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2744 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2416 } 2745 }
2417 2746
2418 /* Clear RESET OWNER as we are not going to use it any further */ 2747 /* Clear RESET OWNER as we are not going to use it any further */
2419 clear_bit(AF_82XX_RST_OWNER, &ha->flags); 2748 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
2420 2749
2421 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2750 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2422 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 2751 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2423 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 2752 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2424 2753
2425 /* Force to DEV_COLD unless someone else is starting a reset */ 2754 /* Force to DEV_COLD unless someone else is starting a reset */
2426 if (dev_state != QLA82XX_DEV_INITIALIZING) { 2755 if (dev_state != QLA8XXX_DEV_INITIALIZING) {
2427 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 2756 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2428 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 2757 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
2429 qla4_8xxx_set_rst_ready(ha); 2758 qla4_8xxx_set_rst_ready(ha);
2430 } 2759 }
2431} 2760}
@@ -2437,9 +2766,104 @@ qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
2437void 2766void
2438qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 2767qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2439{ 2768{
2440 qla4_8xxx_idc_lock(ha); 2769 ha->isp_ops->idc_lock(ha);
2441 qla4_8xxx_set_qsnt_ready(ha); 2770 qla4_8xxx_set_qsnt_ready(ha);
2442 qla4_8xxx_idc_unlock(ha); 2771 ha->isp_ops->idc_unlock(ha);
2772}
2773
2774static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
2775{
2776 int idc_ver;
2777 uint32_t drv_active;
2778
2779 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2780 if (drv_active == (1 << (ha->func_num * 4))) {
2781 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
2782 QLA82XX_IDC_VERSION);
2783 ql4_printk(KERN_INFO, ha,
2784 "%s: IDC version updated to %d\n", __func__,
2785 QLA82XX_IDC_VERSION);
2786 } else {
2787 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2788 if (QLA82XX_IDC_VERSION != idc_ver) {
2789 ql4_printk(KERN_INFO, ha,
2790 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
2791 __func__, QLA82XX_IDC_VERSION, idc_ver);
2792 }
2793 }
2794}
2795
2796static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
2797{
2798 int idc_ver;
2799 uint32_t drv_active;
2800 int rval = QLA_SUCCESS;
2801
2802 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2803 if (drv_active == (1 << ha->func_num)) {
2804 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2805 idc_ver &= (~0xFF);
2806 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
2807 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
2808 ql4_printk(KERN_INFO, ha,
2809 "%s: IDC version updated to %d\n", __func__,
2810 idc_ver);
2811 } else {
2812 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2813 idc_ver &= 0xFF;
2814 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
2815 ql4_printk(KERN_INFO, ha,
2816 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
2817 __func__, QLA83XX_IDC_VER_MAJ_VALUE,
2818 idc_ver);
2819 rval = QLA_ERROR;
2820 goto exit_set_idc_ver;
2821 }
2822 }
2823
2824 /* Update IDC_MINOR_VERSION */
2825 idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
2826 idc_ver &= ~(0x03 << (ha->func_num * 2));
2827 idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
2828 qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
2829
2830exit_set_idc_ver:
2831 return rval;
2832}
2833
2834int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
2835{
2836 uint32_t drv_active;
2837 int rval = QLA_SUCCESS;
2838
2839 if (test_bit(AF_INIT_DONE, &ha->flags))
2840 goto exit_update_idc_reg;
2841
2842 ha->isp_ops->idc_lock(ha);
2843 qla4_8xxx_set_drv_active(ha);
2844
2845 /*
2846 * If we are the first driver to load and
2847 * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
2848 */
2849 if (is_qla8032(ha)) {
2850 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2851 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
2852 qla4_83xx_clear_idc_dontreset(ha);
2853 }
2854
2855 if (is_qla8022(ha)) {
2856 qla4_82xx_set_idc_ver(ha);
2857 } else if (is_qla8032(ha)) {
2858 rval = qla4_83xx_set_idc_ver(ha);
2859 if (rval == QLA_ERROR)
2860 qla4_8xxx_clear_drv_active(ha);
2861 }
2862
2863 ha->isp_ops->idc_unlock(ha);
2864
2865exit_update_idc_reg:
2866 return rval;
2443} 2867}
2444 2868
2445/** 2869/**
@@ -2454,13 +2878,11 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2454 int rval = QLA_SUCCESS; 2878 int rval = QLA_SUCCESS;
2455 unsigned long dev_init_timeout; 2879 unsigned long dev_init_timeout;
2456 2880
2457 if (!test_bit(AF_INIT_DONE, &ha->flags)) { 2881 rval = qla4_8xxx_update_idc_reg(ha);
2458 qla4_8xxx_idc_lock(ha); 2882 if (rval == QLA_ERROR)
2459 qla4_8xxx_set_drv_active(ha); 2883 goto exit_state_handler;
2460 qla4_8xxx_idc_unlock(ha);
2461 }
2462 2884
2463 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2885 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2464 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2886 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2465 dev_state, dev_state < MAX_STATES ? 2887 dev_state, dev_state < MAX_STATES ?
2466 qdev_state[dev_state] : "Unknown")); 2888 qdev_state[dev_state] : "Unknown"));
@@ -2468,7 +2890,7 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2468 /* wait for 30 seconds for device to go ready */ 2890 /* wait for 30 seconds for device to go ready */
2469 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 2891 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2470 2892
2471 qla4_8xxx_idc_lock(ha); 2893 ha->isp_ops->idc_lock(ha);
2472 while (1) { 2894 while (1) {
2473 2895
2474 if (time_after_eq(jiffies, dev_init_timeout)) { 2896 if (time_after_eq(jiffies, dev_init_timeout)) {
@@ -2477,65 +2899,75 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2477 DRIVER_NAME, 2899 DRIVER_NAME,
2478 dev_state, dev_state < MAX_STATES ? 2900 dev_state, dev_state < MAX_STATES ?
2479 qdev_state[dev_state] : "Unknown"); 2901 qdev_state[dev_state] : "Unknown");
2480 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2902 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2481 QLA82XX_DEV_FAILED); 2903 QLA8XXX_DEV_FAILED);
2482 } 2904 }
2483 2905
2484 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2906 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2485 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2907 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2486 dev_state, dev_state < MAX_STATES ? 2908 dev_state, dev_state < MAX_STATES ?
2487 qdev_state[dev_state] : "Unknown"); 2909 qdev_state[dev_state] : "Unknown");
2488 2910
2489 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 2911 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2490 switch (dev_state) { 2912 switch (dev_state) {
2491 case QLA82XX_DEV_READY: 2913 case QLA8XXX_DEV_READY:
2492 goto exit; 2914 goto exit;
2493 case QLA82XX_DEV_COLD: 2915 case QLA8XXX_DEV_COLD:
2494 rval = qla4_8xxx_device_bootstrap(ha); 2916 rval = qla4_8xxx_device_bootstrap(ha);
2495 goto exit; 2917 goto exit;
2496 case QLA82XX_DEV_INITIALIZING: 2918 case QLA8XXX_DEV_INITIALIZING:
2497 qla4_8xxx_idc_unlock(ha); 2919 ha->isp_ops->idc_unlock(ha);
2498 msleep(1000); 2920 msleep(1000);
2499 qla4_8xxx_idc_lock(ha); 2921 ha->isp_ops->idc_lock(ha);
2500 break; 2922 break;
2501 case QLA82XX_DEV_NEED_RESET: 2923 case QLA8XXX_DEV_NEED_RESET:
2502 if (!ql4xdontresethba) { 2924 /*
2503 qla4_8xxx_need_reset_handler(ha); 2925 * For ISP8324, if NEED_RESET is set by any driver,
2504 /* Update timeout value after need 2926 * it should be honored, irrespective of IDC_CTRL
2505 * reset handler */ 2927 * DONTRESET_BIT0
2506 dev_init_timeout = jiffies + 2928 */
2507 (ha->nx_dev_init_timeout * HZ); 2929 if (is_qla8032(ha)) {
2508 } else { 2930 qla4_83xx_need_reset_handler(ha);
2509 qla4_8xxx_idc_unlock(ha); 2931 } else if (is_qla8022(ha)) {
2510 msleep(1000); 2932 if (!ql4xdontresethba) {
2511 qla4_8xxx_idc_lock(ha); 2933 qla4_82xx_need_reset_handler(ha);
2934 /* Update timeout value after need
2935 * reset handler */
2936 dev_init_timeout = jiffies +
2937 (ha->nx_dev_init_timeout * HZ);
2938 } else {
2939 ha->isp_ops->idc_unlock(ha);
2940 msleep(1000);
2941 ha->isp_ops->idc_lock(ha);
2942 }
2512 } 2943 }
2513 break; 2944 break;
2514 case QLA82XX_DEV_NEED_QUIESCENT: 2945 case QLA8XXX_DEV_NEED_QUIESCENT:
2515 /* idc locked/unlocked in handler */ 2946 /* idc locked/unlocked in handler */
2516 qla4_8xxx_need_qsnt_handler(ha); 2947 qla4_8xxx_need_qsnt_handler(ha);
2517 break; 2948 break;
2518 case QLA82XX_DEV_QUIESCENT: 2949 case QLA8XXX_DEV_QUIESCENT:
2519 qla4_8xxx_idc_unlock(ha); 2950 ha->isp_ops->idc_unlock(ha);
2520 msleep(1000); 2951 msleep(1000);
2521 qla4_8xxx_idc_lock(ha); 2952 ha->isp_ops->idc_lock(ha);
2522 break; 2953 break;
2523 case QLA82XX_DEV_FAILED: 2954 case QLA8XXX_DEV_FAILED:
2524 qla4_8xxx_idc_unlock(ha); 2955 ha->isp_ops->idc_unlock(ha);
2525 qla4xxx_dead_adapter_cleanup(ha); 2956 qla4xxx_dead_adapter_cleanup(ha);
2526 rval = QLA_ERROR; 2957 rval = QLA_ERROR;
2527 qla4_8xxx_idc_lock(ha); 2958 ha->isp_ops->idc_lock(ha);
2528 goto exit; 2959 goto exit;
2529 default: 2960 default:
2530 qla4_8xxx_idc_unlock(ha); 2961 ha->isp_ops->idc_unlock(ha);
2531 qla4xxx_dead_adapter_cleanup(ha); 2962 qla4xxx_dead_adapter_cleanup(ha);
2532 rval = QLA_ERROR; 2963 rval = QLA_ERROR;
2533 qla4_8xxx_idc_lock(ha); 2964 ha->isp_ops->idc_lock(ha);
2534 goto exit; 2965 goto exit;
2535 } 2966 }
2536 } 2967 }
2537exit: 2968exit:
2538 qla4_8xxx_idc_unlock(ha); 2969 ha->isp_ops->idc_unlock(ha);
2970exit_state_handler:
2539 return rval; 2971 return rval;
2540} 2972}
2541 2973
@@ -2544,8 +2976,13 @@ int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2544 int retval; 2976 int retval;
2545 2977
2546 /* clear the interrupt */ 2978 /* clear the interrupt */
2547 writel(0, &ha->qla4_8xxx_reg->host_int); 2979 if (is_qla8032(ha)) {
2548 readl(&ha->qla4_8xxx_reg->host_int); 2980 writel(0, &ha->qla4_83xx_reg->risc_intr);
2981 readl(&ha->qla4_83xx_reg->risc_intr);
2982 } else if (is_qla8022(ha)) {
2983 writel(0, &ha->qla4_82xx_reg->host_int);
2984 readl(&ha->qla4_82xx_reg->host_int);
2985 }
2549 2986
2550 retval = qla4_8xxx_device_state_handler(ha); 2987 retval = qla4_8xxx_device_state_handler(ha);
2551 2988
@@ -2579,13 +3016,13 @@ flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2579} 3016}
2580 3017
2581static uint32_t * 3018static uint32_t *
2582qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 3019qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2583 uint32_t faddr, uint32_t length) 3020 uint32_t faddr, uint32_t length)
2584{ 3021{
2585 uint32_t i; 3022 uint32_t i;
2586 uint32_t val; 3023 uint32_t val;
2587 int loops = 0; 3024 int loops = 0;
2588 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 3025 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
2589 udelay(100); 3026 udelay(100);
2590 cond_resched(); 3027 cond_resched();
2591 loops++; 3028 loops++;
@@ -2597,7 +3034,7 @@ qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2597 3034
2598 /* Dword reads to flash. */ 3035 /* Dword reads to flash. */
2599 for (i = 0; i < length/4; i++, faddr += 4) { 3036 for (i = 0; i < length/4; i++, faddr += 4) {
2600 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) { 3037 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
2601 ql4_printk(KERN_WARNING, ha, 3038 ql4_printk(KERN_WARNING, ha,
2602 "Do ROM fast read failed\n"); 3039 "Do ROM fast read failed\n");
2603 goto done_read; 3040 goto done_read;
@@ -2606,7 +3043,7 @@ qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2606 } 3043 }
2607 3044
2608done_read: 3045done_read:
2609 qla4_8xxx_rom_unlock(ha); 3046 qla4_82xx_rom_unlock(ha);
2610 return dwptr; 3047 return dwptr;
2611} 3048}
2612 3049
@@ -2614,10 +3051,10 @@ done_read:
2614 * Address and length are byte address 3051 * Address and length are byte address
2615 **/ 3052 **/
2616static uint8_t * 3053static uint8_t *
2617qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 3054qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2618 uint32_t offset, uint32_t length) 3055 uint32_t offset, uint32_t length)
2619{ 3056{
2620 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length); 3057 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
2621 return buf; 3058 return buf;
2622} 3059}
2623 3060
@@ -2644,7 +3081,7 @@ qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
2644 const char *loc, *locations[] = { "DEF", "FLT" }; 3081 const char *loc, *locations[] = { "DEF", "FLT" };
2645 uint16_t *wptr; 3082 uint16_t *wptr;
2646 uint16_t cnt, chksum; 3083 uint16_t cnt, chksum;
2647 uint32_t start; 3084 uint32_t start, status;
2648 struct qla_flt_header *flt; 3085 struct qla_flt_header *flt;
2649 struct qla_flt_region *region; 3086 struct qla_flt_region *region;
2650 struct ql82xx_hw_data *hw = &ha->hw; 3087 struct ql82xx_hw_data *hw = &ha->hw;
@@ -2653,8 +3090,18 @@ qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
2653 wptr = (uint16_t *)ha->request_ring; 3090 wptr = (uint16_t *)ha->request_ring;
2654 flt = (struct qla_flt_header *)ha->request_ring; 3091 flt = (struct qla_flt_header *)ha->request_ring;
2655 region = (struct qla_flt_region *)&flt[1]; 3092 region = (struct qla_flt_region *)&flt[1];
2656 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3093
2657 flt_addr << 2, OPTROM_BURST_SIZE); 3094 if (is_qla8022(ha)) {
3095 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3096 flt_addr << 2, OPTROM_BURST_SIZE);
3097 } else if (is_qla8032(ha)) {
3098 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3099 (uint8_t *)ha->request_ring,
3100 0x400);
3101 if (status != QLA_SUCCESS)
3102 goto no_flash_data;
3103 }
3104
2658 if (*wptr == __constant_cpu_to_le16(0xffff)) 3105 if (*wptr == __constant_cpu_to_le16(0xffff))
2659 goto no_flash_data; 3106 goto no_flash_data;
2660 if (flt->version != __constant_cpu_to_le16(1)) { 3107 if (flt->version != __constant_cpu_to_le16(1)) {
@@ -2730,7 +3177,7 @@ done:
2730} 3177}
2731 3178
2732static void 3179static void
2733qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha) 3180qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
2734{ 3181{
2735#define FLASH_BLK_SIZE_4K 0x1000 3182#define FLASH_BLK_SIZE_4K 0x1000
2736#define FLASH_BLK_SIZE_32K 0x8000 3183#define FLASH_BLK_SIZE_32K 0x8000
@@ -2748,7 +3195,7 @@ qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
2748 3195
2749 wptr = (uint16_t *)ha->request_ring; 3196 wptr = (uint16_t *)ha->request_ring;
2750 fdt = (struct qla_fdt_layout *)ha->request_ring; 3197 fdt = (struct qla_fdt_layout *)ha->request_ring;
2751 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3198 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2752 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 3199 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2753 3200
2754 if (*wptr == __constant_cpu_to_le16(0xffff)) 3201 if (*wptr == __constant_cpu_to_le16(0xffff))
@@ -2797,7 +3244,7 @@ done:
2797} 3244}
2798 3245
2799static void 3246static void
2800qla4_8xxx_get_idc_param(struct scsi_qla_host *ha) 3247qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
2801{ 3248{
2802#define QLA82XX_IDC_PARAM_ADDR 0x003e885c 3249#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2803 uint32_t *wptr; 3250 uint32_t *wptr;
@@ -2805,7 +3252,7 @@ qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2805 if (!is_qla8022(ha)) 3252 if (!is_qla8022(ha))
2806 return; 3253 return;
2807 wptr = (uint32_t *)ha->request_ring; 3254 wptr = (uint32_t *)ha->request_ring;
2808 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3255 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2809 QLA82XX_IDC_PARAM_ADDR , 8); 3256 QLA82XX_IDC_PARAM_ADDR , 8);
2810 3257
2811 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 3258 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
@@ -2823,6 +3270,39 @@ qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2823 return; 3270 return;
2824} 3271}
2825 3272
3273void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3274 int in_count)
3275{
3276 int i;
3277
3278 /* Load all mailbox registers, except mailbox 0. */
3279 for (i = 1; i < in_count; i++)
3280 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3281
3282 /* Wakeup firmware */
3283 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3284 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3285 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3286 readl(&ha->qla4_82xx_reg->hint);
3287}
3288
3289void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3290{
3291 int intr_status;
3292
3293 intr_status = readl(&ha->qla4_82xx_reg->host_int);
3294 if (intr_status & ISRX_82XX_RISC_INT) {
3295 ha->mbox_status_count = out_count;
3296 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3297 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3298
3299 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3300 test_bit(AF_INTx_ENABLED, &ha->flags))
3301 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3302 0xfbff);
3303 }
3304}
3305
2826int 3306int
2827qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 3307qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2828{ 3308{
@@ -2834,8 +3314,12 @@ qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2834 return ret; 3314 return ret;
2835 3315
2836 qla4_8xxx_get_flt_info(ha, flt_addr); 3316 qla4_8xxx_get_flt_info(ha, flt_addr);
2837 qla4_8xxx_get_fdt_info(ha); 3317 if (is_qla8022(ha)) {
2838 qla4_8xxx_get_idc_param(ha); 3318 qla4_82xx_get_fdt_info(ha);
3319 qla4_82xx_get_idc_param(ha);
3320 } else if (is_qla8032(ha)) {
3321 qla4_83xx_get_idc_param(ha);
3322 }
2839 3323
2840 return QLA_SUCCESS; 3324 return QLA_SUCCESS;
2841} 3325}
@@ -2869,36 +3353,36 @@ qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2869} 3353}
2870 3354
2871/** 3355/**
2872 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands. 3356 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
2873 * @ha: pointer to host adapter structure. 3357 * @ha: pointer to host adapter structure.
2874 **/ 3358 **/
2875int 3359int
2876qla4_8xxx_isp_reset(struct scsi_qla_host *ha) 3360qla4_82xx_isp_reset(struct scsi_qla_host *ha)
2877{ 3361{
2878 int rval; 3362 int rval;
2879 uint32_t dev_state; 3363 uint32_t dev_state;
2880 3364
2881 qla4_8xxx_idc_lock(ha); 3365 qla4_82xx_idc_lock(ha);
2882 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3366 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2883 3367
2884 if (dev_state == QLA82XX_DEV_READY) { 3368 if (dev_state == QLA8XXX_DEV_READY) {
2885 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 3369 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2886 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3370 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2887 QLA82XX_DEV_NEED_RESET); 3371 QLA8XXX_DEV_NEED_RESET);
2888 set_bit(AF_82XX_RST_OWNER, &ha->flags); 3372 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
2889 } else 3373 } else
2890 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 3374 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2891 3375
2892 qla4_8xxx_idc_unlock(ha); 3376 qla4_82xx_idc_unlock(ha);
2893 3377
2894 rval = qla4_8xxx_device_state_handler(ha); 3378 rval = qla4_8xxx_device_state_handler(ha);
2895 3379
2896 qla4_8xxx_idc_lock(ha); 3380 qla4_82xx_idc_lock(ha);
2897 qla4_8xxx_clear_rst_ready(ha); 3381 qla4_8xxx_clear_rst_ready(ha);
2898 qla4_8xxx_idc_unlock(ha); 3382 qla4_82xx_idc_unlock(ha);
2899 3383
2900 if (rval == QLA_SUCCESS) { 3384 if (rval == QLA_SUCCESS) {
2901 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_8xxx_isp_reset\n"); 3385 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
2902 clear_bit(AF_FW_RECOVERY, &ha->flags); 3386 clear_bit(AF_FW_RECOVERY, &ha->flags);
2903 } 3387 }
2904 3388
@@ -2979,8 +3463,7 @@ exit_validate_mac82:
2979 3463
2980/* Interrupt handling helpers. */ 3464/* Interrupt handling helpers. */
2981 3465
2982static int 3466int qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2983qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2984{ 3467{
2985 uint32_t mbox_cmd[MBOX_REG_COUNT]; 3468 uint32_t mbox_cmd[MBOX_REG_COUNT];
2986 uint32_t mbox_sts[MBOX_REG_COUNT]; 3469 uint32_t mbox_sts[MBOX_REG_COUNT];
@@ -3001,8 +3484,7 @@ qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
3001 return QLA_SUCCESS; 3484 return QLA_SUCCESS;
3002} 3485}
3003 3486
3004static int 3487int qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
3005qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
3006{ 3488{
3007 uint32_t mbox_cmd[MBOX_REG_COUNT]; 3489 uint32_t mbox_cmd[MBOX_REG_COUNT];
3008 uint32_t mbox_sts[MBOX_REG_COUNT]; 3490 uint32_t mbox_sts[MBOX_REG_COUNT];
@@ -3025,26 +3507,26 @@ qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
3025} 3507}
3026 3508
3027void 3509void
3028qla4_8xxx_enable_intrs(struct scsi_qla_host *ha) 3510qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
3029{ 3511{
3030 qla4_8xxx_mbx_intr_enable(ha); 3512 qla4_8xxx_mbx_intr_enable(ha);
3031 3513
3032 spin_lock_irq(&ha->hardware_lock); 3514 spin_lock_irq(&ha->hardware_lock);
3033 /* BIT 10 - reset */ 3515 /* BIT 10 - reset */
3034 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 3516 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3035 spin_unlock_irq(&ha->hardware_lock); 3517 spin_unlock_irq(&ha->hardware_lock);
3036 set_bit(AF_INTERRUPTS_ON, &ha->flags); 3518 set_bit(AF_INTERRUPTS_ON, &ha->flags);
3037} 3519}
3038 3520
3039void 3521void
3040qla4_8xxx_disable_intrs(struct scsi_qla_host *ha) 3522qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
3041{ 3523{
3042 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 3524 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3043 qla4_8xxx_mbx_intr_disable(ha); 3525 qla4_8xxx_mbx_intr_disable(ha);
3044 3526
3045 spin_lock_irq(&ha->hardware_lock); 3527 spin_lock_irq(&ha->hardware_lock);
3046 /* BIT 10 - set */ 3528 /* BIT 10 - set */
3047 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 3529 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3048 spin_unlock_irq(&ha->hardware_lock); 3530 spin_unlock_irq(&ha->hardware_lock);
3049} 3531}
3050 3532
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 05:41:58 -0500