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authorDavid Somayajulu <david.somayajulu@qlogic.com>2006-09-19 13:28:00 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-10-04 14:34:04 -0400
commitafaf5a2d341d33b66b47c2716a263ce593460a08 (patch)
tree70aeac2f11cc644114eead55fa003be8288666f0 /drivers/scsi/qla4xxx/ql4_def.h
parented542bed126caeefc6546b276e4af852d4d34f33 (diff)
[SCSI] Initial Commit of qla4xxx
open-iSCSI driver for Qlogic Corporation's iSCSI HBAs Signed-off-by: Ravi Anand <ravi.anand@qlogic.com> Signed-off-by: David Somayajulu <david.somayajulu@qlogic.com> Signed-off-by: Doug Maxey <dwm@bubba.enoyolf.org> Signed-off-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_def.h')
-rw-r--r--drivers/scsi/qla4xxx/ql4_def.h586
1 files changed, 586 insertions, 0 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_def.h b/drivers/scsi/qla4xxx/ql4_def.h
new file mode 100644
index 000000000000..a7f6c7b1c590
--- /dev/null
+++ b/drivers/scsi/qla4xxx/ql4_def.h
@@ -0,0 +1,586 @@
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
27
28#include <net/tcp.h>
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport.h>
34#include <scsi/scsi_transport_iscsi.h>
35
36
37#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
38#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
39#endif
40
41#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
42#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
43#endif /* */
44
45#define QLA_SUCCESS 0
46#define QLA_ERROR 1
47
48/*
49 * Data bit definitions
50 */
51#define BIT_0 0x1
52#define BIT_1 0x2
53#define BIT_2 0x4
54#define BIT_3 0x8
55#define BIT_4 0x10
56#define BIT_5 0x20
57#define BIT_6 0x40
58#define BIT_7 0x80
59#define BIT_8 0x100
60#define BIT_9 0x200
61#define BIT_10 0x400
62#define BIT_11 0x800
63#define BIT_12 0x1000
64#define BIT_13 0x2000
65#define BIT_14 0x4000
66#define BIT_15 0x8000
67#define BIT_16 0x10000
68#define BIT_17 0x20000
69#define BIT_18 0x40000
70#define BIT_19 0x80000
71#define BIT_20 0x100000
72#define BIT_21 0x200000
73#define BIT_22 0x400000
74#define BIT_23 0x800000
75#define BIT_24 0x1000000
76#define BIT_25 0x2000000
77#define BIT_26 0x4000000
78#define BIT_27 0x8000000
79#define BIT_28 0x10000000
80#define BIT_29 0x20000000
81#define BIT_30 0x40000000
82#define BIT_31 0x80000000
83
84/*
85 * Host adapter default definitions
86 ***********************************/
87#define MAX_HBAS 16
88#define MAX_BUSES 1
89#define MAX_TARGETS (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
90#define MAX_LUNS 0xffff
91#define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
92#define MAX_DDB_ENTRIES (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
93#define MAX_PDU_ENTRIES 32
94#define INVALID_ENTRY 0xFFFF
95#define MAX_CMDS_TO_RISC 1024
96#define MAX_SRBS MAX_CMDS_TO_RISC
97#define MBOX_AEN_REG_COUNT 5
98#define MAX_INIT_RETRIES 5
99#define IOCB_HIWAT_CUSHION 16
100
101/*
102 * Buffer sizes
103 */
104#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
105#define RESPONSE_QUEUE_DEPTH 64
106#define QUEUE_SIZE 64
107#define DMA_BUFFER_SIZE 512
108
109/*
110 * Misc
111 */
112#define MAC_ADDR_LEN 6 /* in bytes */
113#define IP_ADDR_LEN 4 /* in bytes */
114#define DRIVER_NAME "qla4xxx"
115
116#define MAX_LINKED_CMDS_PER_LUN 3
117#define MAX_REQS_SERVICED_PER_INTR 16
118
119#define ISCSI_IPADDR_SIZE 4 /* IP address size */
120#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alais name size */
121#define ISCSI_NAME_SIZE 255 /* ISCSI Name size -
122 * usually a string */
123
124#define LSDW(x) ((u32)((u64)(x)))
125#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
126
127/*
128 * Retry & Timeout Values
129 */
130#define MBOX_TOV 60
131#define SOFT_RESET_TOV 30
132#define RESET_INTR_TOV 3
133#define SEMAPHORE_TOV 10
134#define ADAPTER_INIT_TOV 120
135#define ADAPTER_RESET_TOV 180
136#define EXTEND_CMD_TOV 60
137#define WAIT_CMD_TOV 30
138#define EH_WAIT_CMD_TOV 120
139#define FIRMWARE_UP_TOV 60
140#define RESET_FIRMWARE_TOV 30
141#define LOGOUT_TOV 10
142#define IOCB_TOV_MARGIN 10
143#define RELOGIN_TOV 18
144#define ISNS_DEREG_TOV 5
145
146#define MAX_RESET_HA_RETRIES 2
147
148/*
149 * SCSI Request Block structure (srb) that is placed
150 * on cmd->SCp location of every I/O [We have 22 bytes available]
151 */
152struct srb {
153 struct list_head list; /* (8) */
154 struct scsi_qla_host *ha; /* HA the SP is queued on */
155 struct ddb_entry *ddb;
156 uint16_t flags; /* (1) Status flags. */
157
158#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
159#define SRB_GOT_SENSE BIT_4 /* sense data recieved. */
160 uint8_t state; /* (1) Status flags. */
161
162#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
163#define SRB_FREE_STATE 1
164#define SRB_ACTIVE_STATE 3
165#define SRB_ACTIVE_TIMEOUT_STATE 4
166#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
167
168 struct scsi_cmnd *cmd; /* (4) SCSI command block */
169 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
170 atomic_t ref_count; /* reference count for this srb */
171 uint32_t fw_ddb_index;
172 uint8_t err_id; /* error id */
173#define SRB_ERR_PORT 1 /* Request failed because "port down" */
174#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
175#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
176#define SRB_ERR_OTHER 4
177
178 uint16_t reserved;
179 uint16_t iocb_tov;
180 uint16_t iocb_cnt; /* Number of used iocbs */
181 uint16_t cc_stat;
182 u_long r_start; /* Time we recieve a cmd from OS */
183 u_long u_start; /* Time when we handed the cmd to F/W */
184};
185
186 /*
187 * Device Database (DDB) structure
188 */
189struct ddb_entry {
190 struct list_head list; /* ddb list */
191 struct scsi_qla_host *ha;
192 struct iscsi_cls_session *sess;
193 struct iscsi_cls_conn *conn;
194
195 atomic_t state; /* DDB State */
196
197 unsigned long flags; /* DDB Flags */
198
199 unsigned long dev_scan_wait_to_start_relogin;
200 unsigned long dev_scan_wait_to_complete_relogin;
201
202 uint16_t os_target_id; /* Target ID */
203 uint16_t fw_ddb_index; /* DDB firmware index */
204 uint8_t reserved[2];
205 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
206
207 uint32_t CmdSn;
208 uint16_t target_session_id;
209 uint16_t connection_id;
210 uint16_t exe_throttle; /* Max mumber of cmds outstanding
211 * simultaneously */
212 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
213 * complete */
214 uint16_t default_relogin_timeout; /* Max time to wait for
215 * relogin to complete */
216 uint16_t tcp_source_port_num;
217 uint32_t default_time2wait; /* Default Min time between
218 * relogins (+aens) */
219
220 atomic_t port_down_timer; /* Device connection timer */
221 atomic_t retry_relogin_timer; /* Min Time between relogins
222 * (4000 only) */
223 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
224 atomic_t relogin_retry_count; /* Num of times relogin has been
225 * retried */
226
227 uint16_t port;
228 uint32_t tpgt;
229 uint8_t ip_addr[ISCSI_IPADDR_SIZE];
230 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
231 uint8_t iscsi_alias[0x20];
232};
233
234/*
235 * DDB states.
236 */
237#define DDB_STATE_DEAD 0 /* We can no longer talk to
238 * this device */
239#define DDB_STATE_ONLINE 1 /* Device ready to accept
240 * commands */
241#define DDB_STATE_MISSING 2 /* Device logged off, trying
242 * to re-login */
243
244/*
245 * DDB flags.
246 */
247#define DF_RELOGIN 0 /* Relogin to device */
248#define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL
249 * logged it out */
250#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
251#define DF_FO_MASKED 3
252
253/*
254 * Asynchronous Event Queue structure
255 */
256struct aen {
257 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
258};
259
260
261#include "ql4_fw.h"
262#include "ql4_nvram.h"
263
264/*
265 * Linux Host Adapter structure
266 */
267struct scsi_qla_host {
268 /* Linux adapter configuration data */
269 struct Scsi_Host *host; /* pointer to host data */
270 uint32_t tot_ddbs;
271 unsigned long flags;
272
273#define AF_ONLINE 0 /* 0x00000001 */
274#define AF_INIT_DONE 1 /* 0x00000002 */
275#define AF_MBOX_COMMAND 2 /* 0x00000004 */
276#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
277#define AF_INTERRUPTS_ON 6 /* 0x00000040 Not Used */
278#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
279#define AF_LINK_UP 8 /* 0x00000100 */
280#define AF_TOPCAT_CHIP_PRESENT 9 /* 0x00000200 */
281#define AF_IRQ_ATTACHED 10 /* 0x00000400 */
282#define AF_ISNS_CMD_IN_PROCESS 12 /* 0x00001000 */
283#define AF_ISNS_CMD_DONE 13 /* 0x00002000 */
284
285 unsigned long dpc_flags;
286
287#define DPC_RESET_HA 1 /* 0x00000002 */
288#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
289#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
290#define DPC_RESET_HA_DESTROY_DDB_LIST 4 /* 0x00000010 */
291#define DPC_RESET_HA_INTR 5 /* 0x00000020 */
292#define DPC_ISNS_RESTART 7 /* 0x00000080 */
293#define DPC_AEN 9 /* 0x00000200 */
294#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
295
296 uint16_t iocb_cnt;
297 uint16_t iocb_hiwat;
298
299 /* SRB cache. */
300#define SRB_MIN_REQ 128
301 mempool_t *srb_mempool;
302
303 /* pci information */
304 struct pci_dev *pdev;
305
306 struct isp_reg __iomem *reg; /* Base I/O address */
307 unsigned long pio_address;
308 unsigned long pio_length;
309#define MIN_IOBASE_LEN 0x100
310
311 uint16_t req_q_count;
312 uint8_t marker_needed;
313 uint8_t rsvd1;
314
315 unsigned long host_no;
316
317 /* NVRAM registers */
318 struct eeprom_data *nvram;
319 spinlock_t hardware_lock ____cacheline_aligned;
320 spinlock_t list_lock;
321 uint32_t eeprom_cmd_data;
322
323 /* Counters for general statistics */
324 uint64_t adapter_error_count;
325 uint64_t device_error_count;
326 uint64_t total_io_count;
327 uint64_t total_mbytes_xferred;
328 uint64_t link_failure_count;
329 uint64_t invalid_crc_count;
330 uint32_t spurious_int_count;
331 uint32_t aborted_io_count;
332 uint32_t io_timeout_count;
333 uint32_t mailbox_timeout_count;
334 uint32_t seconds_since_last_intr;
335 uint32_t seconds_since_last_heartbeat;
336 uint32_t mac_index;
337
338 /* Info Needed for Management App */
339 /* --- From GetFwVersion --- */
340 uint32_t firmware_version[2];
341 uint32_t patch_number;
342 uint32_t build_number;
343
344 /* --- From Init_FW --- */
345 /* init_cb_t *init_cb; */
346 uint16_t firmware_options;
347 uint16_t tcp_options;
348 uint8_t ip_address[IP_ADDR_LEN];
349 uint8_t subnet_mask[IP_ADDR_LEN];
350 uint8_t gateway[IP_ADDR_LEN];
351 uint8_t alias[32];
352 uint8_t name_string[256];
353 uint8_t heartbeat_interval;
354 uint8_t rsvd;
355
356 /* --- From FlashSysInfo --- */
357 uint8_t my_mac[MAC_ADDR_LEN];
358 uint8_t serial_number[16];
359
360 /* --- From GetFwState --- */
361 uint32_t firmware_state;
362 uint32_t board_id;
363 uint32_t addl_fw_state;
364
365 /* Linux kernel thread */
366 struct workqueue_struct *dpc_thread;
367 struct work_struct dpc_work;
368
369 /* Linux timer thread */
370 struct timer_list timer;
371 uint32_t timer_active;
372
373 /* Recovery Timers */
374 uint32_t port_down_retry_count;
375 uint32_t discovery_wait;
376 atomic_t check_relogin_timeouts;
377 uint32_t retry_reset_ha_cnt;
378 uint32_t isp_reset_timer; /* reset test timer */
379 uint32_t nic_reset_timer; /* simulated nic reset test timer */
380 int eh_start;
381 struct list_head free_srb_q;
382 uint16_t free_srb_q_count;
383 uint16_t num_srbs_allocated;
384
385 /* DMA Memory Block */
386 void *queues;
387 dma_addr_t queues_dma;
388 unsigned long queues_len;
389
390#define MEM_ALIGN_VALUE \
391 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
392 sizeof(struct queue_entry))
393 /* request and response queue variables */
394 dma_addr_t request_dma;
395 struct queue_entry *request_ring;
396 struct queue_entry *request_ptr;
397 dma_addr_t response_dma;
398 struct queue_entry *response_ring;
399 struct queue_entry *response_ptr;
400 dma_addr_t shadow_regs_dma;
401 struct shadow_regs *shadow_regs;
402 uint16_t request_in; /* Current indexes. */
403 uint16_t request_out;
404 uint16_t response_in;
405 uint16_t response_out;
406
407 /* aen queue variables */
408 uint16_t aen_q_count; /* Number of available aen_q entries */
409 uint16_t aen_in; /* Current indexes */
410 uint16_t aen_out;
411 struct aen aen_q[MAX_AEN_ENTRIES];
412
413 /* This mutex protects several threads to do mailbox commands
414 * concurrently.
415 */
416 struct mutex mbox_sem;
417 wait_queue_head_t mailbox_wait_queue;
418
419 /* temporary mailbox status registers */
420 volatile uint8_t mbox_status_count;
421 volatile uint32_t mbox_status[MBOX_REG_COUNT];
422
423 /* local device database list (contains internal ddb entries) */
424 struct list_head ddb_list;
425
426 /* Map ddb_list entry by FW ddb index */
427 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
428
429};
430
431static inline int is_qla4010(struct scsi_qla_host *ha)
432{
433 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
434}
435
436static inline int is_qla4022(struct scsi_qla_host *ha)
437{
438 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
439}
440
441static inline int adapter_up(struct scsi_qla_host *ha)
442{
443 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
444 (test_bit(AF_LINK_UP, &ha->flags) != 0);
445}
446
447static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
448{
449 return (struct scsi_qla_host *)shost->hostdata;
450}
451
452static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
453{
454 return (is_qla4022(ha) ?
455 &ha->reg->u1.isp4022.semaphore :
456 &ha->reg->u1.isp4010.nvram);
457}
458
459static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
460{
461 return (is_qla4022(ha) ?
462 &ha->reg->u1.isp4022.nvram :
463 &ha->reg->u1.isp4010.nvram);
464}
465
466static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
467{
468 return (is_qla4022(ha) ?
469 &ha->reg->u2.isp4022.p0.ext_hw_conf :
470 &ha->reg->u2.isp4010.ext_hw_conf);
471}
472
473static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
474{
475 return (is_qla4022(ha) ?
476 &ha->reg->u2.isp4022.p0.port_status :
477 &ha->reg->u2.isp4010.port_status);
478}
479
480static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
481{
482 return (is_qla4022(ha) ?
483 &ha->reg->u2.isp4022.p0.port_ctrl :
484 &ha->reg->u2.isp4010.port_ctrl);
485}
486
487static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
488{
489 return (is_qla4022(ha) ?
490 &ha->reg->u2.isp4022.p0.port_err_status :
491 &ha->reg->u2.isp4010.port_err_status);
492}
493
494static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
495{
496 return (is_qla4022(ha) ?
497 &ha->reg->u2.isp4022.p0.gp_out :
498 &ha->reg->u2.isp4010.gp_out);
499}
500
501static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
502{
503 return (is_qla4022(ha) ?
504 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2 :
505 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2);
506}
507
508int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
509void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
510int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
511
512static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
513{
514 if (is_qla4022(a))
515 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
516 (QL4022_RESOURCE_BITS_BASE_CODE |
517 (a->mac_index)) << 13);
518 else
519 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
520 QL4010_FLASH_SEM_BITS);
521}
522
523static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
524{
525 if (is_qla4022(a))
526 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
527 else
528 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
529}
530
531static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
532{
533 if (is_qla4022(a))
534 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
535 (QL4022_RESOURCE_BITS_BASE_CODE |
536 (a->mac_index)) << 10);
537 else
538 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
539 QL4010_NVRAM_SEM_BITS);
540}
541
542static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
543{
544 if (is_qla4022(a))
545 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
546 else
547 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
548}
549
550static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
551{
552 if (is_qla4022(a))
553 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
554 (QL4022_RESOURCE_BITS_BASE_CODE |
555 (a->mac_index)) << 1);
556 else
557 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
558 QL4010_DRVR_SEM_BITS);
559}
560
561static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
562{
563 if (is_qla4022(a))
564 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
565 else
566 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
567}
568
569/*---------------------------------------------------------------------------*/
570
571/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
572#define PRESERVE_DDB_LIST 0
573#define REBUILD_DDB_LIST 1
574
575/* Defines for process_aen() */
576#define PROCESS_ALL_AENS 0
577#define FLUSH_DDB_CHANGED_AENS 1
578#define RELOGIN_DDB_CHANGED_AENS 2
579
580#include "ql4_version.h"
581#include "ql4_glbl.h"
582#include "ql4_dbg.h"
583#include "ql4_inline.h"
584
585
586#endif /*_QLA4XXX_H */
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