diff options
author | David C Somayajulu <david.somayajulu@qlogic.com> | 2006-11-15 20:38:40 -0500 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-11-22 13:14:04 -0500 |
commit | d915058f48745c0d5c4582566e5aa63867264f81 (patch) | |
tree | edd78540aa84440dbbf438968a3be6303f81a33d /drivers/scsi/qla4xxx/ql4_def.h | |
parent | 0bd2af46839ad6262d25714a6ec0365db9d6b98f (diff) |
[SCSI] qla4xxx: add support for qla4032
This patch provides the following:
1. adds support for the next version of Qlogic's iSCSI HBA, qla4032
(PCI Device ID 4032).
2. removes dead code related to topcat chip and renames
qla4010_soft_reset to qla4xxx_soft_reset (minor changes).
Signed-off-by: David Somayajulu <david.somayajulu@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_def.h')
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_def.h | 105 |
1 files changed, 57 insertions, 48 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_def.h b/drivers/scsi/qla4xxx/ql4_def.h index a7f6c7b1c590..4249e52a5592 100644 --- a/drivers/scsi/qla4xxx/ql4_def.h +++ b/drivers/scsi/qla4xxx/ql4_def.h | |||
@@ -40,7 +40,11 @@ | |||
40 | 40 | ||
41 | #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 | 41 | #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 |
42 | #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 | 42 | #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 |
43 | #endif /* */ | 43 | #endif |
44 | |||
45 | #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 | ||
46 | #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 | ||
47 | #endif | ||
44 | 48 | ||
45 | #define QLA_SUCCESS 0 | 49 | #define QLA_SUCCESS 0 |
46 | #define QLA_ERROR 1 | 50 | #define QLA_ERROR 1 |
@@ -277,7 +281,6 @@ struct scsi_qla_host { | |||
277 | #define AF_INTERRUPTS_ON 6 /* 0x00000040 Not Used */ | 281 | #define AF_INTERRUPTS_ON 6 /* 0x00000040 Not Used */ |
278 | #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ | 282 | #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ |
279 | #define AF_LINK_UP 8 /* 0x00000100 */ | 283 | #define AF_LINK_UP 8 /* 0x00000100 */ |
280 | #define AF_TOPCAT_CHIP_PRESENT 9 /* 0x00000200 */ | ||
281 | #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ | 284 | #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ |
282 | #define AF_ISNS_CMD_IN_PROCESS 12 /* 0x00001000 */ | 285 | #define AF_ISNS_CMD_IN_PROCESS 12 /* 0x00001000 */ |
283 | #define AF_ISNS_CMD_DONE 13 /* 0x00002000 */ | 286 | #define AF_ISNS_CMD_DONE 13 /* 0x00002000 */ |
@@ -317,16 +320,17 @@ struct scsi_qla_host { | |||
317 | /* NVRAM registers */ | 320 | /* NVRAM registers */ |
318 | struct eeprom_data *nvram; | 321 | struct eeprom_data *nvram; |
319 | spinlock_t hardware_lock ____cacheline_aligned; | 322 | spinlock_t hardware_lock ____cacheline_aligned; |
320 | spinlock_t list_lock; | ||
321 | uint32_t eeprom_cmd_data; | 323 | uint32_t eeprom_cmd_data; |
322 | 324 | ||
323 | /* Counters for general statistics */ | 325 | /* Counters for general statistics */ |
326 | uint64_t isr_count; | ||
324 | uint64_t adapter_error_count; | 327 | uint64_t adapter_error_count; |
325 | uint64_t device_error_count; | 328 | uint64_t device_error_count; |
326 | uint64_t total_io_count; | 329 | uint64_t total_io_count; |
327 | uint64_t total_mbytes_xferred; | 330 | uint64_t total_mbytes_xferred; |
328 | uint64_t link_failure_count; | 331 | uint64_t link_failure_count; |
329 | uint64_t invalid_crc_count; | 332 | uint64_t invalid_crc_count; |
333 | uint32_t bytes_xfered; | ||
330 | uint32_t spurious_int_count; | 334 | uint32_t spurious_int_count; |
331 | uint32_t aborted_io_count; | 335 | uint32_t aborted_io_count; |
332 | uint32_t io_timeout_count; | 336 | uint32_t io_timeout_count; |
@@ -438,6 +442,11 @@ static inline int is_qla4022(struct scsi_qla_host *ha) | |||
438 | return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; | 442 | return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; |
439 | } | 443 | } |
440 | 444 | ||
445 | static inline int is_qla4032(struct scsi_qla_host *ha) | ||
446 | { | ||
447 | return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; | ||
448 | } | ||
449 | |||
441 | static inline int adapter_up(struct scsi_qla_host *ha) | 450 | static inline int adapter_up(struct scsi_qla_host *ha) |
442 | { | 451 | { |
443 | return (test_bit(AF_ONLINE, &ha->flags) != 0) && | 452 | return (test_bit(AF_ONLINE, &ha->flags) != 0) && |
@@ -451,58 +460,58 @@ static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) | |||
451 | 460 | ||
452 | static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) | 461 | static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) |
453 | { | 462 | { |
454 | return (is_qla4022(ha) ? | 463 | return (is_qla4010(ha) ? |
455 | &ha->reg->u1.isp4022.semaphore : | 464 | &ha->reg->u1.isp4010.nvram : |
456 | &ha->reg->u1.isp4010.nvram); | 465 | &ha->reg->u1.isp4022.semaphore); |
457 | } | 466 | } |
458 | 467 | ||
459 | static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) | 468 | static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) |
460 | { | 469 | { |
461 | return (is_qla4022(ha) ? | 470 | return (is_qla4010(ha) ? |
462 | &ha->reg->u1.isp4022.nvram : | 471 | &ha->reg->u1.isp4010.nvram : |
463 | &ha->reg->u1.isp4010.nvram); | 472 | &ha->reg->u1.isp4022.nvram); |
464 | } | 473 | } |
465 | 474 | ||
466 | static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) | 475 | static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) |
467 | { | 476 | { |
468 | return (is_qla4022(ha) ? | 477 | return (is_qla4010(ha) ? |
469 | &ha->reg->u2.isp4022.p0.ext_hw_conf : | 478 | &ha->reg->u2.isp4010.ext_hw_conf : |
470 | &ha->reg->u2.isp4010.ext_hw_conf); | 479 | &ha->reg->u2.isp4022.p0.ext_hw_conf); |
471 | } | 480 | } |
472 | 481 | ||
473 | static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) | 482 | static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) |
474 | { | 483 | { |
475 | return (is_qla4022(ha) ? | 484 | return (is_qla4010(ha) ? |
476 | &ha->reg->u2.isp4022.p0.port_status : | 485 | &ha->reg->u2.isp4010.port_status : |
477 | &ha->reg->u2.isp4010.port_status); | 486 | &ha->reg->u2.isp4022.p0.port_status); |
478 | } | 487 | } |
479 | 488 | ||
480 | static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) | 489 | static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) |
481 | { | 490 | { |
482 | return (is_qla4022(ha) ? | 491 | return (is_qla4010(ha) ? |
483 | &ha->reg->u2.isp4022.p0.port_ctrl : | 492 | &ha->reg->u2.isp4010.port_ctrl : |
484 | &ha->reg->u2.isp4010.port_ctrl); | 493 | &ha->reg->u2.isp4022.p0.port_ctrl); |
485 | } | 494 | } |
486 | 495 | ||
487 | static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) | 496 | static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) |
488 | { | 497 | { |
489 | return (is_qla4022(ha) ? | 498 | return (is_qla4010(ha) ? |
490 | &ha->reg->u2.isp4022.p0.port_err_status : | 499 | &ha->reg->u2.isp4010.port_err_status : |
491 | &ha->reg->u2.isp4010.port_err_status); | 500 | &ha->reg->u2.isp4022.p0.port_err_status); |
492 | } | 501 | } |
493 | 502 | ||
494 | static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) | 503 | static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) |
495 | { | 504 | { |
496 | return (is_qla4022(ha) ? | 505 | return (is_qla4010(ha) ? |
497 | &ha->reg->u2.isp4022.p0.gp_out : | 506 | &ha->reg->u2.isp4010.gp_out : |
498 | &ha->reg->u2.isp4010.gp_out); | 507 | &ha->reg->u2.isp4022.p0.gp_out); |
499 | } | 508 | } |
500 | 509 | ||
501 | static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) | 510 | static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) |
502 | { | 511 | { |
503 | return (is_qla4022(ha) ? | 512 | return (is_qla4010(ha) ? |
504 | offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2 : | 513 | offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : |
505 | offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2); | 514 | offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); |
506 | } | 515 | } |
507 | 516 | ||
508 | int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); | 517 | int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); |
@@ -511,59 +520,59 @@ int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); | |||
511 | 520 | ||
512 | static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) | 521 | static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) |
513 | { | 522 | { |
514 | if (is_qla4022(a)) | 523 | if (is_qla4010(a)) |
524 | return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, | ||
525 | QL4010_FLASH_SEM_BITS); | ||
526 | else | ||
515 | return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, | 527 | return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, |
516 | (QL4022_RESOURCE_BITS_BASE_CODE | | 528 | (QL4022_RESOURCE_BITS_BASE_CODE | |
517 | (a->mac_index)) << 13); | 529 | (a->mac_index)) << 13); |
518 | else | ||
519 | return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, | ||
520 | QL4010_FLASH_SEM_BITS); | ||
521 | } | 530 | } |
522 | 531 | ||
523 | static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) | 532 | static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) |
524 | { | 533 | { |
525 | if (is_qla4022(a)) | 534 | if (is_qla4010(a)) |
526 | ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); | ||
527 | else | ||
528 | ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); | 535 | ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); |
536 | else | ||
537 | ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); | ||
529 | } | 538 | } |
530 | 539 | ||
531 | static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) | 540 | static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) |
532 | { | 541 | { |
533 | if (is_qla4022(a)) | 542 | if (is_qla4010(a)) |
543 | return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, | ||
544 | QL4010_NVRAM_SEM_BITS); | ||
545 | else | ||
534 | return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, | 546 | return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, |
535 | (QL4022_RESOURCE_BITS_BASE_CODE | | 547 | (QL4022_RESOURCE_BITS_BASE_CODE | |
536 | (a->mac_index)) << 10); | 548 | (a->mac_index)) << 10); |
537 | else | ||
538 | return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, | ||
539 | QL4010_NVRAM_SEM_BITS); | ||
540 | } | 549 | } |
541 | 550 | ||
542 | static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) | 551 | static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) |
543 | { | 552 | { |
544 | if (is_qla4022(a)) | 553 | if (is_qla4010(a)) |
545 | ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); | ||
546 | else | ||
547 | ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); | 554 | ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); |
555 | else | ||
556 | ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); | ||
548 | } | 557 | } |
549 | 558 | ||
550 | static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) | 559 | static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) |
551 | { | 560 | { |
552 | if (is_qla4022(a)) | 561 | if (is_qla4010(a)) |
562 | return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, | ||
563 | QL4010_DRVR_SEM_BITS); | ||
564 | else | ||
553 | return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, | 565 | return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, |
554 | (QL4022_RESOURCE_BITS_BASE_CODE | | 566 | (QL4022_RESOURCE_BITS_BASE_CODE | |
555 | (a->mac_index)) << 1); | 567 | (a->mac_index)) << 1); |
556 | else | ||
557 | return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, | ||
558 | QL4010_DRVR_SEM_BITS); | ||
559 | } | 568 | } |
560 | 569 | ||
561 | static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) | 570 | static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) |
562 | { | 571 | { |
563 | if (is_qla4022(a)) | 572 | if (is_qla4010(a)) |
564 | ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); | ||
565 | else | ||
566 | ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); | 573 | ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); |
574 | else | ||
575 | ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); | ||
567 | } | 576 | } |
568 | 577 | ||
569 | /*---------------------------------------------------------------------------*/ | 578 | /*---------------------------------------------------------------------------*/ |