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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2006-06-23 19:10:29 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-06-26 17:20:44 -0400
commita7a167bf7e2d196fc33f292e7b02e90fee03bc9a (patch)
tree1e62085065440e012a7cd2d48cd161bfac408adc /drivers/scsi/qla2xxx
parent9ea7290902abcf22f796e9aeae4dc2e71d3f7e67 (diff)
[SCSI] qla2xxx: Rework firmware-trace facilities.
- Defer firmware dump-data raw-to-textual conversion to user-space. - Add module parameter (ql2xallocfwdump) to allow for per-HBA allocations of firmware dump memory. - Dump request and response queue data as per firmware group request. - Add extended firmware trace support for ISP24XX/ISP54XX chips. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla2xxx')
-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c53
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c925
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.h41
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h12
-rw-r--r--drivers/scsi/qla2xxx/qla_gbl.h9
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c104
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c42
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c26
8 files changed, 401 insertions, 811 deletions
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index e96d58ded57c..78eec6799343 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -16,15 +16,16 @@ qla2x00_sysfs_read_fw_dump(struct kobject *kobj, char *buf, loff_t off,
16{ 16{
17 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj, 17 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
18 struct device, kobj))); 18 struct device, kobj)));
19 char *rbuf = (char *)ha->fw_dump;
19 20
20 if (ha->fw_dump_reading == 0) 21 if (ha->fw_dump_reading == 0)
21 return 0; 22 return 0;
22 if (off > ha->fw_dump_buffer_len) 23 if (off > ha->fw_dump_len)
23 return 0; 24 return 0;
24 if (off + count > ha->fw_dump_buffer_len) 25 if (off + count > ha->fw_dump_len)
25 count = ha->fw_dump_buffer_len - off; 26 count = ha->fw_dump_len - off;
26 27
27 memcpy(buf, &ha->fw_dump_buffer[off], count); 28 memcpy(buf, &rbuf[off], count);
28 29
29 return (count); 30 return (count);
30} 31}
@@ -36,7 +37,6 @@ qla2x00_sysfs_write_fw_dump(struct kobject *kobj, char *buf, loff_t off,
36 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj, 37 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
37 struct device, kobj))); 38 struct device, kobj)));
38 int reading; 39 int reading;
39 uint32_t dump_size;
40 40
41 if (off != 0) 41 if (off != 0)
42 return (0); 42 return (0);
@@ -44,46 +44,27 @@ qla2x00_sysfs_write_fw_dump(struct kobject *kobj, char *buf, loff_t off,
44 reading = simple_strtol(buf, NULL, 10); 44 reading = simple_strtol(buf, NULL, 10);
45 switch (reading) { 45 switch (reading) {
46 case 0: 46 case 0:
47 if (ha->fw_dump_reading == 1) { 47 if (!ha->fw_dump_reading)
48 qla_printk(KERN_INFO, ha, 48 break;
49 "Firmware dump cleared on (%ld).\n", ha->host_no);
50 49
51 vfree(ha->fw_dump_buffer); 50 qla_printk(KERN_INFO, ha,
52 ha->fw_dump_buffer = NULL; 51 "Firmware dump cleared on (%ld).\n", ha->host_no);
53 ha->fw_dump_reading = 0; 52
54 ha->fw_dumped = 0; 53 ha->fw_dump_reading = 0;
55 } 54 ha->fw_dumped = 0;
56 break; 55 break;
57 case 1: 56 case 1:
58 if (ha->fw_dumped && !ha->fw_dump_reading) { 57 if (ha->fw_dumped && !ha->fw_dump_reading) {
59 ha->fw_dump_reading = 1; 58 ha->fw_dump_reading = 1;
60 59
61 if (IS_QLA24XX(ha) || IS_QLA54XX(ha))
62 dump_size = FW_DUMP_SIZE_24XX;
63 else {
64 dump_size = FW_DUMP_SIZE_1M;
65 if (ha->fw_memory_size < 0x20000)
66 dump_size = FW_DUMP_SIZE_128K;
67 else if (ha->fw_memory_size < 0x80000)
68 dump_size = FW_DUMP_SIZE_512K;
69 }
70 ha->fw_dump_buffer = (char *)vmalloc(dump_size);
71 if (ha->fw_dump_buffer == NULL) {
72 qla_printk(KERN_WARNING, ha,
73 "Unable to allocate memory for firmware "
74 "dump buffer (%d).\n", dump_size);
75
76 ha->fw_dump_reading = 0;
77 return (count);
78 }
79 qla_printk(KERN_INFO, ha, 60 qla_printk(KERN_INFO, ha,
80 "Firmware dump ready for read on (%ld).\n", 61 "Raw firmware dump ready for read on (%ld).\n",
81 ha->host_no); 62 ha->host_no);
82 memset(ha->fw_dump_buffer, 0, dump_size);
83 ha->isp_ops.ascii_fw_dump(ha);
84 ha->fw_dump_buffer_len = strlen(ha->fw_dump_buffer);
85 } 63 }
86 break; 64 break;
65 case 2:
66 qla2x00_alloc_fw_dump(ha);
67 break;
87 } 68 }
88 return (count); 69 return (count);
89} 70}
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 74e54713aa7c..f6ed6962bc2b 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -8,7 +8,34 @@
8 8
9#include <linux/delay.h> 9#include <linux/delay.h>
10 10
11static int qla_uprintf(char **, char *, ...); 11static inline void
12qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump)
13{
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23}
24
25static inline void *
26qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
27{
28 /* Request queue. */
29 memcpy(ptr, ha->request_ring, ha->request_q_length *
30 sizeof(request_t));
31
32 /* Response queue. */
33 ptr += ha->request_q_length * sizeof(request_t);
34 memcpy(ptr, ha->response_ring, ha->response_q_length *
35 sizeof(response_t));
36
37 return ptr + (ha->response_q_length * sizeof(response_t));
38}
12 39
13/** 40/**
14 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 41 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
@@ -49,10 +76,11 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
49 "request...\n", ha->fw_dump); 76 "request...\n", ha->fw_dump);
50 goto qla2300_fw_dump_failed; 77 goto qla2300_fw_dump_failed;
51 } 78 }
52 fw = ha->fw_dump; 79 fw = &ha->fw_dump->isp.isp23;
80 qla2xxx_prep_dump(ha, ha->fw_dump);
53 81
54 rval = QLA_SUCCESS; 82 rval = QLA_SUCCESS;
55 fw->hccr = RD_REG_WORD(&reg->hccr); 83 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
56 84
57 /* Pause RISC. */ 85 /* Pause RISC. */
58 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 86 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
@@ -73,85 +101,86 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
73 if (rval == QLA_SUCCESS) { 101 if (rval == QLA_SUCCESS) {
74 dmp_reg = (uint16_t __iomem *)(reg + 0); 102 dmp_reg = (uint16_t __iomem *)(reg + 0);
75 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 103 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
76 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); 104 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
77 105
78 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 106 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
79 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 107 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
80 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++); 108 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
81 109
82 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40); 110 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
83 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 111 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
84 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); 112 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
85 113
86 WRT_REG_WORD(&reg->ctrl_status, 0x40); 114 WRT_REG_WORD(&reg->ctrl_status, 0x40);
87 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 115 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
88 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) 116 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
89 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 117 fw->resp_dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
90 118
91 WRT_REG_WORD(&reg->ctrl_status, 0x50); 119 WRT_REG_WORD(&reg->ctrl_status, 0x50);
92 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 120 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
93 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 121 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
94 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 122 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
95 123
96 WRT_REG_WORD(&reg->ctrl_status, 0x00); 124 WRT_REG_WORD(&reg->ctrl_status, 0x00);
97 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 125 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
98 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 126 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
99 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 127 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
100 128
101 WRT_REG_WORD(&reg->pcr, 0x2000); 129 WRT_REG_WORD(&reg->pcr, 0x2000);
102 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 130 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
103 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 131 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
104 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); 132 fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
105 133
106 WRT_REG_WORD(&reg->pcr, 0x2200); 134 WRT_REG_WORD(&reg->pcr, 0x2200);
107 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 135 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
108 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 136 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
109 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); 137 fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
110 138
111 WRT_REG_WORD(&reg->pcr, 0x2400); 139 WRT_REG_WORD(&reg->pcr, 0x2400);
112 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 140 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
113 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 141 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
114 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); 142 fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
115 143
116 WRT_REG_WORD(&reg->pcr, 0x2600); 144 WRT_REG_WORD(&reg->pcr, 0x2600);
117 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 145 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
118 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 146 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
119 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); 147 fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
120 148
121 WRT_REG_WORD(&reg->pcr, 0x2800); 149 WRT_REG_WORD(&reg->pcr, 0x2800);
122 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 150 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
123 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 151 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
124 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); 152 fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
125 153
126 WRT_REG_WORD(&reg->pcr, 0x2A00); 154 WRT_REG_WORD(&reg->pcr, 0x2A00);
127 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 155 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
128 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 156 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
129 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); 157 fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
130 158
131 WRT_REG_WORD(&reg->pcr, 0x2C00); 159 WRT_REG_WORD(&reg->pcr, 0x2C00);
132 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 160 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
133 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 161 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
134 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); 162 fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
135 163
136 WRT_REG_WORD(&reg->pcr, 0x2E00); 164 WRT_REG_WORD(&reg->pcr, 0x2E00);
137 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 165 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
138 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 166 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
139 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); 167 fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
140 168
141 WRT_REG_WORD(&reg->ctrl_status, 0x10); 169 WRT_REG_WORD(&reg->ctrl_status, 0x10);
142 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 170 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
143 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 171 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
144 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 172 fw->frame_buf_hdw_reg[cnt] =
173 htons(RD_REG_WORD(dmp_reg++));
145 174
146 WRT_REG_WORD(&reg->ctrl_status, 0x20); 175 WRT_REG_WORD(&reg->ctrl_status, 0x20);
147 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 176 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
148 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 177 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
149 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); 178 fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
150 179
151 WRT_REG_WORD(&reg->ctrl_status, 0x30); 180 WRT_REG_WORD(&reg->ctrl_status, 0x30);
152 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 181 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
153 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 182 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
154 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); 183 fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
155 184
156 /* Reset RISC. */ 185 /* Reset RISC. */
157 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); 186 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
@@ -226,7 +255,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
226 255
227 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 256 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
228 rval = mb0 & MBS_MASK; 257 rval = mb0 & MBS_MASK;
229 fw->risc_ram[cnt] = mb2; 258 fw->risc_ram[cnt] = htons(mb2);
230 } else { 259 } else {
231 rval = QLA_FUNCTION_FAILED; 260 rval = QLA_FUNCTION_FAILED;
232 } 261 }
@@ -285,7 +314,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
285 314
286 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 315 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
287 rval = mb0 & MBS_MASK; 316 rval = mb0 & MBS_MASK;
288 fw->stack_ram[cnt] = mb2; 317 fw->stack_ram[cnt] = htons(mb2);
289 } else { 318 } else {
290 rval = QLA_FUNCTION_FAILED; 319 rval = QLA_FUNCTION_FAILED;
291 } 320 }
@@ -345,12 +374,15 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
345 374
346 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 375 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
347 rval = mb0 & MBS_MASK; 376 rval = mb0 & MBS_MASK;
348 fw->data_ram[cnt] = mb2; 377 fw->data_ram[cnt] = htons(mb2);
349 } else { 378 } else {
350 rval = QLA_FUNCTION_FAILED; 379 rval = QLA_FUNCTION_FAILED;
351 } 380 }
352 } 381 }
353 382
383 if (rval == QLA_SUCCESS)
384 qla2xxx_copy_queues(ha, &fw->data_ram[cnt]);
385
354 if (rval != QLA_SUCCESS) { 386 if (rval != QLA_SUCCESS) {
355 qla_printk(KERN_WARNING, ha, 387 qla_printk(KERN_WARNING, ha,
356 "Failed to dump firmware (%x)!!!\n", rval); 388 "Failed to dump firmware (%x)!!!\n", rval);
@@ -369,193 +401,6 @@ qla2300_fw_dump_failed:
369} 401}
370 402
371/** 403/**
372 * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
373 * @ha: HA context
374 */
375void
376qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
377{
378 uint32_t cnt;
379 char *uiter;
380 char fw_info[30];
381 struct qla2300_fw_dump *fw;
382 uint32_t data_ram_cnt;
383
384 uiter = ha->fw_dump_buffer;
385 fw = ha->fw_dump;
386
387 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
388 ha->isp_ops.fw_version_str(ha, fw_info));
389
390 qla_uprintf(&uiter, "\n[==>BEG]\n");
391
392 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
393
394 qla_uprintf(&uiter, "PBIU Registers:");
395 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
396 if (cnt % 8 == 0) {
397 qla_uprintf(&uiter, "\n");
398 }
399 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
400 }
401
402 qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
403 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
404 if (cnt % 8 == 0) {
405 qla_uprintf(&uiter, "\n");
406 }
407 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
408 }
409
410 qla_uprintf(&uiter, "\n\nMailbox Registers:");
411 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
412 if (cnt % 8 == 0) {
413 qla_uprintf(&uiter, "\n");
414 }
415 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
416 }
417
418 qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
419 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
420 if (cnt % 8 == 0) {
421 qla_uprintf(&uiter, "\n");
422 }
423 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
424 }
425
426 qla_uprintf(&uiter, "\n\nDMA Registers:");
427 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
428 if (cnt % 8 == 0) {
429 qla_uprintf(&uiter, "\n");
430 }
431 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
432 }
433
434 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
435 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
436 if (cnt % 8 == 0) {
437 qla_uprintf(&uiter, "\n");
438 }
439 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
440 }
441
442 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
443 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
444 if (cnt % 8 == 0) {
445 qla_uprintf(&uiter, "\n");
446 }
447 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
448 }
449
450 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
451 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
452 if (cnt % 8 == 0) {
453 qla_uprintf(&uiter, "\n");
454 }
455 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
456 }
457
458 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
459 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
460 if (cnt % 8 == 0) {
461 qla_uprintf(&uiter, "\n");
462 }
463 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
464 }
465
466 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
467 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
468 if (cnt % 8 == 0) {
469 qla_uprintf(&uiter, "\n");
470 }
471 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
472 }
473
474 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
475 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
476 if (cnt % 8 == 0) {
477 qla_uprintf(&uiter, "\n");
478 }
479 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
480 }
481
482 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
483 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
484 if (cnt % 8 == 0) {
485 qla_uprintf(&uiter, "\n");
486 }
487 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
488 }
489
490 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
491 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
492 if (cnt % 8 == 0) {
493 qla_uprintf(&uiter, "\n");
494 }
495 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
496 }
497
498 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
499 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
500 if (cnt % 8 == 0) {
501 qla_uprintf(&uiter, "\n");
502 }
503 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
504 }
505
506 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
507 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
508 if (cnt % 8 == 0) {
509 qla_uprintf(&uiter, "\n");
510 }
511 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
512 }
513
514 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
515 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
516 if (cnt % 8 == 0) {
517 qla_uprintf(&uiter, "\n");
518 }
519 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
520 }
521
522 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
523 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
524 if (cnt % 8 == 0) {
525 qla_uprintf(&uiter, "\n");
526 }
527 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
528 }
529
530 qla_uprintf(&uiter, "\n\nCode RAM Dump:");
531 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
532 if (cnt % 8 == 0) {
533 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
534 }
535 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
536 }
537
538 qla_uprintf(&uiter, "\n\nStack RAM Dump:");
539 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
540 if (cnt % 8 == 0) {
541 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
542 }
543 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
544 }
545
546 qla_uprintf(&uiter, "\n\nData RAM Dump:");
547 data_ram_cnt = ha->fw_memory_size - 0x11000 + 1;
548 for (cnt = 0; cnt < data_ram_cnt; cnt++) {
549 if (cnt % 8 == 0) {
550 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
551 }
552 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
553 }
554
555 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
556}
557
558/**
559 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 404 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
560 * @ha: HA context 405 * @ha: HA context
561 * @hardware_locked: Called with the hardware_lock 406 * @hardware_locked: Called with the hardware_lock
@@ -591,10 +436,11 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
591 "request...\n", ha->fw_dump); 436 "request...\n", ha->fw_dump);
592 goto qla2100_fw_dump_failed; 437 goto qla2100_fw_dump_failed;
593 } 438 }
594 fw = ha->fw_dump; 439 fw = &ha->fw_dump->isp.isp21;
440 qla2xxx_prep_dump(ha, ha->fw_dump);
595 441
596 rval = QLA_SUCCESS; 442 rval = QLA_SUCCESS;
597 fw->hccr = RD_REG_WORD(&reg->hccr); 443 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
598 444
599 /* Pause RISC. */ 445 /* Pause RISC. */
600 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 446 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
@@ -608,79 +454,81 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
608 if (rval == QLA_SUCCESS) { 454 if (rval == QLA_SUCCESS) {
609 dmp_reg = (uint16_t __iomem *)(reg + 0); 455 dmp_reg = (uint16_t __iomem *)(reg + 0);
610 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 456 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
611 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); 457 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
612 458
613 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 459 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
614 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 460 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
615 if (cnt == 8) { 461 if (cnt == 8) {
616 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xe0); 462 dmp_reg = (uint16_t __iomem *)
463 ((uint8_t __iomem *)reg + 0xe0);
617 } 464 }
618 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); 465 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
619 } 466 }
620 467
621 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20); 468 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
622 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 469 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
623 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 470 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
624 471
625 WRT_REG_WORD(&reg->ctrl_status, 0x00); 472 WRT_REG_WORD(&reg->ctrl_status, 0x00);
626 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 473 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
627 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 474 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
628 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 475 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
629 476
630 WRT_REG_WORD(&reg->pcr, 0x2000); 477 WRT_REG_WORD(&reg->pcr, 0x2000);
631 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 478 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
632 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 479 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
633 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); 480 fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
634 481
635 WRT_REG_WORD(&reg->pcr, 0x2100); 482 WRT_REG_WORD(&reg->pcr, 0x2100);
636 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 483 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
637 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 484 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
638 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); 485 fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
639 486
640 WRT_REG_WORD(&reg->pcr, 0x2200); 487 WRT_REG_WORD(&reg->pcr, 0x2200);
641 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 488 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
642 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 489 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
643 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); 490 fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
644 491
645 WRT_REG_WORD(&reg->pcr, 0x2300); 492 WRT_REG_WORD(&reg->pcr, 0x2300);
646 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 493 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
647 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 494 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
648 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); 495 fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
649 496
650 WRT_REG_WORD(&reg->pcr, 0x2400); 497 WRT_REG_WORD(&reg->pcr, 0x2400);
651 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 498 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
652 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 499 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
653 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); 500 fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
654 501
655 WRT_REG_WORD(&reg->pcr, 0x2500); 502 WRT_REG_WORD(&reg->pcr, 0x2500);
656 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 503 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
657 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 504 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
658 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); 505 fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
659 506
660 WRT_REG_WORD(&reg->pcr, 0x2600); 507 WRT_REG_WORD(&reg->pcr, 0x2600);
661 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 508 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
662 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 509 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
663 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); 510 fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
664 511
665 WRT_REG_WORD(&reg->pcr, 0x2700); 512 WRT_REG_WORD(&reg->pcr, 0x2700);
666 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 513 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
667 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 514 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
668 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); 515 fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
669 516
670 WRT_REG_WORD(&reg->ctrl_status, 0x10); 517 WRT_REG_WORD(&reg->ctrl_status, 0x10);
671 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 518 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
672 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 519 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
673 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 520 fw->frame_buf_hdw_reg[cnt] =
521 htons(RD_REG_WORD(dmp_reg++));
674 522
675 WRT_REG_WORD(&reg->ctrl_status, 0x20); 523 WRT_REG_WORD(&reg->ctrl_status, 0x20);
676 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 524 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
677 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 525 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
678 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); 526 fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
679 527
680 WRT_REG_WORD(&reg->ctrl_status, 0x30); 528 WRT_REG_WORD(&reg->ctrl_status, 0x30);
681 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 529 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
682 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 530 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
683 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); 531 fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
684 532
685 /* Reset the ISP. */ 533 /* Reset the ISP. */
686 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); 534 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
@@ -755,12 +603,15 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
755 603
756 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 604 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
757 rval = mb0 & MBS_MASK; 605 rval = mb0 & MBS_MASK;
758 fw->risc_ram[cnt] = mb2; 606 fw->risc_ram[cnt] = htons(mb2);
759 } else { 607 } else {
760 rval = QLA_FUNCTION_FAILED; 608 rval = QLA_FUNCTION_FAILED;
761 } 609 }
762 } 610 }
763 611
612 if (rval == QLA_SUCCESS)
613 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
614
764 if (rval != QLA_SUCCESS) { 615 if (rval != QLA_SUCCESS) {
765 qla_printk(KERN_WARNING, ha, 616 qla_printk(KERN_WARNING, ha,
766 "Failed to dump firmware (%x)!!!\n", rval); 617 "Failed to dump firmware (%x)!!!\n", rval);
@@ -778,179 +629,6 @@ qla2100_fw_dump_failed:
778 spin_unlock_irqrestore(&ha->hardware_lock, flags); 629 spin_unlock_irqrestore(&ha->hardware_lock, flags);
779} 630}
780 631
781/**
782 * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
783 * @ha: HA context
784 */
785void
786qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
787{
788 uint32_t cnt;
789 char *uiter;
790 char fw_info[30];
791 struct qla2100_fw_dump *fw;
792
793 uiter = ha->fw_dump_buffer;
794 fw = ha->fw_dump;
795
796 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
797 ha->isp_ops.fw_version_str(ha, fw_info));
798
799 qla_uprintf(&uiter, "\n[==>BEG]\n");
800
801 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
802
803 qla_uprintf(&uiter, "PBIU Registers:");
804 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
805 if (cnt % 8 == 0) {
806 qla_uprintf(&uiter, "\n");
807 }
808 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
809 }
810
811 qla_uprintf(&uiter, "\n\nMailbox Registers:");
812 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
813 if (cnt % 8 == 0) {
814 qla_uprintf(&uiter, "\n");
815 }
816 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
817 }
818
819 qla_uprintf(&uiter, "\n\nDMA Registers:");
820 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
821 if (cnt % 8 == 0) {
822 qla_uprintf(&uiter, "\n");
823 }
824 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
825 }
826
827 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
828 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
829 if (cnt % 8 == 0) {
830 qla_uprintf(&uiter, "\n");
831 }
832 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
833 }
834
835 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
836 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
837 if (cnt % 8 == 0) {
838 qla_uprintf(&uiter, "\n");
839 }
840 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
841 }
842
843 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
844 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
845 if (cnt % 8 == 0) {
846 qla_uprintf(&uiter, "\n");
847 }
848 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
849 }
850
851 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
852 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
853 if (cnt % 8 == 0) {
854 qla_uprintf(&uiter, "\n");
855 }
856 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
857 }
858
859 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
860 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
861 if (cnt % 8 == 0) {
862 qla_uprintf(&uiter, "\n");
863 }
864 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
865 }
866
867 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
868 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
869 if (cnt % 8 == 0) {
870 qla_uprintf(&uiter, "\n");
871 }
872 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
873 }
874
875 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
876 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
877 if (cnt % 8 == 0) {
878 qla_uprintf(&uiter, "\n");
879 }
880 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
881 }
882
883 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
884 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
885 if (cnt % 8 == 0) {
886 qla_uprintf(&uiter, "\n");
887 }
888 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
889 }
890
891 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
892 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
893 if (cnt % 8 == 0) {
894 qla_uprintf(&uiter, "\n");
895 }
896 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
897 }
898
899 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
900 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
901 if (cnt % 8 == 0) {
902 qla_uprintf(&uiter, "\n");
903 }
904 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
905 }
906
907 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
908 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
909 if (cnt % 8 == 0) {
910 qla_uprintf(&uiter, "\n");
911 }
912 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
913 }
914
915 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
916 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
917 if (cnt % 8 == 0) {
918 qla_uprintf(&uiter, "\n");
919 }
920 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
921 }
922
923 qla_uprintf(&uiter, "\n\nRISC SRAM:");
924 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
925 if (cnt % 8 == 0) {
926 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
927 }
928 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
929 }
930
931 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
932
933 return;
934}
935
936static int
937qla_uprintf(char **uiter, char *fmt, ...)
938{
939 int iter, len;
940 char buf[128];
941 va_list args;
942
943 va_start(args, fmt);
944 len = vsprintf(buf, fmt, args);
945 va_end(args);
946
947 for (iter = 0; iter < len; iter++, *uiter += 1)
948 *uiter[0] = buf[iter];
949
950 return (len);
951}
952
953
954void 632void
955qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 633qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
956{ 634{
@@ -967,6 +645,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
967 unsigned long flags; 645 unsigned long flags;
968 struct qla24xx_fw_dump *fw; 646 struct qla24xx_fw_dump *fw;
969 uint32_t ext_mem_cnt; 647 uint32_t ext_mem_cnt;
648 void *eft;
970 649
971 risc_address = ext_mem_cnt = 0; 650 risc_address = ext_mem_cnt = 0;
972 memset(mb, 0, sizeof(mb)); 651 memset(mb, 0, sizeof(mb));
@@ -987,10 +666,11 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
987 "request...\n", ha->fw_dump); 666 "request...\n", ha->fw_dump);
988 goto qla24xx_fw_dump_failed; 667 goto qla24xx_fw_dump_failed;
989 } 668 }
990 fw = ha->fw_dump; 669 fw = &ha->fw_dump->isp.isp24;
670 qla2xxx_prep_dump(ha, ha->fw_dump);
991 671
992 rval = QLA_SUCCESS; 672 rval = QLA_SUCCESS;
993 fw->host_status = RD_REG_DWORD(&reg->host_status); 673 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
994 674
995 /* Pause RISC. */ 675 /* Pause RISC. */
996 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 676 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) {
@@ -1012,7 +692,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1012 /* Host interface registers. */ 692 /* Host interface registers. */
1013 dmp_reg = (uint32_t __iomem *)(reg + 0); 693 dmp_reg = (uint32_t __iomem *)(reg + 0);
1014 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 694 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1015 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++); 695 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1016 696
1017 /* Disable interrupts. */ 697 /* Disable interrupts. */
1018 WRT_REG_DWORD(&reg->ictrl, 0); 698 WRT_REG_DWORD(&reg->ictrl, 0);
@@ -1024,470 +704,471 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1024 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 704 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1025 WRT_REG_DWORD(dmp_reg, 0xB0000000); 705 WRT_REG_DWORD(dmp_reg, 0xB0000000);
1026 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 706 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1027 fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg); 707 fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg));
1028 708
1029 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 709 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1030 WRT_REG_DWORD(dmp_reg, 0xB0100000); 710 WRT_REG_DWORD(dmp_reg, 0xB0100000);
1031 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 711 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1032 fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg); 712 fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg));
1033 713
1034 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 714 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1035 WRT_REG_DWORD(dmp_reg, 0xB0200000); 715 WRT_REG_DWORD(dmp_reg, 0xB0200000);
1036 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 716 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1037 fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg); 717 fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg));
1038 718
1039 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 719 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1040 WRT_REG_DWORD(dmp_reg, 0xB0300000); 720 WRT_REG_DWORD(dmp_reg, 0xB0300000);
1041 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 721 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1042 fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg); 722 fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg));
1043 723
1044 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 724 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1045 WRT_REG_DWORD(dmp_reg, 0xB0400000); 725 WRT_REG_DWORD(dmp_reg, 0xB0400000);
1046 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 726 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1047 fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg); 727 fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg));
1048 728
1049 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 729 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1050 WRT_REG_DWORD(dmp_reg, 0xB0500000); 730 WRT_REG_DWORD(dmp_reg, 0xB0500000);
1051 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 731 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1052 fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg); 732 fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg));
1053 733
1054 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 734 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1055 WRT_REG_DWORD(dmp_reg, 0xB0600000); 735 WRT_REG_DWORD(dmp_reg, 0xB0600000);
1056 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 736 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1057 fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg); 737 fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg));
1058 738
1059 /* Mailbox registers. */ 739 /* Mailbox registers. */
1060 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 740 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
1061 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 741 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1062 fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++); 742 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1063 743
1064 /* Transfer sequence registers. */ 744 /* Transfer sequence registers. */
1065 iter_reg = fw->xseq_gp_reg; 745 iter_reg = fw->xseq_gp_reg;
1066 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 746 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 747 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1068 for (cnt = 0; cnt < 16; cnt++) 748 for (cnt = 0; cnt < 16; cnt++)
1069 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 749 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1070 750
1071 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 751 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 752 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1073 for (cnt = 0; cnt < 16; cnt++) 753 for (cnt = 0; cnt < 16; cnt++)
1074 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 754 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1075 755
1076 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 756 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 757 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1078 for (cnt = 0; cnt < 16; cnt++) 758 for (cnt = 0; cnt < 16; cnt++)
1079 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 759 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1080 760
1081 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 761 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 762 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1083 for (cnt = 0; cnt < 16; cnt++) 763 for (cnt = 0; cnt < 16; cnt++)
1084 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 764 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1085 765
1086 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 766 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 767 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1088 for (cnt = 0; cnt < 16; cnt++) 768 for (cnt = 0; cnt < 16; cnt++)
1089 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 769 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1090 770
1091 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 771 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1092 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 772 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1093 for (cnt = 0; cnt < 16; cnt++) 773 for (cnt = 0; cnt < 16; cnt++)
1094 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 774 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1095 775
1096 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 776 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1097 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 777 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1098 for (cnt = 0; cnt < 16; cnt++) 778 for (cnt = 0; cnt < 16; cnt++)
1099 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 779 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1100 780
1101 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 781 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1102 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 782 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1103 for (cnt = 0; cnt < 16; cnt++) 783 for (cnt = 0; cnt < 16; cnt++)
1104 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 784 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1105 785
1106 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 786 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1107 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 787 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1108 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) 788 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
1109 fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++); 789 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1110 790
1111 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 791 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1112 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 792 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1113 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 793 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1114 fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++); 794 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1115 795
1116 /* Receive sequence registers. */ 796 /* Receive sequence registers. */
1117 iter_reg = fw->rseq_gp_reg; 797 iter_reg = fw->rseq_gp_reg;
1118 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 798 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 799 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1120 for (cnt = 0; cnt < 16; cnt++) 800 for (cnt = 0; cnt < 16; cnt++)
1121 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 801 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1122 802
1123 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 803 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 804 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1125 for (cnt = 0; cnt < 16; cnt++) 805 for (cnt = 0; cnt < 16; cnt++)
1126 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 806 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1127 807
1128 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 808 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 809 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1130 for (cnt = 0; cnt < 16; cnt++) 810 for (cnt = 0; cnt < 16; cnt++)
1131 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 811 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1132 812
1133 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 813 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 814 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1135 for (cnt = 0; cnt < 16; cnt++) 815 for (cnt = 0; cnt < 16; cnt++)
1136 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 816 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1137 817
1138 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 818 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 819 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1140 for (cnt = 0; cnt < 16; cnt++) 820 for (cnt = 0; cnt < 16; cnt++)
1141 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 821 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1142 822
1143 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 823 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 824 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1145 for (cnt = 0; cnt < 16; cnt++) 825 for (cnt = 0; cnt < 16; cnt++)
1146 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 826 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1147 827
1148 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 828 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1149 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 829 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1150 for (cnt = 0; cnt < 16; cnt++) 830 for (cnt = 0; cnt < 16; cnt++)
1151 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 831 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1152 832
1153 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 833 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1154 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 834 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1155 for (cnt = 0; cnt < 16; cnt++) 835 for (cnt = 0; cnt < 16; cnt++)
1156 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 836 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1157 837
1158 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 838 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1159 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 839 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1160 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) 840 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
1161 fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++); 841 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1162 842
1163 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 843 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1164 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 844 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1165 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 845 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1166 fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++); 846 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1167 847
1168 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 848 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 849 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1170 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 850 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1171 fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++); 851 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1172 852
1173 /* Command DMA registers. */ 853 /* Command DMA registers. */
1174 WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 854 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1175 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 855 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1176 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 856 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1177 fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++); 857 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1178 858
1179 /* Queues. */ 859 /* Queues. */
1180 iter_reg = fw->req0_dma_reg; 860 iter_reg = fw->req0_dma_reg;
1181 WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 861 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1182 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 862 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1183 for (cnt = 0; cnt < 8; cnt++) 863 for (cnt = 0; cnt < 8; cnt++)
1184 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 864 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1185 865
1186 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 866 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1187 for (cnt = 0; cnt < 7; cnt++) 867 for (cnt = 0; cnt < 7; cnt++)
1188 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 868 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1189 869
1190 iter_reg = fw->resp0_dma_reg; 870 iter_reg = fw->resp0_dma_reg;
1191 WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 871 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1192 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 872 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1193 for (cnt = 0; cnt < 8; cnt++) 873 for (cnt = 0; cnt < 8; cnt++)
1194 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 874 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1195 875
1196 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 876 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1197 for (cnt = 0; cnt < 7; cnt++) 877 for (cnt = 0; cnt < 7; cnt++)
1198 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 878 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1199 879
1200 iter_reg = fw->req1_dma_reg; 880 iter_reg = fw->req1_dma_reg;
1201 WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 881 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1202 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 882 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1203 for (cnt = 0; cnt < 8; cnt++) 883 for (cnt = 0; cnt < 8; cnt++)
1204 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 884 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1205 885
1206 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 886 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1207 for (cnt = 0; cnt < 7; cnt++) 887 for (cnt = 0; cnt < 7; cnt++)
1208 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 888 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1209 889
1210 /* Transmit DMA registers. */ 890 /* Transmit DMA registers. */
1211 iter_reg = fw->xmt0_dma_reg; 891 iter_reg = fw->xmt0_dma_reg;
1212 WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 892 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1213 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 893 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1214 for (cnt = 0; cnt < 16; cnt++) 894 for (cnt = 0; cnt < 16; cnt++)
1215 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 895 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1216 896
1217 WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 897 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1218 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 898 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1219 for (cnt = 0; cnt < 16; cnt++) 899 for (cnt = 0; cnt < 16; cnt++)
1220 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 900 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1221 901
1222 iter_reg = fw->xmt1_dma_reg; 902 iter_reg = fw->xmt1_dma_reg;
1223 WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 903 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1224 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 904 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1225 for (cnt = 0; cnt < 16; cnt++) 905 for (cnt = 0; cnt < 16; cnt++)
1226 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 906 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1227 907
1228 WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 908 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1229 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 909 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1230 for (cnt = 0; cnt < 16; cnt++) 910 for (cnt = 0; cnt < 16; cnt++)
1231 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 911 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1232 912
1233 iter_reg = fw->xmt2_dma_reg; 913 iter_reg = fw->xmt2_dma_reg;
1234 WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 914 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1235 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 915 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1236 for (cnt = 0; cnt < 16; cnt++) 916 for (cnt = 0; cnt < 16; cnt++)
1237 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 917 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1238 918
1239 WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 919 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1240 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 920 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1241 for (cnt = 0; cnt < 16; cnt++) 921 for (cnt = 0; cnt < 16; cnt++)
1242 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 922 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1243 923
1244 iter_reg = fw->xmt3_dma_reg; 924 iter_reg = fw->xmt3_dma_reg;
1245 WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 925 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1246 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 926 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1247 for (cnt = 0; cnt < 16; cnt++) 927 for (cnt = 0; cnt < 16; cnt++)
1248 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 928 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1249 929
1250 WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 930 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1251 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 931 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1252 for (cnt = 0; cnt < 16; cnt++) 932 for (cnt = 0; cnt < 16; cnt++)
1253 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 933 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1254 934
1255 iter_reg = fw->xmt4_dma_reg; 935 iter_reg = fw->xmt4_dma_reg;
1256 WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 936 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1257 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 937 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1258 for (cnt = 0; cnt < 16; cnt++) 938 for (cnt = 0; cnt < 16; cnt++)
1259 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 939 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1260 940
1261 WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 941 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1262 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 942 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1263 for (cnt = 0; cnt < 16; cnt++) 943 for (cnt = 0; cnt < 16; cnt++)
1264 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 944 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1265 945
1266 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 946 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1267 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 947 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1268 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 948 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1269 fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++); 949 fw->xmt_data_dma_reg[cnt] =
950 htonl(RD_REG_DWORD(dmp_reg++));
1270 951
1271 /* Receive DMA registers. */ 952 /* Receive DMA registers. */
1272 iter_reg = fw->rcvt0_data_dma_reg; 953 iter_reg = fw->rcvt0_data_dma_reg;
1273 WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 954 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1274 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 955 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1275 for (cnt = 0; cnt < 16; cnt++) 956 for (cnt = 0; cnt < 16; cnt++)
1276 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 957 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1277 958
1278 WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 959 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1279 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 960 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1280 for (cnt = 0; cnt < 16; cnt++) 961 for (cnt = 0; cnt < 16; cnt++)
1281 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 962 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1282 963
1283 iter_reg = fw->rcvt1_data_dma_reg; 964 iter_reg = fw->rcvt1_data_dma_reg;
1284 WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 965 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1285 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 966 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1286 for (cnt = 0; cnt < 16; cnt++) 967 for (cnt = 0; cnt < 16; cnt++)
1287 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1288 969
1289 WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 970 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1290 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 971 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1291 for (cnt = 0; cnt < 16; cnt++) 972 for (cnt = 0; cnt < 16; cnt++)
1292 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1293 974
1294 /* RISC registers. */ 975 /* RISC registers. */
1295 iter_reg = fw->risc_gp_reg; 976 iter_reg = fw->risc_gp_reg;
1296 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 977 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1297 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 978 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1298 for (cnt = 0; cnt < 16; cnt++) 979 for (cnt = 0; cnt < 16; cnt++)
1299 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 980 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1300 981
1301 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 982 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1302 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 983 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1303 for (cnt = 0; cnt < 16; cnt++) 984 for (cnt = 0; cnt < 16; cnt++)
1304 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 985 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1305 986
1306 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 987 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1307 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 988 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1308 for (cnt = 0; cnt < 16; cnt++) 989 for (cnt = 0; cnt < 16; cnt++)
1309 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 990 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1310 991
1311 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 992 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1312 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 993 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1313 for (cnt = 0; cnt < 16; cnt++) 994 for (cnt = 0; cnt < 16; cnt++)
1314 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 995 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1315 996
1316 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 997 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1317 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 998 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1318 for (cnt = 0; cnt < 16; cnt++) 999 for (cnt = 0; cnt < 16; cnt++)
1319 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1000 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1320 1001
1321 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1002 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1322 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1003 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1323 for (cnt = 0; cnt < 16; cnt++) 1004 for (cnt = 0; cnt < 16; cnt++)
1324 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1325 1006
1326 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1007 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1327 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1008 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1328 for (cnt = 0; cnt < 16; cnt++) 1009 for (cnt = 0; cnt < 16; cnt++)
1329 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1330 1011
1331 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1012 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1332 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1013 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1333 for (cnt = 0; cnt < 16; cnt++) 1014 for (cnt = 0; cnt < 16; cnt++)
1334 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1015 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1335 1016
1336 /* Local memory controller registers. */ 1017 /* Local memory controller registers. */
1337 iter_reg = fw->lmc_reg; 1018 iter_reg = fw->lmc_reg;
1338 WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1019 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1339 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1020 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1340 for (cnt = 0; cnt < 16; cnt++) 1021 for (cnt = 0; cnt < 16; cnt++)
1341 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1022 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1342 1023
1343 WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1024 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1344 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1025 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1345 for (cnt = 0; cnt < 16; cnt++) 1026 for (cnt = 0; cnt < 16; cnt++)
1346 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1347 1028
1348 WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1029 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1349 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1030 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1350 for (cnt = 0; cnt < 16; cnt++) 1031 for (cnt = 0; cnt < 16; cnt++)
1351 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1352 1033
1353 WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1034 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1354 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1035 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1355 for (cnt = 0; cnt < 16; cnt++) 1036 for (cnt = 0; cnt < 16; cnt++)
1356 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1037 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1357 1038
1358 WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1039 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1359 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1040 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1360 for (cnt = 0; cnt < 16; cnt++) 1041 for (cnt = 0; cnt < 16; cnt++)
1361 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1042 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1362 1043
1363 WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1044 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1364 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1045 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1365 for (cnt = 0; cnt < 16; cnt++) 1046 for (cnt = 0; cnt < 16; cnt++)
1366 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1047 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1367 1048
1368 WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1049 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1369 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1050 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1370 for (cnt = 0; cnt < 16; cnt++) 1051 for (cnt = 0; cnt < 16; cnt++)
1371 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1372 1053
1373 /* Fibre Protocol Module registers. */ 1054 /* Fibre Protocol Module registers. */
1374 iter_reg = fw->fpm_hdw_reg; 1055 iter_reg = fw->fpm_hdw_reg;
1375 WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1056 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1376 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1057 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1377 for (cnt = 0; cnt < 16; cnt++) 1058 for (cnt = 0; cnt < 16; cnt++)
1378 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1059 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1379 1060
1380 WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1061 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1381 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1062 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1382 for (cnt = 0; cnt < 16; cnt++) 1063 for (cnt = 0; cnt < 16; cnt++)
1383 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1064 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1384 1065
1385 WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1066 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1386 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1387 for (cnt = 0; cnt < 16; cnt++) 1068 for (cnt = 0; cnt < 16; cnt++)
1388 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1069 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1389 1070
1390 WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1071 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1391 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1392 for (cnt = 0; cnt < 16; cnt++) 1073 for (cnt = 0; cnt < 16; cnt++)
1393 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1074 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1394 1075
1395 WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1076 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1396 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1397 for (cnt = 0; cnt < 16; cnt++) 1078 for (cnt = 0; cnt < 16; cnt++)
1398 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1399 1080
1400 WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1081 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1401 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1402 for (cnt = 0; cnt < 16; cnt++) 1083 for (cnt = 0; cnt < 16; cnt++)
1403 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1404 1085
1405 WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1086 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1406 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1407 for (cnt = 0; cnt < 16; cnt++) 1088 for (cnt = 0; cnt < 16; cnt++)
1408 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1409 1090
1410 WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1091 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1411 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1092 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1412 for (cnt = 0; cnt < 16; cnt++) 1093 for (cnt = 0; cnt < 16; cnt++)
1413 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1414 1095
1415 WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1096 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1416 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1097 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1417 for (cnt = 0; cnt < 16; cnt++) 1098 for (cnt = 0; cnt < 16; cnt++)
1418 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1419 1100
1420 WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1101 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1421 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1102 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1422 for (cnt = 0; cnt < 16; cnt++) 1103 for (cnt = 0; cnt < 16; cnt++)
1423 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1424 1105
1425 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1106 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1426 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1107 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1427 for (cnt = 0; cnt < 16; cnt++) 1108 for (cnt = 0; cnt < 16; cnt++)
1428 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1429 1110
1430 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1111 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1431 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1112 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1432 for (cnt = 0; cnt < 16; cnt++) 1113 for (cnt = 0; cnt < 16; cnt++)
1433 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1434 1115
1435 /* Frame Buffer registers. */ 1116 /* Frame Buffer registers. */
1436 iter_reg = fw->fb_hdw_reg; 1117 iter_reg = fw->fb_hdw_reg;
1437 WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1118 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1438 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1439 for (cnt = 0; cnt < 16; cnt++) 1120 for (cnt = 0; cnt < 16; cnt++)
1440 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1441 1122
1442 WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1123 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1443 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1444 for (cnt = 0; cnt < 16; cnt++) 1125 for (cnt = 0; cnt < 16; cnt++)
1445 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1446 1127
1447 WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1128 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1448 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1449 for (cnt = 0; cnt < 16; cnt++) 1130 for (cnt = 0; cnt < 16; cnt++)
1450 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1451 1132
1452 WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1133 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1453 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1454 for (cnt = 0; cnt < 16; cnt++) 1135 for (cnt = 0; cnt < 16; cnt++)
1455 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1456 1137
1457 WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1138 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1458 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1459 for (cnt = 0; cnt < 16; cnt++) 1140 for (cnt = 0; cnt < 16; cnt++)
1460 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1461 1142
1462 WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1143 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1463 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1464 for (cnt = 0; cnt < 16; cnt++) 1145 for (cnt = 0; cnt < 16; cnt++)
1465 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1466 1147
1467 WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1148 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1468 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1149 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1469 for (cnt = 0; cnt < 16; cnt++) 1150 for (cnt = 0; cnt < 16; cnt++)
1470 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1471 1152
1472 WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1153 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1473 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1154 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1474 for (cnt = 0; cnt < 16; cnt++) 1155 for (cnt = 0; cnt < 16; cnt++)
1475 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1156 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1476 1157
1477 WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1158 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1478 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1159 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1479 for (cnt = 0; cnt < 16; cnt++) 1160 for (cnt = 0; cnt < 16; cnt++)
1480 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1161 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1481 1162
1482 WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1163 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1483 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1164 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1484 for (cnt = 0; cnt < 16; cnt++) 1165 for (cnt = 0; cnt < 16; cnt++)
1485 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1166 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1486 1167
1487 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1168 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1488 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1489 for (cnt = 0; cnt < 16; cnt++) 1170 for (cnt = 0; cnt < 16; cnt++)
1490 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1491 1172
1492 /* Reset RISC. */ 1173 /* Reset RISC. */
1493 WRT_REG_DWORD(&reg->ctrl_status, 1174 WRT_REG_DWORD(&reg->ctrl_status,
@@ -1577,7 +1258,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1577 1258
1578 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1259 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1579 rval = mb[0] & MBS_MASK; 1260 rval = mb[0] & MBS_MASK;
1580 fw->code_ram[cnt] = (mb[3] << 16) | mb[2]; 1261 fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
1581 } else { 1262 } else {
1582 rval = QLA_FUNCTION_FAILED; 1263 rval = QLA_FUNCTION_FAILED;
1583 } 1264 }
@@ -1627,12 +1308,18 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1627 1308
1628 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1309 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1629 rval = mb[0] & MBS_MASK; 1310 rval = mb[0] & MBS_MASK;
1630 fw->ext_mem[cnt] = (mb[3] << 16) | mb[2]; 1311 fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
1631 } else { 1312 } else {
1632 rval = QLA_FUNCTION_FAILED; 1313 rval = QLA_FUNCTION_FAILED;
1633 } 1314 }
1634 } 1315 }
1635 1316
1317 if (rval == QLA_SUCCESS) {
1318 eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]);
1319 if (ha->eft)
1320 memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size));
1321 }
1322
1636 if (rval != QLA_SUCCESS) { 1323 if (rval != QLA_SUCCESS) {
1637 qla_printk(KERN_WARNING, ha, 1324 qla_printk(KERN_WARNING, ha,
1638 "Failed to dump firmware (%x)!!!\n", rval); 1325 "Failed to dump firmware (%x)!!!\n", rval);
@@ -1650,252 +1337,6 @@ qla24xx_fw_dump_failed:
1650 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1337 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1651} 1338}
1652 1339
1653void
1654qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
1655{
1656 uint32_t cnt;
1657 char *uiter;
1658 struct qla24xx_fw_dump *fw;
1659 uint32_t ext_mem_cnt;
1660
1661 uiter = ha->fw_dump_buffer;
1662 fw = ha->fw_dump;
1663
1664 qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
1665 ha->fw_major_version, ha->fw_minor_version,
1666 ha->fw_subminor_version, ha->fw_attributes);
1667
1668 qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
1669
1670 qla_uprintf(&uiter, "\nHost Interface Registers");
1671 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
1672 if (cnt % 8 == 0)
1673 qla_uprintf(&uiter, "\n");
1674
1675 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
1676 }
1677
1678 qla_uprintf(&uiter, "\n\nShadow Registers");
1679 for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
1680 if (cnt % 8 == 0)
1681 qla_uprintf(&uiter, "\n");
1682
1683 qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
1684 }
1685
1686 qla_uprintf(&uiter, "\n\nMailbox Registers");
1687 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
1688 if (cnt % 8 == 0)
1689 qla_uprintf(&uiter, "\n");
1690
1691 qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
1692 }
1693
1694 qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
1695 for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
1696 if (cnt % 8 == 0)
1697 qla_uprintf(&uiter, "\n");
1698
1699 qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
1700 }
1701
1702 qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
1703 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
1704 if (cnt % 8 == 0)
1705 qla_uprintf(&uiter, "\n");
1706
1707 qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
1708 }
1709
1710 qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
1711 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
1712 if (cnt % 8 == 0)
1713 qla_uprintf(&uiter, "\n");
1714
1715 qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
1716 }
1717
1718 qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
1719 for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
1720 if (cnt % 8 == 0)
1721 qla_uprintf(&uiter, "\n");
1722
1723 qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
1724 }
1725
1726 qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
1727 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
1728 if (cnt % 8 == 0)
1729 qla_uprintf(&uiter, "\n");
1730
1731 qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
1732 }
1733
1734 qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
1735 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
1736 if (cnt % 8 == 0)
1737 qla_uprintf(&uiter, "\n");
1738
1739 qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
1740 }
1741
1742 qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
1743 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
1744 if (cnt % 8 == 0)
1745 qla_uprintf(&uiter, "\n");
1746
1747 qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
1748 }
1749
1750 qla_uprintf(&uiter, "\n\nCommand DMA Registers");
1751 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
1752 if (cnt % 8 == 0)
1753 qla_uprintf(&uiter, "\n");
1754
1755 qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
1756 }
1757
1758 qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
1759 for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
1760 if (cnt % 8 == 0)
1761 qla_uprintf(&uiter, "\n");
1762
1763 qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
1764 }
1765
1766 qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
1767 for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
1768 if (cnt % 8 == 0)
1769 qla_uprintf(&uiter, "\n");
1770
1771 qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
1772 }
1773
1774 qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
1775 for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
1776 if (cnt % 8 == 0)
1777 qla_uprintf(&uiter, "\n");
1778
1779 qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
1780 }
1781
1782 qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
1783 for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
1784 if (cnt % 8 == 0)
1785 qla_uprintf(&uiter, "\n");
1786
1787 qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
1788 }
1789
1790 qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
1791 for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
1792 if (cnt % 8 == 0)
1793 qla_uprintf(&uiter, "\n");
1794
1795 qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
1796 }
1797
1798 qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
1799 for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
1800 if (cnt % 8 == 0)
1801 qla_uprintf(&uiter, "\n");
1802
1803 qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
1804 }
1805
1806 qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
1807 for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
1808 if (cnt % 8 == 0)
1809 qla_uprintf(&uiter, "\n");
1810
1811 qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
1812 }
1813
1814 qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
1815 for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
1816 if (cnt % 8 == 0)
1817 qla_uprintf(&uiter, "\n");
1818
1819 qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
1820 }
1821
1822 qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
1823 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
1824 if (cnt % 8 == 0)
1825 qla_uprintf(&uiter, "\n");
1826
1827 qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
1828 }
1829
1830 qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
1831 for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
1832 if (cnt % 8 == 0)
1833 qla_uprintf(&uiter, "\n");
1834
1835 qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
1836 }
1837
1838 qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
1839 for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
1840 if (cnt % 8 == 0)
1841 qla_uprintf(&uiter, "\n");
1842
1843 qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
1844 }
1845
1846 qla_uprintf(&uiter, "\n\nRISC GP Registers");
1847 for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
1848 if (cnt % 8 == 0)
1849 qla_uprintf(&uiter, "\n");
1850
1851 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
1852 }
1853
1854 qla_uprintf(&uiter, "\n\nLMC Registers");
1855 for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
1856 if (cnt % 8 == 0)
1857 qla_uprintf(&uiter, "\n");
1858
1859 qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
1860 }
1861
1862 qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
1863 for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
1864 if (cnt % 8 == 0)
1865 qla_uprintf(&uiter, "\n");
1866
1867 qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
1868 }
1869
1870 qla_uprintf(&uiter, "\n\nFB Hardware Registers");
1871 for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
1872 if (cnt % 8 == 0)
1873 qla_uprintf(&uiter, "\n");
1874
1875 qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
1876 }
1877
1878 qla_uprintf(&uiter, "\n\nCode RAM");
1879 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
1880 if (cnt % 8 == 0) {
1881 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
1882 }
1883 qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
1884 }
1885
1886 qla_uprintf(&uiter, "\n\nExternal Memory");
1887 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1888 for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
1889 if (cnt % 8 == 0) {
1890 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
1891 }
1892 qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
1893 }
1894
1895 qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
1896}
1897
1898
1899/****************************************************************************/ 1340/****************************************************************************/
1900/* Driver Debug Functions. */ 1341/* Driver Debug Functions. */
1901/****************************************************************************/ 1342/****************************************************************************/
diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h
index ab6afeaa2f2c..ace6afdfe708 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.h
+++ b/drivers/scsi/qla2xxx/qla_dbg.h
@@ -176,9 +176,6 @@
176/* 176/*
177 * Firmware Dump structure definition 177 * Firmware Dump structure definition
178 */ 178 */
179#define FW_DUMP_SIZE_128K 0xBC000
180#define FW_DUMP_SIZE_512K 0x2FC000
181#define FW_DUMP_SIZE_1M 0x5FC000
182 179
183struct qla2300_fw_dump { 180struct qla2300_fw_dump {
184 uint16_t hccr; 181 uint16_t hccr;
@@ -224,8 +221,6 @@ struct qla2100_fw_dump {
224 uint16_t risc_ram[0xf000]; 221 uint16_t risc_ram[0xf000];
225}; 222};
226 223
227#define FW_DUMP_SIZE_24XX 0x2B0000
228
229struct qla24xx_fw_dump { 224struct qla24xx_fw_dump {
230 uint32_t host_status; 225 uint32_t host_status;
231 uint32_t host_reg[32]; 226 uint32_t host_reg[32];
@@ -257,3 +252,39 @@ struct qla24xx_fw_dump {
257 uint32_t code_ram[0x2000]; 252 uint32_t code_ram[0x2000];
258 uint32_t ext_mem[1]; 253 uint32_t ext_mem[1];
259}; 254};
255
256#define EFT_NUM_BUFFERS 4
257#define EFT_BYTES_PER_BUFFER 0x4000
258#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
259
260struct qla2xxx_fw_dump {
261 uint8_t signature[4];
262 uint32_t version;
263
264 uint32_t fw_major_version;
265 uint32_t fw_minor_version;
266 uint32_t fw_subminor_version;
267 uint32_t fw_attributes;
268
269 uint32_t vendor;
270 uint32_t device;
271 uint32_t subsystem_vendor;
272 uint32_t subsystem_device;
273
274 uint32_t fixed_size;
275 uint32_t mem_size;
276 uint32_t req_q_size;
277 uint32_t rsp_q_size;
278
279 uint32_t eft_size;
280 uint32_t eft_addr_l;
281 uint32_t eft_addr_h;
282
283 uint32_t header_size;
284
285 union {
286 struct qla2100_fw_dump isp21;
287 struct qla2300_fw_dump isp23;
288 struct qla24xx_fw_dump isp24;
289 } isp;
290};
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index d6f6579cfd27..653e22e490a1 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -608,6 +608,7 @@ typedef struct {
608#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 608#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
609#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 609#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
610#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 610#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
611#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
611#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 612#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
612#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 613#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
613#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 614#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
@@ -618,6 +619,9 @@ typedef struct {
618#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 619#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
619#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 620#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
620 621
622#define TC_ENABLE 4
623#define TC_DISABLE 5
624
621/* Firmware return data sizes */ 625/* Firmware return data sizes */
622#define FCAL_MAP_SIZE 128 626#define FCAL_MAP_SIZE 128
623 627
@@ -1997,7 +2001,6 @@ struct isp_operations {
1997 uint32_t); 2001 uint32_t);
1998 2002
1999 void (*fw_dump) (struct scsi_qla_host *, int); 2003 void (*fw_dump) (struct scsi_qla_host *, int);
2000 void (*ascii_fw_dump) (struct scsi_qla_host *);
2001 2004
2002 int (*beacon_on) (struct scsi_qla_host *); 2005 int (*beacon_on) (struct scsi_qla_host *);
2003 int (*beacon_off) (struct scsi_qla_host *); 2006 int (*beacon_off) (struct scsi_qla_host *);
@@ -2303,11 +2306,12 @@ typedef struct scsi_qla_host {
2303 uint16_t fw_seriallink_options24[4]; 2306 uint16_t fw_seriallink_options24[4];
2304 2307
2305 /* Firmware dump information. */ 2308 /* Firmware dump information. */
2306 void *fw_dump; 2309 struct qla2xxx_fw_dump *fw_dump;
2310 uint32_t fw_dump_len;
2307 int fw_dumped; 2311 int fw_dumped;
2308 int fw_dump_reading; 2312 int fw_dump_reading;
2309 char *fw_dump_buffer; 2313 dma_addr_t eft_dma;
2310 int fw_dump_buffer_len; 2314 void *eft;
2311 2315
2312 uint8_t host_str[16]; 2316 uint8_t host_str[16];
2313 uint32_t pci_attr; 2317 uint32_t pci_attr;
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
index 164d53ccbfd0..fec1e1c9381f 100644
--- a/drivers/scsi/qla2xxx/qla_gbl.h
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
@@ -51,6 +51,8 @@ extern int qla2x00_abort_isp(scsi_qla_host_t *);
51extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *); 51extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *);
52extern void qla2x00_reg_remote_port(scsi_qla_host_t *, fc_port_t *); 52extern void qla2x00_reg_remote_port(scsi_qla_host_t *, fc_port_t *);
53 53
54extern void qla2x00_alloc_fw_dump(scsi_qla_host_t *);
55
54/* 56/*
55 * Global Data in qla_os.c source file. 57 * Global Data in qla_os.c source file.
56 */ 58 */
@@ -61,6 +63,7 @@ extern int qlport_down_retry;
61extern int ql2xplogiabsentdevice; 63extern int ql2xplogiabsentdevice;
62extern int ql2xloginretrycount; 64extern int ql2xloginretrycount;
63extern int ql2xfdmienable; 65extern int ql2xfdmienable;
66extern int ql2xallocfwdump;
64 67
65extern void qla2x00_sp_compl(scsi_qla_host_t *, srb_t *); 68extern void qla2x00_sp_compl(scsi_qla_host_t *, srb_t *);
66 69
@@ -204,6 +207,9 @@ qla2x00_set_serdes_params(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t);
204extern int 207extern int
205qla2x00_stop_firmware(scsi_qla_host_t *); 208qla2x00_stop_firmware(scsi_qla_host_t *);
206 209
210extern int
211qla2x00_trace_control(scsi_qla_host_t *, uint16_t, dma_addr_t, uint16_t);
212
207/* 213/*
208 * Global Function Prototypes in qla_isr.c source file. 214 * Global Function Prototypes in qla_isr.c source file.
209 */ 215 */
@@ -254,9 +260,6 @@ extern int qla24xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
254extern void qla2100_fw_dump(scsi_qla_host_t *, int); 260extern void qla2100_fw_dump(scsi_qla_host_t *, int);
255extern void qla2300_fw_dump(scsi_qla_host_t *, int); 261extern void qla2300_fw_dump(scsi_qla_host_t *, int);
256extern void qla24xx_fw_dump(scsi_qla_host_t *, int); 262extern void qla24xx_fw_dump(scsi_qla_host_t *, int);
257extern void qla2100_ascii_fw_dump(scsi_qla_host_t *);
258extern void qla2300_ascii_fw_dump(scsi_qla_host_t *);
259extern void qla24xx_ascii_fw_dump(scsi_qla_host_t *);
260extern void qla2x00_dump_regs(scsi_qla_host_t *); 263extern void qla2x00_dump_regs(scsi_qla_host_t *);
261extern void qla2x00_dump_buffer(uint8_t *, uint32_t); 264extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
262extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *); 265extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *);
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index aef093db597e..880de6f380e9 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -770,29 +770,104 @@ qla24xx_chip_diag(scsi_qla_host_t *ha)
770 return rval; 770 return rval;
771} 771}
772 772
773static void 773void
774qla2x00_alloc_fw_dump(scsi_qla_host_t *ha) 774qla2x00_alloc_fw_dump(scsi_qla_host_t *ha)
775{ 775{
776 uint32_t dump_size = 0; 776 int rval;
777 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
778 eft_size;
779 dma_addr_t eft_dma;
780 void *eft;
781
782 if (ha->fw_dump) {
783 qla_printk(KERN_WARNING, ha,
784 "Firmware dump previously allocated.\n");
785 return;
786 }
777 787
778 ha->fw_dumped = 0; 788 ha->fw_dumped = 0;
789 fixed_size = mem_size = eft_size = 0;
779 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 790 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
780 dump_size = sizeof(struct qla2100_fw_dump); 791 fixed_size = sizeof(struct qla2100_fw_dump);
781 } else if (IS_QLA23XX(ha)) { 792 } else if (IS_QLA23XX(ha)) {
782 dump_size = sizeof(struct qla2300_fw_dump); 793 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
783 dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t); 794 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
784 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 795 sizeof(uint16_t);
785 dump_size = sizeof(struct qla24xx_fw_dump); 796 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
786 dump_size += (ha->fw_memory_size - 0x100000) * sizeof(uint32_t); 797 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
798 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
799 sizeof(uint32_t);
800
801 /* Allocate memory for Extended Trace Buffer. */
802 eft = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &eft_dma,
803 GFP_KERNEL);
804 if (!eft) {
805 qla_printk(KERN_WARNING, ha, "Unable to allocate "
806 "(%d KB) for EFT.\n", EFT_SIZE / 1024);
807 goto cont_alloc;
808 }
809
810 rval = qla2x00_trace_control(ha, TC_ENABLE, eft_dma,
811 EFT_NUM_BUFFERS);
812 if (rval) {
813 qla_printk(KERN_WARNING, ha, "Unable to initialize "
814 "EFT (%d).\n", rval);
815 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, eft,
816 eft_dma);
817 goto cont_alloc;
818 }
819
820 qla_printk(KERN_INFO, ha, "Allocated (%d KB) for EFT...\n",
821 EFT_SIZE / 1024);
822
823 eft_size = EFT_SIZE;
824 memset(eft, 0, eft_size);
825 ha->eft_dma = eft_dma;
826 ha->eft = eft;
787 } 827 }
828cont_alloc:
829 req_q_size = ha->request_q_length * sizeof(request_t);
830 rsp_q_size = ha->response_q_length * sizeof(response_t);
831
832 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
833 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size +
834 eft_size;
788 835
789 ha->fw_dump = vmalloc(dump_size); 836 ha->fw_dump = vmalloc(dump_size);
790 if (ha->fw_dump) 837 if (!ha->fw_dump) {
791 qla_printk(KERN_INFO, ha, "Allocated (%d KB) for firmware "
792 "dump...\n", dump_size / 1024);
793 else
794 qla_printk(KERN_WARNING, ha, "Unable to allocate (%d KB) for " 838 qla_printk(KERN_WARNING, ha, "Unable to allocate (%d KB) for "
795 "firmware dump!!!\n", dump_size / 1024); 839 "firmware dump!!!\n", dump_size / 1024);
840
841 if (ha->eft) {
842 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
843 ha->eft_dma);
844 ha->eft = NULL;
845 ha->eft_dma = 0;
846 }
847 return;
848 }
849
850 qla_printk(KERN_INFO, ha, "Allocated (%d KB) for firmware dump...\n",
851 dump_size / 1024);
852
853 ha->fw_dump_len = dump_size;
854 ha->fw_dump->signature[0] = 'Q';
855 ha->fw_dump->signature[1] = 'L';
856 ha->fw_dump->signature[2] = 'G';
857 ha->fw_dump->signature[3] = 'C';
858 ha->fw_dump->version = __constant_htonl(1);
859
860 ha->fw_dump->fixed_size = htonl(fixed_size);
861 ha->fw_dump->mem_size = htonl(mem_size);
862 ha->fw_dump->req_q_size = htonl(req_q_size);
863 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
864
865 ha->fw_dump->eft_size = htonl(eft_size);
866 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
867 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
868
869 ha->fw_dump->header_size =
870 htonl(offsetof(struct qla2xxx_fw_dump, isp));
796} 871}
797 872
798/** 873/**
@@ -810,8 +885,6 @@ qla2x00_resize_request_q(scsi_qla_host_t *ha)
810 dma_addr_t request_dma; 885 dma_addr_t request_dma;
811 request_t *request_ring; 886 request_t *request_ring;
812 887
813 qla2x00_alloc_fw_dump(ha);
814
815 /* Valid only on recent ISPs. */ 888 /* Valid only on recent ISPs. */
816 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 889 if (IS_QLA2100(ha) || IS_QLA2200(ha))
817 return; 890 return;
@@ -883,6 +956,9 @@ qla2x00_setup_chip(scsi_qla_host_t *ha)
883 &ha->fw_subminor_version, 956 &ha->fw_subminor_version,
884 &ha->fw_attributes, &ha->fw_memory_size); 957 &ha->fw_attributes, &ha->fw_memory_size);
885 qla2x00_resize_request_q(ha); 958 qla2x00_resize_request_q(ha);
959
960 if (ql2xallocfwdump)
961 qla2x00_alloc_fw_dump(ha);
886 } 962 }
887 } else { 963 } else {
888 DEBUG2(printk(KERN_INFO 964 DEBUG2(printk(KERN_INFO
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index d6cb3bd1a29a..39ddd38e7475 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -2460,3 +2460,45 @@ qla2x00_stop_firmware(scsi_qla_host_t *ha)
2460 2460
2461 return rval; 2461 return rval;
2462} 2462}
2463
2464int
2465qla2x00_trace_control(scsi_qla_host_t *ha, uint16_t ctrl, dma_addr_t eft_dma,
2466 uint16_t buffers)
2467{
2468 int rval;
2469 mbx_cmd_t mc;
2470 mbx_cmd_t *mcp = &mc;
2471
2472 if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))
2473 return QLA_FUNCTION_FAILED;
2474
2475 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
2476
2477 mcp->mb[0] = MBC_TRACE_CONTROL;
2478 mcp->mb[1] = ctrl;
2479 mcp->out_mb = MBX_1|MBX_0;
2480 mcp->in_mb = MBX_1|MBX_0;
2481 if (ctrl == TC_ENABLE) {
2482 mcp->mb[2] = LSW(eft_dma);
2483 mcp->mb[3] = MSW(eft_dma);
2484 mcp->mb[4] = LSW(MSD(eft_dma));
2485 mcp->mb[5] = MSW(MSD(eft_dma));
2486 mcp->mb[6] = buffers;
2487 mcp->mb[7] = buffers;
2488 mcp->out_mb |= MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2;
2489 }
2490 mcp->tov = 30;
2491 mcp->flags = 0;
2492 rval = qla2x00_mailbox_command(ha, mcp);
2493
2494 if (rval != QLA_SUCCESS) {
2495 DEBUG2_3_11(printk("%s(%ld): failed=%x mb[0]=%x mb[1]=%x.\n",
2496 __func__, ha->host_no, rval, mcp->mb[0], mcp->mb[1]));
2497 } else {
2498 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
2499 }
2500
2501 return rval;
2502}
2503
2504
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index ccaad0b08d35..c16154c51298 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -54,6 +54,13 @@ module_param(ql2xloginretrycount, int, S_IRUGO|S_IRUSR);
54MODULE_PARM_DESC(ql2xloginretrycount, 54MODULE_PARM_DESC(ql2xloginretrycount,
55 "Specify an alternate value for the NVRAM login retry count."); 55 "Specify an alternate value for the NVRAM login retry count.");
56 56
57int ql2xallocfwdump = 1;
58module_param(ql2xallocfwdump, int, S_IRUGO|S_IRUSR);
59MODULE_PARM_DESC(ql2xallocfwdump,
60 "Option to enable allocation of memory for a firmware dump "
61 "during HBA initialization. Memory allocation requirements "
62 "vary by ISP type. Default is 1 - allocate memory.");
63
57static void qla2x00_free_device(scsi_qla_host_t *); 64static void qla2x00_free_device(scsi_qla_host_t *);
58 65
59static void qla2x00_config_dma_addressing(scsi_qla_host_t *ha); 66static void qla2x00_config_dma_addressing(scsi_qla_host_t *ha);
@@ -1405,7 +1412,6 @@ static int qla2x00_probe_one(struct pci_dev *pdev)
1405 ha->isp_ops.read_nvram = qla2x00_read_nvram_data; 1412 ha->isp_ops.read_nvram = qla2x00_read_nvram_data;
1406 ha->isp_ops.write_nvram = qla2x00_write_nvram_data; 1413 ha->isp_ops.write_nvram = qla2x00_write_nvram_data;
1407 ha->isp_ops.fw_dump = qla2100_fw_dump; 1414 ha->isp_ops.fw_dump = qla2100_fw_dump;
1408 ha->isp_ops.ascii_fw_dump = qla2100_ascii_fw_dump;
1409 ha->isp_ops.read_optrom = qla2x00_read_optrom_data; 1415 ha->isp_ops.read_optrom = qla2x00_read_optrom_data;
1410 ha->isp_ops.write_optrom = qla2x00_write_optrom_data; 1416 ha->isp_ops.write_optrom = qla2x00_write_optrom_data;
1411 if (IS_QLA2100(ha)) { 1417 if (IS_QLA2100(ha)) {
@@ -1432,7 +1438,6 @@ static int qla2x00_probe_one(struct pci_dev *pdev)
1432 ha->isp_ops.pci_config = qla2300_pci_config; 1438 ha->isp_ops.pci_config = qla2300_pci_config;
1433 ha->isp_ops.intr_handler = qla2300_intr_handler; 1439 ha->isp_ops.intr_handler = qla2300_intr_handler;
1434 ha->isp_ops.fw_dump = qla2300_fw_dump; 1440 ha->isp_ops.fw_dump = qla2300_fw_dump;
1435 ha->isp_ops.ascii_fw_dump = qla2300_ascii_fw_dump;
1436 ha->isp_ops.beacon_on = qla2x00_beacon_on; 1441 ha->isp_ops.beacon_on = qla2x00_beacon_on;
1437 ha->isp_ops.beacon_off = qla2x00_beacon_off; 1442 ha->isp_ops.beacon_off = qla2x00_beacon_off;
1438 ha->isp_ops.beacon_blink = qla2x00_beacon_blink; 1443 ha->isp_ops.beacon_blink = qla2x00_beacon_blink;
@@ -1469,7 +1474,6 @@ static int qla2x00_probe_one(struct pci_dev *pdev)
1469 ha->isp_ops.read_nvram = qla24xx_read_nvram_data; 1474 ha->isp_ops.read_nvram = qla24xx_read_nvram_data;
1470 ha->isp_ops.write_nvram = qla24xx_write_nvram_data; 1475 ha->isp_ops.write_nvram = qla24xx_write_nvram_data;
1471 ha->isp_ops.fw_dump = qla24xx_fw_dump; 1476 ha->isp_ops.fw_dump = qla24xx_fw_dump;
1472 ha->isp_ops.ascii_fw_dump = qla24xx_ascii_fw_dump;
1473 ha->isp_ops.read_optrom = qla24xx_read_optrom_data; 1477 ha->isp_ops.read_optrom = qla24xx_read_optrom_data;
1474 ha->isp_ops.write_optrom = qla24xx_write_optrom_data; 1478 ha->isp_ops.write_optrom = qla24xx_write_optrom_data;
1475 ha->isp_ops.beacon_on = qla24xx_beacon_on; 1479 ha->isp_ops.beacon_on = qla24xx_beacon_on;
@@ -1678,6 +1682,9 @@ qla2x00_free_device(scsi_qla_host_t *ha)
1678 kthread_stop(t); 1682 kthread_stop(t);
1679 } 1683 }
1680 1684
1685 if (ha->eft)
1686 qla2x00_trace_control(ha, TC_DISABLE, 0, 0);
1687
1681 /* Stop currently executing firmware. */ 1688 /* Stop currently executing firmware. */
1682 qla2x00_stop_firmware(ha); 1689 qla2x00_stop_firmware(ha);
1683 1690
@@ -2012,6 +2019,13 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2012 /* free sp pool */ 2019 /* free sp pool */
2013 qla2x00_free_sp_pool(ha); 2020 qla2x00_free_sp_pool(ha);
2014 2021
2022 if (ha->fw_dump) {
2023 if (ha->eft)
2024 dma_free_coherent(&ha->pdev->dev,
2025 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
2026 vfree(ha->fw_dump);
2027 }
2028
2015 if (ha->sns_cmd) 2029 if (ha->sns_cmd)
2016 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 2030 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
2017 ha->sns_cmd, ha->sns_cmd_dma); 2031 ha->sns_cmd, ha->sns_cmd_dma);
@@ -2043,6 +2057,8 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2043 (ha->request_q_length + 1) * sizeof(request_t), 2057 (ha->request_q_length + 1) * sizeof(request_t),
2044 ha->request_ring, ha->request_dma); 2058 ha->request_ring, ha->request_dma);
2045 2059
2060 ha->eft = NULL;
2061 ha->eft_dma = 0;
2046 ha->sns_cmd = NULL; 2062 ha->sns_cmd = NULL;
2047 ha->sns_cmd_dma = 0; 2063 ha->sns_cmd_dma = 0;
2048 ha->ct_sns = NULL; 2064 ha->ct_sns = NULL;
@@ -2071,13 +2087,9 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2071 } 2087 }
2072 INIT_LIST_HEAD(&ha->fcports); 2088 INIT_LIST_HEAD(&ha->fcports);
2073 2089
2074 vfree(ha->fw_dump);
2075 vfree(ha->fw_dump_buffer);
2076
2077 ha->fw_dump = NULL; 2090 ha->fw_dump = NULL;
2078 ha->fw_dumped = 0; 2091 ha->fw_dumped = 0;
2079 ha->fw_dump_reading = 0; 2092 ha->fw_dump_reading = 0;
2080 ha->fw_dump_buffer = NULL;
2081 2093
2082 vfree(ha->optrom_buffer); 2094 vfree(ha->optrom_buffer);
2083} 2095}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 14:44:45 -0500