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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2007-07-26 14:41:13 -0400
committerJames Bottomley <jejb@mulgrave.localdomain>2007-10-12 14:49:34 -0400
commitc81d04c9e27966c0e4c5650d130f209bff9671f9 (patch)
treed1d07e231d49a9f603a0482d7c9e328c51c59da0 /drivers/scsi/qla2xxx
parent7f9a6bc4e9d59e7fcf03ed23f60cd81ca5d80b65 (diff)
[SCSI] qla2xxx: Collapse and simplify ISP2XXX firmware dump routines.
Add IO-base-window accessor functions. Merge duplicate RISC-pause and soft-reset code segments. Drop 'eye-watering' __iomem casting. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla2xxx')
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c1829
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h4
2 files changed, 560 insertions, 1273 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index c6680348b648..b52fa8977d91 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -38,7 +38,7 @@ qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
38} 38}
39 39
40static int 40static int
41qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, 41qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
42 uint32_t cram_size, uint32_t *ext_mem, void **nxt) 42 uint32_t cram_size, uint32_t *ext_mem, void **nxt)
43{ 43{
44 int rval; 44 int rval;
@@ -152,6 +152,106 @@ qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
152 return rval; 152 return rval;
153} 153}
154 154
155static uint32_t *
156qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
157 uint32_t count, uint32_t *buf)
158{
159 uint32_t __iomem *dmp_reg;
160
161 WRT_REG_DWORD(&reg->iobase_addr, iobase);
162 dmp_reg = &reg->iobase_window;
163 while (count--)
164 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
165
166 return buf;
167}
168
169static inline int
170qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
171{
172 int rval = QLA_SUCCESS;
173 uint32_t cnt;
174
175 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) {
176 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
177 HCCRX_CLR_HOST_INT);
178 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
179 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
180 for (cnt = 30000;
181 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
182 rval == QLA_SUCCESS; cnt--) {
183 if (cnt)
184 udelay(100);
185 else
186 rval = QLA_FUNCTION_TIMEOUT;
187 }
188 }
189
190 return rval;
191}
192
193static int
194qla24xx_soft_reset(scsi_qla_host_t *ha)
195{
196 int rval = QLA_SUCCESS;
197 uint32_t cnt;
198 uint16_t mb0, wd;
199 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
200
201 /* Reset RISC. */
202 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
203 for (cnt = 0; cnt < 30000; cnt++) {
204 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
205 break;
206
207 udelay(10);
208 }
209
210 WRT_REG_DWORD(&reg->ctrl_status,
211 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
212 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
213
214 udelay(100);
215 /* Wait for firmware to complete NVRAM accesses. */
216 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
217 for (cnt = 10000 ; cnt && mb0; cnt--) {
218 udelay(5);
219 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
220 barrier();
221 }
222
223 /* Wait for soft-reset to complete. */
224 for (cnt = 0; cnt < 30000; cnt++) {
225 if ((RD_REG_DWORD(&reg->ctrl_status) &
226 CSRX_ISP_SOFT_RESET) == 0)
227 break;
228
229 udelay(10);
230 }
231 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
232 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
233
234 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
235 rval == QLA_SUCCESS; cnt--) {
236 if (cnt)
237 udelay(100);
238 else
239 rval = QLA_FUNCTION_TIMEOUT;
240 }
241
242 return rval;
243}
244
245static inline void
246qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
247 uint16_t *buf)
248{
249 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
250
251 while (count--)
252 *buf++ = htons(RD_REG_WORD(dmp_reg++));
253}
254
155/** 255/**
156 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 256 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
157 * @ha: HA context 257 * @ha: HA context
@@ -214,88 +314,61 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
214 } 314 }
215 315
216 if (rval == QLA_SUCCESS) { 316 if (rval == QLA_SUCCESS) {
217 dmp_reg = (uint16_t __iomem *)(reg + 0); 317 dmp_reg = &reg->flash_address;
218 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 318 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
219 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 319 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
220 320
221 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 321 dmp_reg = &reg->u.isp2300.req_q_in;
222 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 322 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
223 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 323 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
224 324
225 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40); 325 dmp_reg = &reg->u.isp2300.mailbox0;
226 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 326 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
227 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 327 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
228 328
229 WRT_REG_WORD(&reg->ctrl_status, 0x40); 329 WRT_REG_WORD(&reg->ctrl_status, 0x40);
230 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 330 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
231 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
232 fw->resp_dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
233 331
234 WRT_REG_WORD(&reg->ctrl_status, 0x50); 332 WRT_REG_WORD(&reg->ctrl_status, 0x50);
235 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 333 qla2xxx_read_window(reg, 48, fw->dma_reg);
236 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
237 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
238 334
239 WRT_REG_WORD(&reg->ctrl_status, 0x00); 335 WRT_REG_WORD(&reg->ctrl_status, 0x00);
240 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 336 dmp_reg = &reg->risc_hw;
241 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 337 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
242 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 338 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
243 339
244 WRT_REG_WORD(&reg->pcr, 0x2000); 340 WRT_REG_WORD(&reg->pcr, 0x2000);
245 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 341 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
246 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
247 fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
248 342
249 WRT_REG_WORD(&reg->pcr, 0x2200); 343 WRT_REG_WORD(&reg->pcr, 0x2200);
250 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 344 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
251 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
252 fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
253 345
254 WRT_REG_WORD(&reg->pcr, 0x2400); 346 WRT_REG_WORD(&reg->pcr, 0x2400);
255 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 347 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
256 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
257 fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
258 348
259 WRT_REG_WORD(&reg->pcr, 0x2600); 349 WRT_REG_WORD(&reg->pcr, 0x2600);
260 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 350 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
261 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
262 fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
263 351
264 WRT_REG_WORD(&reg->pcr, 0x2800); 352 WRT_REG_WORD(&reg->pcr, 0x2800);
265 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 353 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
266 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
267 fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
268 354
269 WRT_REG_WORD(&reg->pcr, 0x2A00); 355 WRT_REG_WORD(&reg->pcr, 0x2A00);
270 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 356 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
271 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
272 fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
273 357
274 WRT_REG_WORD(&reg->pcr, 0x2C00); 358 WRT_REG_WORD(&reg->pcr, 0x2C00);
275 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 359 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
276 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
277 fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
278 360
279 WRT_REG_WORD(&reg->pcr, 0x2E00); 361 WRT_REG_WORD(&reg->pcr, 0x2E00);
280 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 362 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
281 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
282 fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
283 363
284 WRT_REG_WORD(&reg->ctrl_status, 0x10); 364 WRT_REG_WORD(&reg->ctrl_status, 0x10);
285 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 365 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
286 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
287 fw->frame_buf_hdw_reg[cnt] =
288 htons(RD_REG_WORD(dmp_reg++));
289 366
290 WRT_REG_WORD(&reg->ctrl_status, 0x20); 367 WRT_REG_WORD(&reg->ctrl_status, 0x20);
291 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 368 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
292 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
293 fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
294 369
295 WRT_REG_WORD(&reg->ctrl_status, 0x30); 370 WRT_REG_WORD(&reg->ctrl_status, 0x30);
296 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 371 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
297 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
298 fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
299 372
300 /* Reset RISC. */ 373 /* Reset RISC. */
301 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); 374 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
@@ -567,83 +640,59 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
567 rval = QLA_FUNCTION_TIMEOUT; 640 rval = QLA_FUNCTION_TIMEOUT;
568 } 641 }
569 if (rval == QLA_SUCCESS) { 642 if (rval == QLA_SUCCESS) {
570 dmp_reg = (uint16_t __iomem *)(reg + 0); 643 dmp_reg = &reg->flash_address;
571 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 644 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
572 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 645 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
573 646
574 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 647 dmp_reg = &reg->u.isp2100.mailbox0;
575 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 648 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
576 if (cnt == 8) { 649 if (cnt == 8)
577 dmp_reg = (uint16_t __iomem *) 650 dmp_reg = &reg->u_end.isp2200.mailbox8;
578 ((uint8_t __iomem *)reg + 0xe0); 651
579 }
580 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 652 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
581 } 653 }
582 654
583 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20); 655 dmp_reg = &reg->u.isp2100.unused_2[0];
584 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 656 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
585 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 657 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
586 658
587 WRT_REG_WORD(&reg->ctrl_status, 0x00); 659 WRT_REG_WORD(&reg->ctrl_status, 0x00);
588 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 660 dmp_reg = &reg->risc_hw;
589 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 661 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
590 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 662 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
591 663
592 WRT_REG_WORD(&reg->pcr, 0x2000); 664 WRT_REG_WORD(&reg->pcr, 0x2000);
593 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 665 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
594 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
595 fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
596 666
597 WRT_REG_WORD(&reg->pcr, 0x2100); 667 WRT_REG_WORD(&reg->pcr, 0x2100);
598 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 668 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
599 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
600 fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
601 669
602 WRT_REG_WORD(&reg->pcr, 0x2200); 670 WRT_REG_WORD(&reg->pcr, 0x2200);
603 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 671 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
604 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
605 fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
606 672
607 WRT_REG_WORD(&reg->pcr, 0x2300); 673 WRT_REG_WORD(&reg->pcr, 0x2300);
608 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 674 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
609 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
610 fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
611 675
612 WRT_REG_WORD(&reg->pcr, 0x2400); 676 WRT_REG_WORD(&reg->pcr, 0x2400);
613 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 677 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
614 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
615 fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
616 678
617 WRT_REG_WORD(&reg->pcr, 0x2500); 679 WRT_REG_WORD(&reg->pcr, 0x2500);
618 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 680 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
619 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
620 fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
621 681
622 WRT_REG_WORD(&reg->pcr, 0x2600); 682 WRT_REG_WORD(&reg->pcr, 0x2600);
623 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 683 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
624 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
625 fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
626 684
627 WRT_REG_WORD(&reg->pcr, 0x2700); 685 WRT_REG_WORD(&reg->pcr, 0x2700);
628 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 686 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
629 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
630 fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
631 687
632 WRT_REG_WORD(&reg->ctrl_status, 0x10); 688 WRT_REG_WORD(&reg->ctrl_status, 0x10);
633 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 689 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
634 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
635 fw->frame_buf_hdw_reg[cnt] =
636 htons(RD_REG_WORD(dmp_reg++));
637 690
638 WRT_REG_WORD(&reg->ctrl_status, 0x20); 691 WRT_REG_WORD(&reg->ctrl_status, 0x20);
639 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 692 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
640 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
641 fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
642 693
643 WRT_REG_WORD(&reg->ctrl_status, 0x30); 694 WRT_REG_WORD(&reg->ctrl_status, 0x30);
644 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 695 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
645 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
646 fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
647 696
648 /* Reset the ISP. */ 697 /* Reset the ISP. */
649 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); 698 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
@@ -750,7 +799,6 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
750 int rval; 799 int rval;
751 uint32_t cnt; 800 uint32_t cnt;
752 uint32_t risc_address; 801 uint32_t risc_address;
753 uint16_t mb0, wd;
754 802
755 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 803 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
756 uint32_t __iomem *dmp_reg; 804 uint32_t __iomem *dmp_reg;
@@ -782,547 +830,198 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
782 fw = &ha->fw_dump->isp.isp24; 830 fw = &ha->fw_dump->isp.isp24;
783 qla2xxx_prep_dump(ha, ha->fw_dump); 831 qla2xxx_prep_dump(ha, ha->fw_dump);
784 832
785 rval = QLA_SUCCESS;
786 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); 833 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
787 834
788 /* Pause RISC. */ 835 /* Pause RISC. */
789 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 836 rval = qla24xx_pause_risc(reg);
790 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | 837 if (rval != QLA_SUCCESS)
791 HCCRX_CLR_HOST_INT); 838 goto qla24xx_fw_dump_failed_0;
792 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ 839
793 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE); 840 /* Host interface registers. */
794 for (cnt = 30000; 841 dmp_reg = &reg->flash_addr;
795 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 && 842 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
796 rval == QLA_SUCCESS; cnt--) { 843 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
797 if (cnt) 844
798 udelay(100); 845 /* Disable interrupts. */
799 else 846 WRT_REG_DWORD(&reg->ictrl, 0);
800 rval = QLA_FUNCTION_TIMEOUT; 847 RD_REG_DWORD(&reg->ictrl);
801 } 848
802 } 849 /* Shadow registers. */
803 850 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
804 if (rval == QLA_SUCCESS) { 851 RD_REG_DWORD(&reg->iobase_addr);
805 /* Host interface registers. */ 852 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
806 dmp_reg = (uint32_t __iomem *)(reg + 0); 853 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
807 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 854
808 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 855 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
809 856 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
810 /* Disable interrupts. */ 857
811 WRT_REG_DWORD(&reg->ictrl, 0); 858 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
812 RD_REG_DWORD(&reg->ictrl); 859 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
813 860
814 /* Shadow registers. */ 861 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
815 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 862 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
816 RD_REG_DWORD(&reg->iobase_addr); 863
817 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); 864 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
818 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 865 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
819 866
820 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); 867 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
821 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 868 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
822 869
823 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); 870 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
824 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 871 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
825 872
826 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); 873 /* Mailbox registers. */
827 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 874 mbx_reg = &reg->mailbox0;
828 875 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
829 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); 876 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
830 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 877
831 878 /* Transfer sequence registers. */
832 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); 879 iter_reg = fw->xseq_gp_reg;
833 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 880 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
834 881 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
835 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); 882 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
836 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 883 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
837 884 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
838 /* Mailbox registers. */ 885 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
839 mbx_reg = &reg->mailbox0; 886 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
840 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 887 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
841 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 888
842 889 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
843 /* Transfer sequence registers. */ 890 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
844 iter_reg = fw->xseq_gp_reg; 891
845 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 892 /* Receive sequence registers. */
846 dmp_reg = &reg->iobase_window; 893 iter_reg = fw->rseq_gp_reg;
847 for (cnt = 0; cnt < 16; cnt++) 894 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
848 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 895 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
849 896 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
850 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 897 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
851 dmp_reg = &reg->iobase_window; 898 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
852 for (cnt = 0; cnt < 16; cnt++) 899 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
853 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 900 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
854 901 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
855 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 902
856 dmp_reg = &reg->iobase_window; 903 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
857 for (cnt = 0; cnt < 16; cnt++) 904 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
858 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 905 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
859 906
860 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 907 /* Command DMA registers. */
861 dmp_reg = &reg->iobase_window; 908 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
862 for (cnt = 0; cnt < 16; cnt++) 909
863 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 910 /* Queues. */
864 911 iter_reg = fw->req0_dma_reg;
865 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 912 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
866 dmp_reg = &reg->iobase_window; 913 dmp_reg = &reg->iobase_q;
867 for (cnt = 0; cnt < 16; cnt++) 914 for (cnt = 0; cnt < 7; cnt++)
868 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 915 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
869 916
870 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 917 iter_reg = fw->resp0_dma_reg;
871 dmp_reg = &reg->iobase_window; 918 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
872 for (cnt = 0; cnt < 16; cnt++) 919 dmp_reg = &reg->iobase_q;
873 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 920 for (cnt = 0; cnt < 7; cnt++)
874 921 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
875 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 922
876 dmp_reg = &reg->iobase_window; 923 iter_reg = fw->req1_dma_reg;
877 for (cnt = 0; cnt < 16; cnt++) 924 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
878 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 925 dmp_reg = &reg->iobase_q;
879 926 for (cnt = 0; cnt < 7; cnt++)
880 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 927 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
881 dmp_reg = &reg->iobase_window; 928
882 for (cnt = 0; cnt < 16; cnt++) 929 /* Transmit DMA registers. */
883 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 930 iter_reg = fw->xmt0_dma_reg;
884 931 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
885 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 932 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
886 dmp_reg = &reg->iobase_window; 933
887 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) 934 iter_reg = fw->xmt1_dma_reg;
888 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 935 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
889 936 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
890 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 937
891 dmp_reg = &reg->iobase_window; 938 iter_reg = fw->xmt2_dma_reg;
892 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 939 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
893 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 940 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
894 941
895 /* Receive sequence registers. */ 942 iter_reg = fw->xmt3_dma_reg;
896 iter_reg = fw->rseq_gp_reg; 943 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
897 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 944 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
898 dmp_reg = &reg->iobase_window; 945
899 for (cnt = 0; cnt < 16; cnt++) 946 iter_reg = fw->xmt4_dma_reg;
900 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 947 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
901 948 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
902 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 949
903 dmp_reg = &reg->iobase_window; 950 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
904 for (cnt = 0; cnt < 16; cnt++) 951
905 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 952 /* Receive DMA registers. */
906 953 iter_reg = fw->rcvt0_data_dma_reg;
907 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 954 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
908 dmp_reg = &reg->iobase_window; 955 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
909 for (cnt = 0; cnt < 16; cnt++) 956
910 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 957 iter_reg = fw->rcvt1_data_dma_reg;
911 958 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
912 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 959 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
913 dmp_reg = &reg->iobase_window; 960
914 for (cnt = 0; cnt < 16; cnt++) 961 /* RISC registers. */
915 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 962 iter_reg = fw->risc_gp_reg;
916 963 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
917 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 964 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
918 dmp_reg = &reg->iobase_window; 965 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
919 for (cnt = 0; cnt < 16; cnt++) 966 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
920 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 967 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
921 968 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
922 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 969 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
923 dmp_reg = &reg->iobase_window; 970 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
924 for (cnt = 0; cnt < 16; cnt++) 971
925 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 972 /* Local memory controller registers. */
926 973 iter_reg = fw->lmc_reg;
927 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 974 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
928 dmp_reg = &reg->iobase_window; 975 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
929 for (cnt = 0; cnt < 16; cnt++) 976 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
930 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 977 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
931 978 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
932 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 979 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
933 dmp_reg = &reg->iobase_window; 980 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
934 for (cnt = 0; cnt < 16; cnt++) 981
935 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 982 /* Fibre Protocol Module registers. */
936 983 iter_reg = fw->fpm_hdw_reg;
937 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 984 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
938 dmp_reg = &reg->iobase_window; 985 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
939 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) 986 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
940 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 987 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
941 988 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
942 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 989 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
943 dmp_reg = &reg->iobase_window; 990 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
944 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 991 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
945 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 992 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
946 993 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
947 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 994 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
948 dmp_reg = &reg->iobase_window; 995 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
949 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 996
950 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 997 /* Frame Buffer registers. */
951 998 iter_reg = fw->fb_hdw_reg;
952 /* Command DMA registers. */ 999 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
953 WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 1000 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
954 dmp_reg = &reg->iobase_window; 1001 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
955 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 1002 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
956 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1003 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
957 1004 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
958 /* Queues. */ 1005 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
959 iter_reg = fw->req0_dma_reg; 1006 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
960 WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 1007 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
961 dmp_reg = &reg->iobase_window; 1008 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
962 for (cnt = 0; cnt < 8; cnt++) 1009 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
963 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1010
964 1011 rval = qla24xx_soft_reset(ha);
965 dmp_reg = &reg->iobase_q; 1012 if (rval != QLA_SUCCESS)
966 for (cnt = 0; cnt < 7; cnt++) 1013 goto qla24xx_fw_dump_failed_0;
967 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1014
968 1015 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
969 iter_reg = fw->resp0_dma_reg; 1016 fw->ext_mem, &nxt);
970 WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 1017 if (rval != QLA_SUCCESS)
971 dmp_reg = &reg->iobase_window; 1018 goto qla24xx_fw_dump_failed_0;
972 for (cnt = 0; cnt < 8; cnt++) 1019
973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1020 nxt = qla2xxx_copy_queues(ha, nxt);
974 1021 if (ha->eft)
975 dmp_reg = &reg->iobase_q; 1022 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
976 for (cnt = 0; cnt < 7; cnt++) 1023
977 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1024qla24xx_fw_dump_failed_0:
978
979 iter_reg = fw->req1_dma_reg;
980 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
981 dmp_reg = &reg->iobase_window;
982 for (cnt = 0; cnt < 8; cnt++)
983 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
984
985 dmp_reg = &reg->iobase_q;
986 for (cnt = 0; cnt < 7; cnt++)
987 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
988
989 /* Transmit DMA registers. */
990 iter_reg = fw->xmt0_dma_reg;
991 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
992 dmp_reg = &reg->iobase_window;
993 for (cnt = 0; cnt < 16; cnt++)
994 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
995
996 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
997 dmp_reg = &reg->iobase_window;
998 for (cnt = 0; cnt < 16; cnt++)
999 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1000
1001 iter_reg = fw->xmt1_dma_reg;
1002 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1003 dmp_reg = &reg->iobase_window;
1004 for (cnt = 0; cnt < 16; cnt++)
1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1006
1007 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1008 dmp_reg = &reg->iobase_window;
1009 for (cnt = 0; cnt < 16; cnt++)
1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1011
1012 iter_reg = fw->xmt2_dma_reg;
1013 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1014 dmp_reg = &reg->iobase_window;
1015 for (cnt = 0; cnt < 16; cnt++)
1016 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1017
1018 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1019 dmp_reg = &reg->iobase_window;
1020 for (cnt = 0; cnt < 16; cnt++)
1021 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1022
1023 iter_reg = fw->xmt3_dma_reg;
1024 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1025 dmp_reg = &reg->iobase_window;
1026 for (cnt = 0; cnt < 16; cnt++)
1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1028
1029 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1030 dmp_reg = &reg->iobase_window;
1031 for (cnt = 0; cnt < 16; cnt++)
1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1033
1034 iter_reg = fw->xmt4_dma_reg;
1035 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1036 dmp_reg = &reg->iobase_window;
1037 for (cnt = 0; cnt < 16; cnt++)
1038 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1039
1040 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1041 dmp_reg = &reg->iobase_window;
1042 for (cnt = 0; cnt < 16; cnt++)
1043 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1044
1045 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1046 dmp_reg = &reg->iobase_window;
1047 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1048 fw->xmt_data_dma_reg[cnt] =
1049 htonl(RD_REG_DWORD(dmp_reg++));
1050
1051 /* Receive DMA registers. */
1052 iter_reg = fw->rcvt0_data_dma_reg;
1053 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1054 dmp_reg = &reg->iobase_window;
1055 for (cnt = 0; cnt < 16; cnt++)
1056 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1057
1058 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1059 dmp_reg = &reg->iobase_window;
1060 for (cnt = 0; cnt < 16; cnt++)
1061 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1062
1063 iter_reg = fw->rcvt1_data_dma_reg;
1064 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1065 dmp_reg = &reg->iobase_window;
1066 for (cnt = 0; cnt < 16; cnt++)
1067 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1068
1069 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1070 dmp_reg = &reg->iobase_window;
1071 for (cnt = 0; cnt < 16; cnt++)
1072 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1073
1074 /* RISC registers. */
1075 iter_reg = fw->risc_gp_reg;
1076 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1077 dmp_reg = &reg->iobase_window;
1078 for (cnt = 0; cnt < 16; cnt++)
1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1080
1081 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1082 dmp_reg = &reg->iobase_window;
1083 for (cnt = 0; cnt < 16; cnt++)
1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1085
1086 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1087 dmp_reg = &reg->iobase_window;
1088 for (cnt = 0; cnt < 16; cnt++)
1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1090
1091 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1092 dmp_reg = &reg->iobase_window;
1093 for (cnt = 0; cnt < 16; cnt++)
1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1095
1096 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1097 dmp_reg = &reg->iobase_window;
1098 for (cnt = 0; cnt < 16; cnt++)
1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1100
1101 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1102 dmp_reg = &reg->iobase_window;
1103 for (cnt = 0; cnt < 16; cnt++)
1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1105
1106 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1107 dmp_reg = &reg->iobase_window;
1108 for (cnt = 0; cnt < 16; cnt++)
1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1110
1111 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1112 dmp_reg = &reg->iobase_window;
1113 for (cnt = 0; cnt < 16; cnt++)
1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1115
1116 /* Local memory controller registers. */
1117 iter_reg = fw->lmc_reg;
1118 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1119 dmp_reg = &reg->iobase_window;
1120 for (cnt = 0; cnt < 16; cnt++)
1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1122
1123 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1124 dmp_reg = &reg->iobase_window;
1125 for (cnt = 0; cnt < 16; cnt++)
1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1127
1128 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1129 dmp_reg = &reg->iobase_window;
1130 for (cnt = 0; cnt < 16; cnt++)
1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1132
1133 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1134 dmp_reg = &reg->iobase_window;
1135 for (cnt = 0; cnt < 16; cnt++)
1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1137
1138 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1139 dmp_reg = &reg->iobase_window;
1140 for (cnt = 0; cnt < 16; cnt++)
1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1142
1143 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1144 dmp_reg = &reg->iobase_window;
1145 for (cnt = 0; cnt < 16; cnt++)
1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1147
1148 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1149 dmp_reg = &reg->iobase_window;
1150 for (cnt = 0; cnt < 16; cnt++)
1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1152
1153 /* Fibre Protocol Module registers. */
1154 iter_reg = fw->fpm_hdw_reg;
1155 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1156 dmp_reg = &reg->iobase_window;
1157 for (cnt = 0; cnt < 16; cnt++)
1158 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1159
1160 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1161 dmp_reg = &reg->iobase_window;
1162 for (cnt = 0; cnt < 16; cnt++)
1163 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1164
1165 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1166 dmp_reg = &reg->iobase_window;
1167 for (cnt = 0; cnt < 16; cnt++)
1168 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1169
1170 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1171 dmp_reg = &reg->iobase_window;
1172 for (cnt = 0; cnt < 16; cnt++)
1173 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1174
1175 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1176 dmp_reg = &reg->iobase_window;
1177 for (cnt = 0; cnt < 16; cnt++)
1178 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1179
1180 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1181 dmp_reg = &reg->iobase_window;
1182 for (cnt = 0; cnt < 16; cnt++)
1183 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1184
1185 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1186 dmp_reg = &reg->iobase_window;
1187 for (cnt = 0; cnt < 16; cnt++)
1188 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1189
1190 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1191 dmp_reg = &reg->iobase_window;
1192 for (cnt = 0; cnt < 16; cnt++)
1193 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1194
1195 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1196 dmp_reg = &reg->iobase_window;
1197 for (cnt = 0; cnt < 16; cnt++)
1198 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1199
1200 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1201 dmp_reg = &reg->iobase_window;
1202 for (cnt = 0; cnt < 16; cnt++)
1203 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1204
1205 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1206 dmp_reg = &reg->iobase_window;
1207 for (cnt = 0; cnt < 16; cnt++)
1208 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1209
1210 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1211 dmp_reg = &reg->iobase_window;
1212 for (cnt = 0; cnt < 16; cnt++)
1213 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1214
1215 /* Frame Buffer registers. */
1216 iter_reg = fw->fb_hdw_reg;
1217 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1218 dmp_reg = &reg->iobase_window;
1219 for (cnt = 0; cnt < 16; cnt++)
1220 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1221
1222 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1223 dmp_reg = &reg->iobase_window;
1224 for (cnt = 0; cnt < 16; cnt++)
1225 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1226
1227 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1228 dmp_reg = &reg->iobase_window;
1229 for (cnt = 0; cnt < 16; cnt++)
1230 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1231
1232 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1233 dmp_reg = &reg->iobase_window;
1234 for (cnt = 0; cnt < 16; cnt++)
1235 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1236
1237 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1238 dmp_reg = &reg->iobase_window;
1239 for (cnt = 0; cnt < 16; cnt++)
1240 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1241
1242 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1243 dmp_reg = &reg->iobase_window;
1244 for (cnt = 0; cnt < 16; cnt++)
1245 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1246
1247 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1248 dmp_reg = &reg->iobase_window;
1249 for (cnt = 0; cnt < 16; cnt++)
1250 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1251
1252 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1253 dmp_reg = &reg->iobase_window;
1254 for (cnt = 0; cnt < 16; cnt++)
1255 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1256
1257 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1258 dmp_reg = &reg->iobase_window;
1259 for (cnt = 0; cnt < 16; cnt++)
1260 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1261
1262 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1263 dmp_reg = &reg->iobase_window;
1264 for (cnt = 0; cnt < 16; cnt++)
1265 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1266
1267 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1268 dmp_reg = &reg->iobase_window;
1269 for (cnt = 0; cnt < 16; cnt++)
1270 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1271
1272 /* Reset RISC. */
1273 WRT_REG_DWORD(&reg->ctrl_status,
1274 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1275 for (cnt = 0; cnt < 30000; cnt++) {
1276 if ((RD_REG_DWORD(&reg->ctrl_status) &
1277 CSRX_DMA_ACTIVE) == 0)
1278 break;
1279
1280 udelay(10);
1281 }
1282
1283 WRT_REG_DWORD(&reg->ctrl_status,
1284 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1285 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1286
1287 udelay(100);
1288 /* Wait for firmware to complete NVRAM accesses. */
1289 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1290 for (cnt = 10000 ; cnt && mb0; cnt--) {
1291 udelay(5);
1292 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1293 barrier();
1294 }
1295
1296 /* Wait for soft-reset to complete. */
1297 for (cnt = 0; cnt < 30000; cnt++) {
1298 if ((RD_REG_DWORD(&reg->ctrl_status) &
1299 CSRX_ISP_SOFT_RESET) == 0)
1300 break;
1301
1302 udelay(10);
1303 }
1304 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1305 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1306 }
1307
1308 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1309 rval == QLA_SUCCESS; cnt--) {
1310 if (cnt)
1311 udelay(100);
1312 else
1313 rval = QLA_FUNCTION_TIMEOUT;
1314 }
1315
1316 if (rval == QLA_SUCCESS)
1317 rval = qla2xxx_dump_memory(ha, fw->code_ram,
1318 sizeof(fw->code_ram), fw->ext_mem, &nxt);
1319
1320 if (rval == QLA_SUCCESS) {
1321 nxt = qla2xxx_copy_queues(ha, nxt);
1322 if (ha->eft)
1323 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1324 }
1325
1326 if (rval != QLA_SUCCESS) { 1025 if (rval != QLA_SUCCESS) {
1327 qla_printk(KERN_WARNING, ha, 1026 qla_printk(KERN_WARNING, ha,
1328 "Failed to dump firmware (%x)!!!\n", rval); 1027 "Failed to dump firmware (%x)!!!\n", rval);
@@ -1346,7 +1045,6 @@ qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1346 int rval; 1045 int rval;
1347 uint32_t cnt; 1046 uint32_t cnt;
1348 uint32_t risc_address; 1047 uint32_t risc_address;
1349 uint16_t mb0, wd;
1350 1048
1351 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1049 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1352 uint32_t __iomem *dmp_reg; 1050 uint32_t __iomem *dmp_reg;
@@ -1378,654 +1076,241 @@ qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1378 fw = &ha->fw_dump->isp.isp25; 1076 fw = &ha->fw_dump->isp.isp25;
1379 qla2xxx_prep_dump(ha, ha->fw_dump); 1077 qla2xxx_prep_dump(ha, ha->fw_dump);
1380 1078
1381 rval = QLA_SUCCESS;
1382 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); 1079 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1383 1080
1384 /* Pause RISC. */ 1081 /* Pause RISC. */
1385 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 1082 rval = qla24xx_pause_risc(reg);
1386 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | 1083 if (rval != QLA_SUCCESS)
1387 HCCRX_CLR_HOST_INT); 1084 goto qla25xx_fw_dump_failed_0;
1388 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ 1085
1389 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE); 1086 /* Host interface registers. */
1390 for (cnt = 30000; 1087 dmp_reg = &reg->flash_addr;
1391 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 && 1088 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1392 rval == QLA_SUCCESS; cnt--) { 1089 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1393 if (cnt) 1090
1394 udelay(100); 1091 /* Disable interrupts. */
1395 else 1092 WRT_REG_DWORD(&reg->ictrl, 0);
1396 rval = QLA_FUNCTION_TIMEOUT; 1093 RD_REG_DWORD(&reg->ictrl);
1397 } 1094
1398 } 1095 /* Shadow registers. */
1399 1096 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1400 if (rval == QLA_SUCCESS) { 1097 RD_REG_DWORD(&reg->iobase_addr);
1401 /* Host interface registers. */ 1098 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1402 dmp_reg = (uint32_t __iomem *)(reg + 0); 1099 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1403 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1100
1404 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1101 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1405 1102 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1406 /* Disable interrupts. */ 1103
1407 WRT_REG_DWORD(&reg->ictrl, 0); 1104 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1408 RD_REG_DWORD(&reg->ictrl); 1105 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1409 1106
1410 /* Shadow registers. */ 1107 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1411 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1108 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1412 RD_REG_DWORD(&reg->iobase_addr); 1109
1413 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); 1110 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1414 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1111 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1415 1112
1416 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); 1113 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1417 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1114 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1418 1115
1419 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); 1116 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1420 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1117 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1421 1118
1422 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); 1119 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1423 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1120 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1424 1121
1425 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); 1122 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1426 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1123 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1427 1124
1428 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); 1125 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1429 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1126 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1430 1127
1431 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); 1128 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1432 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1129 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1433 1130
1434 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000); 1131 /* RISC I/O register. */
1435 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1132 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1436 1133 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1437 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000); 1134
1438 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1135 /* Mailbox registers. */
1439 1136 mbx_reg = &reg->mailbox0;
1440 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000); 1137 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1441 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1138 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1442 1139
1443 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000); 1140 /* Transfer sequence registers. */
1444 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1141 iter_reg = fw->xseq_gp_reg;
1445 1142 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1446 /* RISC I/O register. */ 1143 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1447 WRT_REG_DWORD(&reg->iobase_addr, 0x0010); 1144 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1448 RD_REG_DWORD(&reg->iobase_addr); 1145 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1449 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window)); 1146 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1450 1147 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1451 /* Mailbox registers. */ 1148 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1452 mbx_reg = &reg->mailbox0; 1149 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1453 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1150
1454 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1151 iter_reg = fw->xseq_0_reg;
1455 1152 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1456 /* Transfer sequence registers. */ 1153 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1457 iter_reg = fw->xseq_gp_reg; 1154 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1458 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 1155
1459 dmp_reg = &reg->iobase_window; 1156 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1460 for (cnt = 0; cnt < 16; cnt++) 1157
1461 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1158 /* Receive sequence registers. */
1462 1159 iter_reg = fw->rseq_gp_reg;
1463 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 1160 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1464 dmp_reg = &reg->iobase_window; 1161 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1465 for (cnt = 0; cnt < 16; cnt++) 1162 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1466 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1163 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1467 1164 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1468 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 1165 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1469 dmp_reg = &reg->iobase_window; 1166 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1470 for (cnt = 0; cnt < 16; cnt++) 1167 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1471 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1168
1472 1169 iter_reg = fw->rseq_0_reg;
1473 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 1170 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1474 dmp_reg = &reg->iobase_window; 1171 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1475 for (cnt = 0; cnt < 16; cnt++) 1172
1476 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1173 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1477 1174 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1478 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 1175
1479 dmp_reg = &reg->iobase_window; 1176 /* Auxiliary sequence registers. */
1480 for (cnt = 0; cnt < 16; cnt++) 1177 iter_reg = fw->aseq_gp_reg;
1481 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1178 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1482 1179 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1483 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 1180 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1484 dmp_reg = &reg->iobase_window; 1181 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1485 for (cnt = 0; cnt < 16; cnt++) 1182 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1486 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1183 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1487 1184 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1488 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 1185 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1489 dmp_reg = &reg->iobase_window; 1186
1490 for (cnt = 0; cnt < 16; cnt++) 1187 iter_reg = fw->aseq_0_reg;
1491 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1188 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1492 1189 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1493 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 1190
1494 dmp_reg = &reg->iobase_window; 1191 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1495 for (cnt = 0; cnt < 16; cnt++) 1192 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1496 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1193
1497 1194 /* Command DMA registers. */
1498 iter_reg = fw->xseq_0_reg; 1195 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1499 WRT_REG_DWORD(&reg->iobase_addr, 0xBFC0); 1196
1500 dmp_reg = &reg->iobase_window; 1197 /* Queues. */
1501 for (cnt = 0; cnt < 16; cnt++) 1198 iter_reg = fw->req0_dma_reg;
1502 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1199 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1503 1200 dmp_reg = &reg->iobase_q;
1504 WRT_REG_DWORD(&reg->iobase_addr, 0xBFD0); 1201 for (cnt = 0; cnt < 7; cnt++)
1505 dmp_reg = &reg->iobase_window; 1202 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1506 for (cnt = 0; cnt < 16; cnt++) 1203
1507 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1204 iter_reg = fw->resp0_dma_reg;
1508 1205 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1509 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 1206 dmp_reg = &reg->iobase_q;
1510 dmp_reg = &reg->iobase_window; 1207 for (cnt = 0; cnt < 7; cnt++)
1511 for (cnt = 0; cnt < 16; cnt++) 1208 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1512 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1209
1513 1210 iter_reg = fw->req1_dma_reg;
1514 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 1211 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1515 dmp_reg = &reg->iobase_window; 1212 dmp_reg = &reg->iobase_q;
1516 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 1213 for (cnt = 0; cnt < 7; cnt++)
1517 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1214 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1518 1215
1519 /* Receive sequence registers. */ 1216 /* Transmit DMA registers. */
1520 iter_reg = fw->rseq_gp_reg; 1217 iter_reg = fw->xmt0_dma_reg;
1521 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 1218 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1522 dmp_reg = &reg->iobase_window; 1219 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1523 for (cnt = 0; cnt < 16; cnt++) 1220
1524 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1221 iter_reg = fw->xmt1_dma_reg;
1525 1222 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1526 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 1223 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1527 dmp_reg = &reg->iobase_window; 1224
1528 for (cnt = 0; cnt < 16; cnt++) 1225 iter_reg = fw->xmt2_dma_reg;
1529 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1226 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1530 1227 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1531 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 1228
1532 dmp_reg = &reg->iobase_window; 1229 iter_reg = fw->xmt3_dma_reg;
1533 for (cnt = 0; cnt < 16; cnt++) 1230 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1534 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1231 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1535 1232
1536 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 1233 iter_reg = fw->xmt4_dma_reg;
1537 dmp_reg = &reg->iobase_window; 1234 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1538 for (cnt = 0; cnt < 16; cnt++) 1235 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1539 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1236
1540 1237 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1541 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 1238
1542 dmp_reg = &reg->iobase_window; 1239 /* Receive DMA registers. */
1543 for (cnt = 0; cnt < 16; cnt++) 1240 iter_reg = fw->rcvt0_data_dma_reg;
1544 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1241 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1545 1242 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1546 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 1243
1547 dmp_reg = &reg->iobase_window; 1244 iter_reg = fw->rcvt1_data_dma_reg;
1548 for (cnt = 0; cnt < 16; cnt++) 1245 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1549 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1246 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1550 1247
1551 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 1248 /* RISC registers. */
1552 dmp_reg = &reg->iobase_window; 1249 iter_reg = fw->risc_gp_reg;
1553 for (cnt = 0; cnt < 16; cnt++) 1250 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1554 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1251 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1555 1252 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1556 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 1253 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1557 dmp_reg = &reg->iobase_window; 1254 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1558 for (cnt = 0; cnt < 16; cnt++) 1255 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1559 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1256 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1560 1257 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1561 iter_reg = fw->rseq_0_reg; 1258
1562 WRT_REG_DWORD(&reg->iobase_addr, 0xFFC0); 1259 /* Local memory controller registers. */
1563 dmp_reg = &reg->iobase_window; 1260 iter_reg = fw->lmc_reg;
1564 for (cnt = 0; cnt < 16; cnt++) 1261 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1565 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1262 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1566 1263 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1567 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 1264 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1568 dmp_reg = &reg->iobase_window; 1265 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1569 for (cnt = 0; cnt < 16; cnt++) 1266 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1570 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1267 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1571 1268 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1572 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 1269
1573 dmp_reg = &reg->iobase_window; 1270 /* Fibre Protocol Module registers. */
1574 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 1271 iter_reg = fw->fpm_hdw_reg;
1575 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1272 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1576 1273 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1577 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 1274 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1578 dmp_reg = &reg->iobase_window; 1275 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1579 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 1276 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1580 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1277 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1581 1278 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1582 /* Auxiliary sequence registers. */ 1279 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1583 iter_reg = fw->aseq_gp_reg; 1280 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1584 WRT_REG_DWORD(&reg->iobase_addr, 0xB000); 1281 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1585 dmp_reg = &reg->iobase_window; 1282 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1586 for (cnt = 0; cnt < 16; cnt++) 1283 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1587 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1284
1588 1285 /* Frame Buffer registers. */
1589 WRT_REG_DWORD(&reg->iobase_addr, 0xB010); 1286 iter_reg = fw->fb_hdw_reg;
1590 dmp_reg = &reg->iobase_window; 1287 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1591 for (cnt = 0; cnt < 16; cnt++) 1288 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1592 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1289 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1593 1290 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1594 WRT_REG_DWORD(&reg->iobase_addr, 0xB020); 1291 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1595 dmp_reg = &reg->iobase_window; 1292 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1596 for (cnt = 0; cnt < 16; cnt++) 1293 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1597 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1294 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1598 1295 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1599 WRT_REG_DWORD(&reg->iobase_addr, 0xB030); 1296 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1600 dmp_reg = &reg->iobase_window; 1297 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1601 for (cnt = 0; cnt < 16; cnt++) 1298 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1602 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1299
1603 1300 rval = qla24xx_soft_reset(ha);
1604 WRT_REG_DWORD(&reg->iobase_addr, 0xB040); 1301 if (rval != QLA_SUCCESS)
1605 dmp_reg = &reg->iobase_window; 1302 goto qla25xx_fw_dump_failed_0;
1606 for (cnt = 0; cnt < 16; cnt++) 1303
1607 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1304 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1608 1305 fw->ext_mem, &nxt);
1609 WRT_REG_DWORD(&reg->iobase_addr, 0xB050); 1306 if (rval != QLA_SUCCESS)
1610 dmp_reg = &reg->iobase_window; 1307 goto qla25xx_fw_dump_failed_0;
1611 for (cnt = 0; cnt < 16; cnt++) 1308
1612 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1309 nxt = qla2xxx_copy_queues(ha, nxt);
1613 1310 if (ha->eft)
1614 WRT_REG_DWORD(&reg->iobase_addr, 0xB060); 1311 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1615 dmp_reg = &reg->iobase_window; 1312
1616 for (cnt = 0; cnt < 16; cnt++) 1313qla25xx_fw_dump_failed_0:
1617 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1618
1619 WRT_REG_DWORD(&reg->iobase_addr, 0xB070);
1620 dmp_reg = &reg->iobase_window;
1621 for (cnt = 0; cnt < 16; cnt++)
1622 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1623
1624 iter_reg = fw->aseq_0_reg;
1625 WRT_REG_DWORD(&reg->iobase_addr, 0xB0C0);
1626 dmp_reg = &reg->iobase_window;
1627 for (cnt = 0; cnt < 16; cnt++)
1628 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1629
1630 WRT_REG_DWORD(&reg->iobase_addr, 0xB0D0);
1631 dmp_reg = &reg->iobase_window;
1632 for (cnt = 0; cnt < 16; cnt++)
1633 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1634
1635 WRT_REG_DWORD(&reg->iobase_addr, 0xB0E0);
1636 dmp_reg = &reg->iobase_window;
1637 for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++)
1638 fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1639
1640 WRT_REG_DWORD(&reg->iobase_addr, 0xB0F0);
1641 dmp_reg = &reg->iobase_window;
1642 for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++)
1643 fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1644
1645 /* Command DMA registers. */
1646 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1647 dmp_reg = &reg->iobase_window;
1648 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1649 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1650
1651 /* Queues. */
1652 iter_reg = fw->req0_dma_reg;
1653 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1654 dmp_reg = &reg->iobase_window;
1655 for (cnt = 0; cnt < 8; cnt++)
1656 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1657
1658 dmp_reg = &reg->iobase_q;
1659 for (cnt = 0; cnt < 7; cnt++)
1660 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1661
1662 iter_reg = fw->resp0_dma_reg;
1663 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1664 dmp_reg = &reg->iobase_window;
1665 for (cnt = 0; cnt < 8; cnt++)
1666 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1667
1668 dmp_reg = &reg->iobase_q;
1669 for (cnt = 0; cnt < 7; cnt++)
1670 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1671
1672 iter_reg = fw->req1_dma_reg;
1673 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1674 dmp_reg = &reg->iobase_window;
1675 for (cnt = 0; cnt < 8; cnt++)
1676 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1677
1678 dmp_reg = &reg->iobase_q;
1679 for (cnt = 0; cnt < 7; cnt++)
1680 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1681
1682 /* Transmit DMA registers. */
1683 iter_reg = fw->xmt0_dma_reg;
1684 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1685 dmp_reg = &reg->iobase_window;
1686 for (cnt = 0; cnt < 16; cnt++)
1687 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1688
1689 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1690 dmp_reg = &reg->iobase_window;
1691 for (cnt = 0; cnt < 16; cnt++)
1692 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1693
1694 iter_reg = fw->xmt1_dma_reg;
1695 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1696 dmp_reg = &reg->iobase_window;
1697 for (cnt = 0; cnt < 16; cnt++)
1698 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1699
1700 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1701 dmp_reg = &reg->iobase_window;
1702 for (cnt = 0; cnt < 16; cnt++)
1703 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1704
1705 iter_reg = fw->xmt2_dma_reg;
1706 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1707 dmp_reg = &reg->iobase_window;
1708 for (cnt = 0; cnt < 16; cnt++)
1709 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1710
1711 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1712 dmp_reg = &reg->iobase_window;
1713 for (cnt = 0; cnt < 16; cnt++)
1714 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1715
1716 iter_reg = fw->xmt3_dma_reg;
1717 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1718 dmp_reg = &reg->iobase_window;
1719 for (cnt = 0; cnt < 16; cnt++)
1720 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1721
1722 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1723 dmp_reg = &reg->iobase_window;
1724 for (cnt = 0; cnt < 16; cnt++)
1725 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1726
1727 iter_reg = fw->xmt4_dma_reg;
1728 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1729 dmp_reg = &reg->iobase_window;
1730 for (cnt = 0; cnt < 16; cnt++)
1731 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1732
1733 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1734 dmp_reg = &reg->iobase_window;
1735 for (cnt = 0; cnt < 16; cnt++)
1736 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1737
1738 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1739 dmp_reg = &reg->iobase_window;
1740 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1741 fw->xmt_data_dma_reg[cnt] =
1742 htonl(RD_REG_DWORD(dmp_reg++));
1743
1744 /* Receive DMA registers. */
1745 iter_reg = fw->rcvt0_data_dma_reg;
1746 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1747 dmp_reg = &reg->iobase_window;
1748 for (cnt = 0; cnt < 16; cnt++)
1749 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1750
1751 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1752 dmp_reg = &reg->iobase_window;
1753 for (cnt = 0; cnt < 16; cnt++)
1754 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1755
1756 iter_reg = fw->rcvt1_data_dma_reg;
1757 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1758 dmp_reg = &reg->iobase_window;
1759 for (cnt = 0; cnt < 16; cnt++)
1760 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1761
1762 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1763 dmp_reg = &reg->iobase_window;
1764 for (cnt = 0; cnt < 16; cnt++)
1765 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1766
1767 /* RISC registers. */
1768 iter_reg = fw->risc_gp_reg;
1769 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1770 dmp_reg = &reg->iobase_window;
1771 for (cnt = 0; cnt < 16; cnt++)
1772 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1773
1774 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1775 dmp_reg = &reg->iobase_window;
1776 for (cnt = 0; cnt < 16; cnt++)
1777 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1778
1779 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1780 dmp_reg = &reg->iobase_window;
1781 for (cnt = 0; cnt < 16; cnt++)
1782 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1783
1784 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1785 dmp_reg = &reg->iobase_window;
1786 for (cnt = 0; cnt < 16; cnt++)
1787 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1788
1789 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1790 dmp_reg = &reg->iobase_window;
1791 for (cnt = 0; cnt < 16; cnt++)
1792 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1793
1794 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1795 dmp_reg = &reg->iobase_window;
1796 for (cnt = 0; cnt < 16; cnt++)
1797 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1798
1799 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1800 dmp_reg = &reg->iobase_window;
1801 for (cnt = 0; cnt < 16; cnt++)
1802 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1803
1804 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1805 dmp_reg = &reg->iobase_window;
1806 for (cnt = 0; cnt < 16; cnt++)
1807 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1808
1809 /* Local memory controller registers. */
1810 iter_reg = fw->lmc_reg;
1811 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1812 dmp_reg = &reg->iobase_window;
1813 for (cnt = 0; cnt < 16; cnt++)
1814 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1815
1816 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1817 dmp_reg = &reg->iobase_window;
1818 for (cnt = 0; cnt < 16; cnt++)
1819 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1820
1821 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1822 dmp_reg = &reg->iobase_window;
1823 for (cnt = 0; cnt < 16; cnt++)
1824 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1825
1826 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1827 dmp_reg = &reg->iobase_window;
1828 for (cnt = 0; cnt < 16; cnt++)
1829 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1830
1831 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1832 dmp_reg = &reg->iobase_window;
1833 for (cnt = 0; cnt < 16; cnt++)
1834 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1835
1836 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1837 dmp_reg = &reg->iobase_window;
1838 for (cnt = 0; cnt < 16; cnt++)
1839 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1840
1841 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1842 dmp_reg = &reg->iobase_window;
1843 for (cnt = 0; cnt < 16; cnt++)
1844 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1845
1846 WRT_REG_DWORD(&reg->iobase_addr, 0x3070);
1847 dmp_reg = &reg->iobase_window;
1848 for (cnt = 0; cnt < 16; cnt++)
1849 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1850
1851 /* Fibre Protocol Module registers. */
1852 iter_reg = fw->fpm_hdw_reg;
1853 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1854 dmp_reg = &reg->iobase_window;
1855 for (cnt = 0; cnt < 16; cnt++)
1856 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1857
1858 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1859 dmp_reg = &reg->iobase_window;
1860 for (cnt = 0; cnt < 16; cnt++)
1861 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1862
1863 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1864 dmp_reg = &reg->iobase_window;
1865 for (cnt = 0; cnt < 16; cnt++)
1866 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1867
1868 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1869 dmp_reg = &reg->iobase_window;
1870 for (cnt = 0; cnt < 16; cnt++)
1871 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1872
1873 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1874 dmp_reg = &reg->iobase_window;
1875 for (cnt = 0; cnt < 16; cnt++)
1876 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1877
1878 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1879 dmp_reg = &reg->iobase_window;
1880 for (cnt = 0; cnt < 16; cnt++)
1881 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1882
1883 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1884 dmp_reg = &reg->iobase_window;
1885 for (cnt = 0; cnt < 16; cnt++)
1886 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1887
1888 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1889 dmp_reg = &reg->iobase_window;
1890 for (cnt = 0; cnt < 16; cnt++)
1891 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1892
1893 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1894 dmp_reg = &reg->iobase_window;
1895 for (cnt = 0; cnt < 16; cnt++)
1896 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1897
1898 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1899 dmp_reg = &reg->iobase_window;
1900 for (cnt = 0; cnt < 16; cnt++)
1901 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1902
1903 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1904 dmp_reg = &reg->iobase_window;
1905 for (cnt = 0; cnt < 16; cnt++)
1906 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1907
1908 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1909 dmp_reg = &reg->iobase_window;
1910 for (cnt = 0; cnt < 16; cnt++)
1911 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1912
1913 /* Frame Buffer registers. */
1914 iter_reg = fw->fb_hdw_reg;
1915 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1916 dmp_reg = &reg->iobase_window;
1917 for (cnt = 0; cnt < 16; cnt++)
1918 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1919
1920 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1921 dmp_reg = &reg->iobase_window;
1922 for (cnt = 0; cnt < 16; cnt++)
1923 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1924
1925 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1926 dmp_reg = &reg->iobase_window;
1927 for (cnt = 0; cnt < 16; cnt++)
1928 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1929
1930 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1931 dmp_reg = &reg->iobase_window;
1932 for (cnt = 0; cnt < 16; cnt++)
1933 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1934
1935 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1936 dmp_reg = &reg->iobase_window;
1937 for (cnt = 0; cnt < 16; cnt++)
1938 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1939
1940 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1941 dmp_reg = &reg->iobase_window;
1942 for (cnt = 0; cnt < 16; cnt++)
1943 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1944
1945 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1946 dmp_reg = &reg->iobase_window;
1947 for (cnt = 0; cnt < 16; cnt++)
1948 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1949
1950 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1951 dmp_reg = &reg->iobase_window;
1952 for (cnt = 0; cnt < 16; cnt++)
1953 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1954
1955 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1956 dmp_reg = &reg->iobase_window;
1957 for (cnt = 0; cnt < 16; cnt++)
1958 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1959
1960 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1961 dmp_reg = &reg->iobase_window;
1962 for (cnt = 0; cnt < 16; cnt++)
1963 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1964
1965 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1966 dmp_reg = &reg->iobase_window;
1967 for (cnt = 0; cnt < 16; cnt++)
1968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1969
1970 WRT_REG_DWORD(&reg->iobase_addr, 0x6F00);
1971 dmp_reg = &reg->iobase_window;
1972 for (cnt = 0; cnt < 16; cnt++)
1973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1974
1975 /* Reset RISC. */
1976 WRT_REG_DWORD(&reg->ctrl_status,
1977 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1978 for (cnt = 0; cnt < 30000; cnt++) {
1979 if ((RD_REG_DWORD(&reg->ctrl_status) &
1980 CSRX_DMA_ACTIVE) == 0)
1981 break;
1982
1983 udelay(10);
1984 }
1985
1986 WRT_REG_DWORD(&reg->ctrl_status,
1987 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1988 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1989
1990 udelay(100);
1991 /* Wait for firmware to complete NVRAM accesses. */
1992 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1993 for (cnt = 10000 ; cnt && mb0; cnt--) {
1994 udelay(5);
1995 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1996 barrier();
1997 }
1998
1999 /* Wait for soft-reset to complete. */
2000 for (cnt = 0; cnt < 30000; cnt++) {
2001 if ((RD_REG_DWORD(&reg->ctrl_status) &
2002 CSRX_ISP_SOFT_RESET) == 0)
2003 break;
2004
2005 udelay(10);
2006 }
2007 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2008 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
2009 }
2010
2011 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2012 rval == QLA_SUCCESS; cnt--) {
2013 if (cnt)
2014 udelay(100);
2015 else
2016 rval = QLA_FUNCTION_TIMEOUT;
2017 }
2018
2019 if (rval == QLA_SUCCESS)
2020 rval = qla2xxx_dump_memory(ha, fw->code_ram,
2021 sizeof(fw->code_ram), fw->ext_mem, &nxt);
2022
2023 if (rval == QLA_SUCCESS) {
2024 nxt = qla2xxx_copy_queues(ha, nxt);
2025 if (ha->eft)
2026 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
2027 }
2028
2029 if (rval != QLA_SUCCESS) { 1314 if (rval != QLA_SUCCESS) {
2030 qla_printk(KERN_WARNING, ha, 1315 qla_printk(KERN_WARNING, ha,
2031 "Failed to dump firmware (%x)!!!\n", rval); 1316 "Failed to dump firmware (%x)!!!\n", rval);
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index c1964866a423..4af08561883d 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -316,7 +316,9 @@ struct device_reg_2xxx {
316 } u; 316 } u;
317 317
318 uint16_t fpm_diag_config; 318 uint16_t fpm_diag_config;
319 uint16_t unused_5[0x6]; /* Gap */ 319 uint16_t unused_5[0x4]; /* Gap */
320 uint16_t risc_hw;
321 uint16_t unused_5_1; /* Gap */
320 uint16_t pcr; /* Processor Control Register. */ 322 uint16_t pcr; /* Processor Control Register. */
321 uint16_t unused_6[0x5]; /* Gap */ 323 uint16_t unused_6[0x5]; /* Gap */
322 uint16_t mctr; /* Memory Configuration and Timing. */ 324 uint16_t mctr; /* Memory Configuration and Timing. */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-27 02:40:20 -0400