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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2009-01-05 14:18:11 -0500
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2009-01-07 16:51:44 -0500
commit3a03eb797ce76ae8868a1497e9e746ad0add1e3b (patch)
tree2dc17c39b7c1e35248b35f7433de8711f0b6656a /drivers/scsi/qla2xxx
parent444786d7fdd770f67e29a068ec8ee981d323f7a7 (diff)
[SCSI] qla2xxx: Add ISP81XX support.
Codes to support new FCoE boards. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers/scsi/qla2xxx')
-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c26
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c324
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.h40
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h21
-rw-r--r--drivers/scsi/qla2xxx/qla_dfs.c3
-rw-r--r--drivers/scsi/qla2xxx/qla_fw.h294
-rw-r--r--drivers/scsi/qla2xxx/qla_gbl.h5
-rw-r--r--drivers/scsi/qla2xxx/qla_gs.c9
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c280
-rw-r--r--drivers/scsi/qla2xxx/qla_isr.c60
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c25
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c113
-rw-r--r--drivers/scsi/qla2xxx/qla_sup.c143
13 files changed, 1234 insertions, 109 deletions
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index cd53627cc761..c7acef50d5da 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -303,7 +303,7 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj,
303 else if (start == (ha->flt_region_boot * 4) || 303 else if (start == (ha->flt_region_boot * 4) ||
304 start == (ha->flt_region_fw * 4)) 304 start == (ha->flt_region_fw * 4))
305 valid = 1; 305 valid = 1;
306 else if (IS_QLA25XX(ha) && 306 else if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) &&
307 start == (ha->flt_region_vpd_nvram * 4)) 307 start == (ha->flt_region_vpd_nvram * 4))
308 valid = 1; 308 valid = 1;
309 if (!valid) { 309 if (!valid) {
@@ -815,6 +815,21 @@ qla2x00_total_isp_aborts_show(struct device *dev,
815 ha->qla_stats.total_isp_aborts); 815 ha->qla_stats.total_isp_aborts);
816} 816}
817 817
818static ssize_t
819qla2x00_mpi_version_show(struct device *dev, struct device_attribute *attr,
820 char *buf)
821{
822 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
823 struct qla_hw_data *ha = vha->hw;
824
825 if (!IS_QLA81XX(ha))
826 return snprintf(buf, PAGE_SIZE, "\n");
827
828 return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x (%x)\n",
829 ha->mpi_version[0], ha->mpi_version[1], ha->mpi_version[2],
830 ha->mpi_version[3], ha->mpi_capabilities);
831}
832
818static DEVICE_ATTR(driver_version, S_IRUGO, qla2x00_drvr_version_show, NULL); 833static DEVICE_ATTR(driver_version, S_IRUGO, qla2x00_drvr_version_show, NULL);
819static DEVICE_ATTR(fw_version, S_IRUGO, qla2x00_fw_version_show, NULL); 834static DEVICE_ATTR(fw_version, S_IRUGO, qla2x00_fw_version_show, NULL);
820static DEVICE_ATTR(serial_num, S_IRUGO, qla2x00_serial_num_show, NULL); 835static DEVICE_ATTR(serial_num, S_IRUGO, qla2x00_serial_num_show, NULL);
@@ -839,6 +854,7 @@ static DEVICE_ATTR(optrom_fw_version, S_IRUGO, qla2x00_optrom_fw_version_show,
839 NULL); 854 NULL);
840static DEVICE_ATTR(total_isp_aborts, S_IRUGO, qla2x00_total_isp_aborts_show, 855static DEVICE_ATTR(total_isp_aborts, S_IRUGO, qla2x00_total_isp_aborts_show,
841 NULL); 856 NULL);
857static DEVICE_ATTR(mpi_version, S_IRUGO, qla2x00_mpi_version_show, NULL);
842 858
843struct device_attribute *qla2x00_host_attrs[] = { 859struct device_attribute *qla2x00_host_attrs[] = {
844 &dev_attr_driver_version, 860 &dev_attr_driver_version,
@@ -858,6 +874,7 @@ struct device_attribute *qla2x00_host_attrs[] = {
858 &dev_attr_optrom_fcode_version, 874 &dev_attr_optrom_fcode_version,
859 &dev_attr_optrom_fw_version, 875 &dev_attr_optrom_fw_version,
860 &dev_attr_total_isp_aborts, 876 &dev_attr_total_isp_aborts,
877 &dev_attr_mpi_version,
861 NULL, 878 NULL,
862}; 879};
863 880
@@ -892,6 +909,9 @@ qla2x00_get_host_speed(struct Scsi_Host *shost)
892 case PORT_SPEED_8GB: 909 case PORT_SPEED_8GB:
893 speed = FC_PORTSPEED_8GBIT; 910 speed = FC_PORTSPEED_8GBIT;
894 break; 911 break;
912 case PORT_SPEED_10GB:
913 speed = FC_PORTSPEED_10GBIT;
914 break;
895 } 915 }
896 fc_host_speed(shost) = speed; 916 fc_host_speed(shost) = speed;
897} 917}
@@ -1382,7 +1402,9 @@ qla2x00_init_host_attr(scsi_qla_host_t *vha)
1382 fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports; 1402 fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports;
1383 fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count; 1403 fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count;
1384 1404
1385 if (IS_QLA25XX(ha)) 1405 if (IS_QLA81XX(ha))
1406 speed = FC_PORTSPEED_10GBIT;
1407 else if (IS_QLA25XX(ha))
1386 speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT | 1408 speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT |
1387 FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT; 1409 FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT;
1388 else if (IS_QLA24XX_TYPE(ha)) 1410 else if (IS_QLA24XX_TYPE(ha))
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 4f478364fa43..34760f8d4f17 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -1324,6 +1324,330 @@ qla25xx_fw_dump_failed:
1324 if (!hardware_locked) 1324 if (!hardware_locked)
1325 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1326} 1326}
1327
1328void
1329qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1330{
1331 int rval;
1332 uint32_t cnt;
1333 uint32_t risc_address;
1334 struct qla_hw_data *ha = vha->hw;
1335 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1336 uint32_t __iomem *dmp_reg;
1337 uint32_t *iter_reg;
1338 uint16_t __iomem *mbx_reg;
1339 unsigned long flags;
1340 struct qla81xx_fw_dump *fw;
1341 uint32_t ext_mem_cnt;
1342 void *nxt, *nxt_chain;
1343 uint32_t *last_chain = NULL;
1344 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1345
1346 risc_address = ext_mem_cnt = 0;
1347 flags = 0;
1348
1349 if (!hardware_locked)
1350 spin_lock_irqsave(&ha->hardware_lock, flags);
1351
1352 if (!ha->fw_dump) {
1353 qla_printk(KERN_WARNING, ha,
1354 "No buffer available for dump!!!\n");
1355 goto qla81xx_fw_dump_failed;
1356 }
1357
1358 if (ha->fw_dumped) {
1359 qla_printk(KERN_WARNING, ha,
1360 "Firmware has been previously dumped (%p) -- ignoring "
1361 "request...\n", ha->fw_dump);
1362 goto qla81xx_fw_dump_failed;
1363 }
1364 fw = &ha->fw_dump->isp.isp81;
1365 qla2xxx_prep_dump(ha, ha->fw_dump);
1366
1367 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1368
1369 /* Pause RISC. */
1370 rval = qla24xx_pause_risc(reg);
1371 if (rval != QLA_SUCCESS)
1372 goto qla81xx_fw_dump_failed_0;
1373
1374 /* Host/Risc registers. */
1375 iter_reg = fw->host_risc_reg;
1376 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1377 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1378
1379 /* PCIe registers. */
1380 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1381 RD_REG_DWORD(&reg->iobase_addr);
1382 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1383 dmp_reg = &reg->iobase_c4;
1384 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1385 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1386 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1387 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1388
1389 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1390 RD_REG_DWORD(&reg->iobase_window);
1391
1392 /* Host interface registers. */
1393 dmp_reg = &reg->flash_addr;
1394 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1395 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1396
1397 /* Disable interrupts. */
1398 WRT_REG_DWORD(&reg->ictrl, 0);
1399 RD_REG_DWORD(&reg->ictrl);
1400
1401 /* Shadow registers. */
1402 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1403 RD_REG_DWORD(&reg->iobase_addr);
1404 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1405 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1406
1407 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1408 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1409
1410 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1411 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1412
1413 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1414 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1415
1416 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1417 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1418
1419 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1420 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1421
1422 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1423 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1424
1425 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1426 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1427
1428 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1429 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1430
1431 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1432 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1433
1434 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1435 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1436
1437 /* RISC I/O register. */
1438 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1439 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1440
1441 /* Mailbox registers. */
1442 mbx_reg = &reg->mailbox0;
1443 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1444 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1445
1446 /* Transfer sequence registers. */
1447 iter_reg = fw->xseq_gp_reg;
1448 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1454 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1455 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1456
1457 iter_reg = fw->xseq_0_reg;
1458 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1459 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1460 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1461
1462 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1463
1464 /* Receive sequence registers. */
1465 iter_reg = fw->rseq_gp_reg;
1466 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1467 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1468 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1469 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1470 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1471 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1472 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1473 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1474
1475 iter_reg = fw->rseq_0_reg;
1476 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1477 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1478
1479 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1480 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1481
1482 /* Auxiliary sequence registers. */
1483 iter_reg = fw->aseq_gp_reg;
1484 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1485 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1486 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1487 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1488 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1489 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1490 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1491 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1492
1493 iter_reg = fw->aseq_0_reg;
1494 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1495 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1496
1497 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1498 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1499
1500 /* Command DMA registers. */
1501 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1502
1503 /* Queues. */
1504 iter_reg = fw->req0_dma_reg;
1505 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1506 dmp_reg = &reg->iobase_q;
1507 for (cnt = 0; cnt < 7; cnt++)
1508 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1509
1510 iter_reg = fw->resp0_dma_reg;
1511 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1512 dmp_reg = &reg->iobase_q;
1513 for (cnt = 0; cnt < 7; cnt++)
1514 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1515
1516 iter_reg = fw->req1_dma_reg;
1517 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1518 dmp_reg = &reg->iobase_q;
1519 for (cnt = 0; cnt < 7; cnt++)
1520 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1521
1522 /* Transmit DMA registers. */
1523 iter_reg = fw->xmt0_dma_reg;
1524 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1525 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1526
1527 iter_reg = fw->xmt1_dma_reg;
1528 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1529 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1530
1531 iter_reg = fw->xmt2_dma_reg;
1532 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1533 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1534
1535 iter_reg = fw->xmt3_dma_reg;
1536 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1537 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1538
1539 iter_reg = fw->xmt4_dma_reg;
1540 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1541 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1542
1543 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1544
1545 /* Receive DMA registers. */
1546 iter_reg = fw->rcvt0_data_dma_reg;
1547 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1548 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1549
1550 iter_reg = fw->rcvt1_data_dma_reg;
1551 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1552 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1553
1554 /* RISC registers. */
1555 iter_reg = fw->risc_gp_reg;
1556 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1557 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1558 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1559 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1560 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1561 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1562 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1563 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1564
1565 /* Local memory controller registers. */
1566 iter_reg = fw->lmc_reg;
1567 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1568 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1569 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1570 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1571 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1572 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1573 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1574 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1575
1576 /* Fibre Protocol Module registers. */
1577 iter_reg = fw->fpm_hdw_reg;
1578 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1579 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1580 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1581 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1582 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1583 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1584 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1585 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1586 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1587 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1588 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1589 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1590 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1591 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1592
1593 /* Frame Buffer registers. */
1594 iter_reg = fw->fb_hdw_reg;
1595 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1596 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1597 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1598 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1599 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1600 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1601 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1602 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1603 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1604 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1605 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1606 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1607 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1608
1609 /* Multi queue registers */
1610 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1611 &last_chain);
1612
1613 rval = qla24xx_soft_reset(ha);
1614 if (rval != QLA_SUCCESS)
1615 goto qla81xx_fw_dump_failed_0;
1616
1617 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1618 &nxt);
1619 if (rval != QLA_SUCCESS)
1620 goto qla81xx_fw_dump_failed_0;
1621
1622 nxt = qla2xxx_copy_queues(ha, nxt);
1623
1624 nxt = qla24xx_copy_eft(ha, nxt);
1625
1626 /* Chain entries -- started with MQ. */
1627 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1628 if (last_chain) {
1629 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1630 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1631 }
1632
1633qla81xx_fw_dump_failed_0:
1634 if (rval != QLA_SUCCESS) {
1635 qla_printk(KERN_WARNING, ha,
1636 "Failed to dump firmware (%x)!!!\n", rval);
1637 ha->fw_dumped = 0;
1638
1639 } else {
1640 qla_printk(KERN_INFO, ha,
1641 "Firmware dump saved to temp buffer (%ld/%p).\n",
1642 base_vha->host_no, ha->fw_dump);
1643 ha->fw_dumped = 1;
1644 }
1645
1646qla81xx_fw_dump_failed:
1647 if (!hardware_locked)
1648 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1649}
1650
1327/****************************************************************************/ 1651/****************************************************************************/
1328/* Driver Debug Functions. */ 1652/* Driver Debug Functions. */
1329/****************************************************************************/ 1653/****************************************************************************/
diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h
index c1794a70a45f..f660dd70b72e 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.h
+++ b/drivers/scsi/qla2xxx/qla_dbg.h
@@ -251,6 +251,45 @@ struct qla25xx_fw_dump {
251 uint32_t ext_mem[1]; 251 uint32_t ext_mem[1];
252}; 252};
253 253
254struct qla81xx_fw_dump {
255 uint32_t host_status;
256 uint32_t host_risc_reg[32];
257 uint32_t pcie_regs[4];
258 uint32_t host_reg[32];
259 uint32_t shadow_reg[11];
260 uint32_t risc_io_reg;
261 uint16_t mailbox_reg[32];
262 uint32_t xseq_gp_reg[128];
263 uint32_t xseq_0_reg[48];
264 uint32_t xseq_1_reg[16];
265 uint32_t rseq_gp_reg[128];
266 uint32_t rseq_0_reg[32];
267 uint32_t rseq_1_reg[16];
268 uint32_t rseq_2_reg[16];
269 uint32_t aseq_gp_reg[128];
270 uint32_t aseq_0_reg[32];
271 uint32_t aseq_1_reg[16];
272 uint32_t aseq_2_reg[16];
273 uint32_t cmd_dma_reg[16];
274 uint32_t req0_dma_reg[15];
275 uint32_t resp0_dma_reg[15];
276 uint32_t req1_dma_reg[15];
277 uint32_t xmt0_dma_reg[32];
278 uint32_t xmt1_dma_reg[32];
279 uint32_t xmt2_dma_reg[32];
280 uint32_t xmt3_dma_reg[32];
281 uint32_t xmt4_dma_reg[32];
282 uint32_t xmt_data_dma_reg[16];
283 uint32_t rcvt0_data_dma_reg[32];
284 uint32_t rcvt1_data_dma_reg[32];
285 uint32_t risc_gp_reg[128];
286 uint32_t lmc_reg[128];
287 uint32_t fpm_hdw_reg[224];
288 uint32_t fb_hdw_reg[208];
289 uint32_t code_ram[0x2000];
290 uint32_t ext_mem[1];
291};
292
254#define EFT_NUM_BUFFERS 4 293#define EFT_NUM_BUFFERS 4
255#define EFT_BYTES_PER_BUFFER 0x4000 294#define EFT_BYTES_PER_BUFFER 0x4000
256#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 295#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
@@ -313,5 +352,6 @@ struct qla2xxx_fw_dump {
313 struct qla2300_fw_dump isp23; 352 struct qla2300_fw_dump isp23;
314 struct qla24xx_fw_dump isp24; 353 struct qla24xx_fw_dump isp24;
315 struct qla25xx_fw_dump isp25; 354 struct qla25xx_fw_dump isp25;
355 struct qla81xx_fw_dump isp81;
316 } isp; 356 } isp;
317}; 357};
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index 6b3762243689..023ee77fb027 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -2303,6 +2303,7 @@ struct qla_hw_data {
2303#define PORT_SPEED_2GB 0x01 2303#define PORT_SPEED_2GB 0x01
2304#define PORT_SPEED_4GB 0x03 2304#define PORT_SPEED_4GB 0x03
2305#define PORT_SPEED_8GB 0x04 2305#define PORT_SPEED_8GB 0x04
2306#define PORT_SPEED_10GB 0x13
2306 uint16_t link_data_rate; /* F/W operating speed */ 2307 uint16_t link_data_rate; /* F/W operating speed */
2307 2308
2308 uint8_t current_topology; 2309 uint8_t current_topology;
@@ -2322,6 +2323,7 @@ struct qla_hw_data {
2322 2323
2323#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2324#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2324#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 2325#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2326#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2325 uint32_t device_type; 2327 uint32_t device_type;
2326#define DT_ISP2100 BIT_0 2328#define DT_ISP2100 BIT_0
2327#define DT_ISP2200 BIT_1 2329#define DT_ISP2200 BIT_1
@@ -2336,7 +2338,8 @@ struct qla_hw_data {
2336#define DT_ISP5432 BIT_10 2338#define DT_ISP5432 BIT_10
2337#define DT_ISP2532 BIT_11 2339#define DT_ISP2532 BIT_11
2338#define DT_ISP8432 BIT_12 2340#define DT_ISP8432 BIT_12
2339#define DT_ISP_LAST (DT_ISP8432 << 1) 2341#define DT_ISP8001 BIT_13
2342#define DT_ISP_LAST (DT_ISP8001 << 1)
2340 2343
2341#define DT_IIDMA BIT_26 2344#define DT_IIDMA BIT_26
2342#define DT_FWI2 BIT_27 2345#define DT_FWI2 BIT_27
@@ -2358,6 +2361,7 @@ struct qla_hw_data {
2358#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2361#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2359#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2362#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2360#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 2363#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2364#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2361 2365
2362#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2366#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2363 IS_QLA6312(ha) || IS_QLA6322(ha)) 2367 IS_QLA6312(ha) || IS_QLA6322(ha))
@@ -2367,9 +2371,10 @@ struct qla_hw_data {
2367#define IS_QLA84XX(ha) (IS_QLA8432(ha)) 2371#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2368#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 2372#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2369 IS_QLA84XX(ha)) 2373 IS_QLA84XX(ha))
2374#define IS_QLA81XX(ha) (IS_QLA8001(ha))
2370#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 2375#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2371 IS_QLA25XX(ha)) 2376 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2372#define IS_NOPOLLING_TYPE(ha) (IS_QLA25XX(ha) && \ 2377#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2373 (ha)->flags.msix_enabled) 2378 (ha)->flags.msix_enabled)
2374 2379
2375#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 2380#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
@@ -2468,6 +2473,9 @@ struct qla_hw_data {
2468 uint8_t fw_seriallink_options[4]; 2473 uint8_t fw_seriallink_options[4];
2469 uint16_t fw_seriallink_options24[4]; 2474 uint16_t fw_seriallink_options24[4];
2470 2475
2476 uint8_t mpi_version[4];
2477 uint32_t mpi_capabilities;
2478
2471 /* Firmware dump information. */ 2479 /* Firmware dump information. */
2472 struct qla2xxx_fw_dump *fw_dump; 2480 struct qla2xxx_fw_dump *fw_dump;
2473 uint32_t fw_dump_len; 2481 uint32_t fw_dump_len;
@@ -2515,6 +2523,12 @@ struct qla_hw_data {
2515 uint8_t fcode_revision[16]; 2523 uint8_t fcode_revision[16];
2516 uint32_t fw_revision[4]; 2524 uint32_t fw_revision[4];
2517 2525
2526 /* Offsets for flash/nvram access (set to ~0 if not used). */
2527 uint32_t flash_conf_off;
2528 uint32_t flash_data_off;
2529 uint32_t nvram_conf_off;
2530 uint32_t nvram_data_off;
2531
2518 uint32_t fdt_wrt_disable; 2532 uint32_t fdt_wrt_disable;
2519 uint32_t fdt_erase_cmd; 2533 uint32_t fdt_erase_cmd;
2520 uint32_t fdt_block_size; 2534 uint32_t fdt_block_size;
@@ -2729,6 +2743,7 @@ typedef struct scsi_qla_host {
2729#define OPTROM_SIZE_2322 0x100000 2743#define OPTROM_SIZE_2322 0x100000
2730#define OPTROM_SIZE_24XX 0x100000 2744#define OPTROM_SIZE_24XX 0x100000
2731#define OPTROM_SIZE_25XX 0x200000 2745#define OPTROM_SIZE_25XX 0x200000
2746#define OPTROM_SIZE_81XX 0x400000
2732 2747
2733#include "qla_gbl.h" 2748#include "qla_gbl.h"
2734#include "qla_dbg.h" 2749#include "qla_dbg.h"
diff --git a/drivers/scsi/qla2xxx/qla_dfs.c b/drivers/scsi/qla2xxx/qla_dfs.c
index 0e366a1b44b3..c66036da7d2b 100644
--- a/drivers/scsi/qla2xxx/qla_dfs.c
+++ b/drivers/scsi/qla2xxx/qla_dfs.c
@@ -113,7 +113,8 @@ int
113qla2x00_dfs_setup(scsi_qla_host_t *vha) 113qla2x00_dfs_setup(scsi_qla_host_t *vha)
114{ 114{
115 struct qla_hw_data *ha = vha->hw; 115 struct qla_hw_data *ha = vha->hw;
116 if (!IS_QLA25XX(ha)) 116
117 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
117 goto out; 118 goto out;
118 if (!ha->fce) 119 if (!ha->fce)
119 goto out; 120 goto out;
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
index ee1f1e794c2d..7abb045a0410 100644
--- a/drivers/scsi/qla2xxx/qla_fw.h
+++ b/drivers/scsi/qla2xxx/qla_fw.h
@@ -1215,9 +1215,10 @@ struct qla_fdt_layout {
1215 1215
1216struct qla_flt_location { 1216struct qla_flt_location {
1217 uint8_t sig[4]; 1217 uint8_t sig[4];
1218 uint32_t start_lo; 1218 uint16_t start_lo;
1219 uint32_t start_hi; 1219 uint16_t start_hi;
1220 uint16_t unused; 1220 uint8_t version;
1221 uint8_t unused[5];
1221 uint16_t checksum; 1222 uint16_t checksum;
1222}; 1223};
1223 1224
@@ -1390,4 +1391,291 @@ struct access_chip_rsp_84xx {
1390 1391
1391 uint32_t reserved[12]; 1392 uint32_t reserved[12];
1392}; 1393};
1394
1395/* 81XX Support **************************************************************/
1396
1397#define MBA_DCBX_START 0x8016
1398#define MBA_DCBX_COMPLETE 0x8030
1399#define MBA_FCF_CONF_ERR 0x8031
1400#define MBA_DCBX_PARAM_UPDATE 0x8032
1401#define MBA_IDC_COMPLETE 0x8100
1402#define MBA_IDC_NOTIFY 0x8101
1403#define MBA_IDC_TIME_EXT 0x8102
1404
1405struct nvram_81xx {
1406 /* NVRAM header. */
1407 uint8_t id[4];
1408 uint16_t nvram_version;
1409 uint16_t reserved_0;
1410
1411 /* Firmware Initialization Control Block. */
1412 uint16_t version;
1413 uint16_t reserved_1;
1414 uint16_t frame_payload_size;
1415 uint16_t execution_throttle;
1416 uint16_t exchange_count;
1417 uint16_t reserved_2;
1418
1419 uint8_t port_name[WWN_SIZE];
1420 uint8_t node_name[WWN_SIZE];
1421
1422 uint16_t login_retry_count;
1423 uint16_t reserved_3;
1424 uint16_t interrupt_delay_timer;
1425 uint16_t login_timeout;
1426
1427 uint32_t firmware_options_1;
1428 uint32_t firmware_options_2;
1429 uint32_t firmware_options_3;
1430
1431 uint16_t reserved_4[4];
1432
1433 /* Offset 64. */
1434 uint8_t enode_mac[6];
1435 uint16_t reserved_5[5];
1436
1437 /* Offset 80. */
1438 uint16_t reserved_6[24];
1439
1440 /* Offset 128. */
1441 uint16_t reserved_7[64];
1442
1443 /*
1444 * BIT 0 = Enable spinup delay
1445 * BIT 1 = Disable BIOS
1446 * BIT 2 = Enable Memory Map BIOS
1447 * BIT 3 = Enable Selectable Boot
1448 * BIT 4 = Disable RISC code load
1449 * BIT 5 = Disable Serdes
1450 * BIT 6 = Opt boot mode
1451 * BIT 7 = Interrupt enable
1452 *
1453 * BIT 8 = EV Control enable
1454 * BIT 9 = Enable lip reset
1455 * BIT 10 = Enable lip full login
1456 * BIT 11 = Enable target reset
1457 * BIT 12 = Stop firmware
1458 * BIT 13 = Enable nodename option
1459 * BIT 14 = Default WWPN valid
1460 * BIT 15 = Enable alternate WWN
1461 *
1462 * BIT 16 = CLP LUN string
1463 * BIT 17 = CLP Target string
1464 * BIT 18 = CLP BIOS enable string
1465 * BIT 19 = CLP Serdes string
1466 * BIT 20 = CLP WWPN string
1467 * BIT 21 = CLP WWNN string
1468 * BIT 22 =
1469 * BIT 23 =
1470 * BIT 24 = Keep WWPN
1471 * BIT 25 = Temp WWPN
1472 * BIT 26-31 =
1473 */
1474 uint32_t host_p;
1475
1476 uint8_t alternate_port_name[WWN_SIZE];
1477 uint8_t alternate_node_name[WWN_SIZE];
1478
1479 uint8_t boot_port_name[WWN_SIZE];
1480 uint16_t boot_lun_number;
1481 uint16_t reserved_8;
1482
1483 uint8_t alt1_boot_port_name[WWN_SIZE];
1484 uint16_t alt1_boot_lun_number;
1485 uint16_t reserved_9;
1486
1487 uint8_t alt2_boot_port_name[WWN_SIZE];
1488 uint16_t alt2_boot_lun_number;
1489 uint16_t reserved_10;
1490
1491 uint8_t alt3_boot_port_name[WWN_SIZE];
1492 uint16_t alt3_boot_lun_number;
1493 uint16_t reserved_11;
1494
1495 /*
1496 * BIT 0 = Selective Login
1497 * BIT 1 = Alt-Boot Enable
1498 * BIT 2 = Reserved
1499 * BIT 3 = Boot Order List
1500 * BIT 4 = Reserved
1501 * BIT 5 = Selective LUN
1502 * BIT 6 = Reserved
1503 * BIT 7-31 =
1504 */
1505 uint32_t efi_parameters;
1506
1507 uint8_t reset_delay;
1508 uint8_t reserved_12;
1509 uint16_t reserved_13;
1510
1511 uint16_t boot_id_number;
1512 uint16_t reserved_14;
1513
1514 uint16_t max_luns_per_target;
1515 uint16_t reserved_15;
1516
1517 uint16_t port_down_retry_count;
1518 uint16_t link_down_timeout;
1519
1520 /* FCode parameters. */
1521 uint16_t fcode_parameter;
1522
1523 uint16_t reserved_16[3];
1524
1525 /* Offset 352. */
1526 uint8_t reserved_17[4];
1527 uint16_t reserved_18[5];
1528 uint8_t reserved_19[2];
1529 uint16_t reserved_20[8];
1530
1531 /* Offset 384. */
1532 uint8_t reserved_21[16];
1533 uint16_t reserved_22[8];
1534
1535 /* Offset 416. */
1536 uint16_t reserved_23[32];
1537
1538 /* Offset 480. */
1539 uint8_t model_name[16];
1540
1541 /* Offset 496. */
1542 uint16_t feature_mask_l;
1543 uint16_t feature_mask_h;
1544 uint16_t reserved_24[2];
1545
1546 uint16_t subsystem_vendor_id;
1547 uint16_t subsystem_device_id;
1548
1549 uint32_t checksum;
1550};
1551
1552/*
1553 * ISP Initialization Control Block.
1554 * Little endian except where noted.
1555 */
1556#define ICB_VERSION 1
1557struct init_cb_81xx {
1558 uint16_t version;
1559 uint16_t reserved_1;
1560
1561 uint16_t frame_payload_size;
1562 uint16_t execution_throttle;
1563 uint16_t exchange_count;
1564
1565 uint16_t reserved_2;
1566
1567 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1568 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1569
1570 uint16_t response_q_inpointer;
1571 uint16_t request_q_outpointer;
1572
1573 uint16_t login_retry_count;
1574
1575 uint16_t prio_request_q_outpointer;
1576
1577 uint16_t response_q_length;
1578 uint16_t request_q_length;
1579
1580 uint16_t reserved_3;
1581
1582 uint16_t prio_request_q_length;
1583
1584 uint32_t request_q_address[2];
1585 uint32_t response_q_address[2];
1586 uint32_t prio_request_q_address[2];
1587
1588 uint8_t reserved_4[8];
1589
1590 uint16_t atio_q_inpointer;
1591 uint16_t atio_q_length;
1592 uint32_t atio_q_address[2];
1593
1594 uint16_t interrupt_delay_timer; /* 100us increments. */
1595 uint16_t login_timeout;
1596
1597 /*
1598 * BIT 0-3 = Reserved
1599 * BIT 4 = Enable Target Mode
1600 * BIT 5 = Disable Initiator Mode
1601 * BIT 6 = Reserved
1602 * BIT 7 = Reserved
1603 *
1604 * BIT 8-13 = Reserved
1605 * BIT 14 = Node Name Option
1606 * BIT 15-31 = Reserved
1607 */
1608 uint32_t firmware_options_1;
1609
1610 /*
1611 * BIT 0 = Operation Mode bit 0
1612 * BIT 1 = Operation Mode bit 1
1613 * BIT 2 = Operation Mode bit 2
1614 * BIT 3 = Operation Mode bit 3
1615 * BIT 4-7 = Reserved
1616 *
1617 * BIT 8 = Enable Class 2
1618 * BIT 9 = Enable ACK0
1619 * BIT 10 = Reserved
1620 * BIT 11 = Enable FC-SP Security
1621 * BIT 12 = FC Tape Enable
1622 * BIT 13 = Reserved
1623 * BIT 14 = Enable Target PRLI Control
1624 * BIT 15-31 = Reserved
1625 */
1626 uint32_t firmware_options_2;
1627
1628 /*
1629 * BIT 0-3 = Reserved
1630 * BIT 4 = FCP RSP Payload bit 0
1631 * BIT 5 = FCP RSP Payload bit 1
1632 * BIT 6 = Enable Receive Out-of-Order data frame handling
1633 * BIT 7 = Reserved
1634 *
1635 * BIT 8 = Reserved
1636 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1637 * BIT 10-16 = Reserved
1638 * BIT 17 = Enable multiple FCFs
1639 * BIT 18-20 = MAC addressing mode
1640 * BIT 21-25 = Ethernet data rate
1641 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1642 * BIT 27 = Enable ethernet header rx IOCB for response q
1643 * BIT 28 = SPMA selection bit 0
1644 * BIT 28 = SPMA selection bit 1
1645 * BIT 30-31 = Reserved
1646 */
1647 uint32_t firmware_options_3;
1648
1649 uint8_t reserved_5[8];
1650
1651 uint8_t enode_mac[6];
1652
1653 uint8_t reserved_6[10];
1654};
1655
1656struct mid_init_cb_81xx {
1657 struct init_cb_81xx init_cb;
1658
1659 uint16_t count;
1660 uint16_t options;
1661
1662 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1663};
1664
1665#define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
1666#define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
1667
1668/* 81XX Flash locations -- occupies second 2MB region. */
1669#define FA_BOOT_CODE_ADDR_81 0x80000
1670#define FA_RISC_CODE_ADDR_81 0xA0000
1671#define FA_FW_AREA_ADDR_81 0xC0000
1672#define FA_VPD_NVRAM_ADDR_81 0xD0000
1673#define FA_FEATURE_ADDR_81 0xD4000
1674#define FA_FLASH_DESCR_ADDR_81 0xD8000
1675#define FA_FLASH_LAYOUT_ADDR_81 0xD8400
1676#define FA_HW_EVENT0_ADDR_81 0xDC000
1677#define FA_HW_EVENT1_ADDR_81 0xDC400
1678#define FA_NPIV_CONF0_ADDR_81 0xD1000
1679#define FA_NPIV_CONF1_ADDR_81 0xD2000
1680
1393#endif 1681#endif
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
index 450a05c5d33b..ba4913353752 100644
--- a/drivers/scsi/qla2xxx/qla_gbl.h
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
@@ -28,8 +28,10 @@ extern void qla2x00_reset_adapter(struct scsi_qla_host *);
28extern void qla24xx_reset_adapter(struct scsi_qla_host *); 28extern void qla24xx_reset_adapter(struct scsi_qla_host *);
29extern int qla2x00_nvram_config(struct scsi_qla_host *); 29extern int qla2x00_nvram_config(struct scsi_qla_host *);
30extern int qla24xx_nvram_config(struct scsi_qla_host *); 30extern int qla24xx_nvram_config(struct scsi_qla_host *);
31extern int qla81xx_nvram_config(struct scsi_qla_host *);
31extern void qla2x00_update_fw_options(struct scsi_qla_host *); 32extern void qla2x00_update_fw_options(struct scsi_qla_host *);
32extern void qla24xx_update_fw_options(scsi_qla_host_t *); 33extern void qla24xx_update_fw_options(scsi_qla_host_t *);
34extern void qla81xx_update_fw_options(scsi_qla_host_t *);
33extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *); 35extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *);
34extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *); 36extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *);
35 37
@@ -141,7 +143,7 @@ qla2x00_execute_fw(scsi_qla_host_t *, uint32_t);
141 143
142extern void 144extern void
143qla2x00_get_fw_version(scsi_qla_host_t *, uint16_t *, 145qla2x00_get_fw_version(scsi_qla_host_t *, uint16_t *,
144 uint16_t *, uint16_t *, uint16_t *, uint32_t *); 146 uint16_t *, uint16_t *, uint16_t *, uint32_t *, uint8_t *, uint32_t *);
145 147
146extern int 148extern int
147qla2x00_get_fw_options(scsi_qla_host_t *, uint16_t *); 149qla2x00_get_fw_options(scsi_qla_host_t *, uint16_t *);
@@ -327,6 +329,7 @@ extern void qla2100_fw_dump(scsi_qla_host_t *, int);
327extern void qla2300_fw_dump(scsi_qla_host_t *, int); 329extern void qla2300_fw_dump(scsi_qla_host_t *, int);
328extern void qla24xx_fw_dump(scsi_qla_host_t *, int); 330extern void qla24xx_fw_dump(scsi_qla_host_t *, int);
329extern void qla25xx_fw_dump(scsi_qla_host_t *, int); 331extern void qla25xx_fw_dump(scsi_qla_host_t *, int);
332extern void qla81xx_fw_dump(scsi_qla_host_t *, int);
330extern void qla2x00_dump_regs(scsi_qla_host_t *); 333extern void qla2x00_dump_regs(scsi_qla_host_t *);
331extern void qla2x00_dump_buffer(uint8_t *, uint32_t); 334extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
332 335
diff --git a/drivers/scsi/qla2xxx/qla_gs.c b/drivers/scsi/qla2xxx/qla_gs.c
index 0a6f72973996..557f58d5bf88 100644
--- a/drivers/scsi/qla2xxx/qla_gs.c
+++ b/drivers/scsi/qla2xxx/qla_gs.c
@@ -1535,7 +1535,10 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *vha)
1535 eiter = (struct ct_fdmi_port_attr *) (entries + size); 1535 eiter = (struct ct_fdmi_port_attr *) (entries + size);
1536 eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); 1536 eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED);
1537 eiter->len = __constant_cpu_to_be16(4 + 4); 1537 eiter->len = __constant_cpu_to_be16(4 + 4);
1538 if (IS_QLA25XX(ha)) 1538 if (IS_QLA81XX(ha))
1539 eiter->a.sup_speed = __constant_cpu_to_be32(
1540 FDMI_PORT_SPEED_10GB);
1541 else if (IS_QLA25XX(ha))
1539 eiter->a.sup_speed = __constant_cpu_to_be32( 1542 eiter->a.sup_speed = __constant_cpu_to_be32(
1540 FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| 1543 FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB|
1541 FDMI_PORT_SPEED_4GB|FDMI_PORT_SPEED_8GB); 1544 FDMI_PORT_SPEED_4GB|FDMI_PORT_SPEED_8GB);
@@ -1575,6 +1578,10 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *vha)
1575 eiter->a.cur_speed = 1578 eiter->a.cur_speed =
1576 __constant_cpu_to_be32(FDMI_PORT_SPEED_8GB); 1579 __constant_cpu_to_be32(FDMI_PORT_SPEED_8GB);
1577 break; 1580 break;
1581 case PORT_SPEED_10GB:
1582 eiter->a.cur_speed =
1583 __constant_cpu_to_be32(FDMI_PORT_SPEED_10GB);
1584 break;
1578 default: 1585 default:
1579 eiter->a.cur_speed = 1586 eiter->a.cur_speed =
1580 __constant_cpu_to_be32(FDMI_PORT_SPEED_UNKNOWN); 1587 __constant_cpu_to_be32(FDMI_PORT_SPEED_UNKNOWN);
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 6038aedc1239..2d4f32b4df5c 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -778,16 +778,19 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
778 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 778 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
779 sizeof(uint16_t); 779 sizeof(uint16_t);
780 } else if (IS_FWI2_CAPABLE(ha)) { 780 } else if (IS_FWI2_CAPABLE(ha)) {
781 fixed_size = IS_QLA25XX(ha) ? 781 if (IS_QLA81XX(ha))
782 offsetof(struct qla25xx_fw_dump, ext_mem) : 782 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
783 offsetof(struct qla24xx_fw_dump, ext_mem); 783 else if (IS_QLA25XX(ha))
784 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
785 else
786 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
784 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 787 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
785 sizeof(uint32_t); 788 sizeof(uint32_t);
786 if (ha->mqenable) 789 if (ha->mqenable)
787 mq_size = sizeof(struct qla2xxx_mq_chain); 790 mq_size = sizeof(struct qla2xxx_mq_chain);
788 791
789 /* Allocate memory for Fibre Channel Event Buffer. */ 792 /* Allocate memory for Fibre Channel Event Buffer. */
790 if (!IS_QLA25XX(ha)) 793 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
791 goto try_eft; 794 goto try_eft;
792 795
793 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 796 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
@@ -988,7 +991,8 @@ qla2x00_setup_chip(scsi_qla_host_t *vha)
988 &ha->fw_major_version, 991 &ha->fw_major_version,
989 &ha->fw_minor_version, 992 &ha->fw_minor_version,
990 &ha->fw_subminor_version, 993 &ha->fw_subminor_version,
991 &ha->fw_attributes, &ha->fw_memory_size); 994 &ha->fw_attributes, &ha->fw_memory_size,
995 ha->mpi_version, &ha->mpi_capabilities);
992 ha->flags.npiv_supported = 0; 996 ha->flags.npiv_supported = 0;
993 if (IS_QLA2XXX_MIDTYPE(ha) && 997 if (IS_QLA2XXX_MIDTYPE(ha) &&
994 (ha->fw_attributes & BIT_2)) { 998 (ha->fw_attributes & BIT_2)) {
@@ -4252,3 +4256,269 @@ qla84xx_init_chip(scsi_qla_host_t *vha)
4252 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: 4256 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
4253 QLA_SUCCESS; 4257 QLA_SUCCESS;
4254} 4258}
4259
4260/* 81XX Support **************************************************************/
4261
4262int
4263qla81xx_nvram_config(scsi_qla_host_t *vha)
4264{
4265 int rval;
4266 struct init_cb_81xx *icb;
4267 struct nvram_81xx *nv;
4268 uint32_t *dptr;
4269 uint8_t *dptr1, *dptr2;
4270 uint32_t chksum;
4271 uint16_t cnt;
4272 struct qla_hw_data *ha = vha->hw;
4273
4274 rval = QLA_SUCCESS;
4275 icb = (struct init_cb_81xx *)ha->init_cb;
4276 nv = ha->nvram;
4277
4278 /* Determine NVRAM starting address. */
4279 ha->nvram_size = sizeof(struct nvram_81xx);
4280 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4281 ha->vpd_size = FA_NVRAM_VPD_SIZE;
4282 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4283 if (PCI_FUNC(ha->pdev->devfn) & 1) {
4284 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
4285 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4286 }
4287
4288 /* Get VPD data into cache */
4289 ha->vpd = ha->nvram + VPD_OFFSET;
4290 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
4291 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4292
4293 /* Get NVRAM data into cache and calculate checksum. */
4294 dptr = (uint32_t *)nv;
4295 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
4296 ha->nvram_size);
4297 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4298 chksum += le32_to_cpu(*dptr++);
4299
4300 DEBUG5(printk("scsi(%ld): Contents of NVRAM\n", ha->host_no));
4301 DEBUG5(qla2x00_dump_buffer((uint8_t *)nv, ha->nvram_size));
4302
4303 /* Bad NVRAM data, set defaults parameters. */
4304 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4305 || nv->id[3] != ' ' ||
4306 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4307 /* Reset NVRAM data. */
4308 qla_printk(KERN_WARNING, ha, "Inconsistent NVRAM detected: "
4309 "checksum=0x%x id=%c version=0x%x.\n", chksum, nv->id[0],
4310 le16_to_cpu(nv->nvram_version));
4311 qla_printk(KERN_WARNING, ha, "Falling back to functioning (yet "
4312 "invalid -- WWPN) defaults.\n");
4313
4314 /*
4315 * Set default initialization control block.
4316 */
4317 memset(nv, 0, ha->nvram_size);
4318 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4319 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4320 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4321 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4322 nv->exchange_count = __constant_cpu_to_le16(0);
4323 nv->port_name[0] = 0x21;
4324 nv->port_name[1] = 0x00 + PCI_FUNC(ha->pdev->devfn);
4325 nv->port_name[2] = 0x00;
4326 nv->port_name[3] = 0xe0;
4327 nv->port_name[4] = 0x8b;
4328 nv->port_name[5] = 0x1c;
4329 nv->port_name[6] = 0x55;
4330 nv->port_name[7] = 0x86;
4331 nv->node_name[0] = 0x20;
4332 nv->node_name[1] = 0x00;
4333 nv->node_name[2] = 0x00;
4334 nv->node_name[3] = 0xe0;
4335 nv->node_name[4] = 0x8b;
4336 nv->node_name[5] = 0x1c;
4337 nv->node_name[6] = 0x55;
4338 nv->node_name[7] = 0x86;
4339 nv->login_retry_count = __constant_cpu_to_le16(8);
4340 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4341 nv->login_timeout = __constant_cpu_to_le16(0);
4342 nv->firmware_options_1 =
4343 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4344 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4345 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4346 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4347 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4348 nv->efi_parameters = __constant_cpu_to_le32(0);
4349 nv->reset_delay = 5;
4350 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4351 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4352 nv->link_down_timeout = __constant_cpu_to_le16(30);
4353 nv->enode_mac[0] = 0x01;
4354 nv->enode_mac[1] = 0x02;
4355 nv->enode_mac[2] = 0x03;
4356 nv->enode_mac[3] = 0x04;
4357 nv->enode_mac[4] = 0x05;
4358 nv->enode_mac[5] = 0x06 + PCI_FUNC(ha->pdev->devfn);
4359
4360 rval = 1;
4361 }
4362
4363 /* Reset Initialization control block */
4364 memset(icb, 0, sizeof(struct init_cb_81xx));
4365
4366 /* Copy 1st segment. */
4367 dptr1 = (uint8_t *)icb;
4368 dptr2 = (uint8_t *)&nv->version;
4369 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4370 while (cnt--)
4371 *dptr1++ = *dptr2++;
4372
4373 icb->login_retry_count = nv->login_retry_count;
4374
4375 /* Copy 2nd segment. */
4376 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4377 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4378 cnt = (uint8_t *)&icb->reserved_5 -
4379 (uint8_t *)&icb->interrupt_delay_timer;
4380 while (cnt--)
4381 *dptr1++ = *dptr2++;
4382
4383 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
4384 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
4385 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
4386 icb->enode_mac[0] = 0x01;
4387 icb->enode_mac[1] = 0x02;
4388 icb->enode_mac[2] = 0x03;
4389 icb->enode_mac[3] = 0x04;
4390 icb->enode_mac[4] = 0x05;
4391 icb->enode_mac[5] = 0x06 + PCI_FUNC(ha->pdev->devfn);
4392 }
4393
4394 /*
4395 * Setup driver NVRAM options.
4396 */
4397 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
4398 "QLE81XX");
4399
4400 /* Use alternate WWN? */
4401 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
4402 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4403 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4404 }
4405
4406 /* Prepare nodename */
4407 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
4408 /*
4409 * Firmware will apply the following mask if the nodename was
4410 * not provided.
4411 */
4412 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4413 icb->node_name[0] &= 0xF0;
4414 }
4415
4416 /* Set host adapter parameters. */
4417 ha->flags.disable_risc_code_load = 0;
4418 ha->flags.enable_lip_reset = 0;
4419 ha->flags.enable_lip_full_login =
4420 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4421 ha->flags.enable_target_reset =
4422 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
4423 ha->flags.enable_led_scheme = 0;
4424 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
4425
4426 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4427 (BIT_6 | BIT_5 | BIT_4)) >> 4;
4428
4429 /* save HBA serial number */
4430 ha->serial0 = icb->port_name[5];
4431 ha->serial1 = icb->port_name[6];
4432 ha->serial2 = icb->port_name[7];
4433 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4434 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
4435
4436 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4437
4438 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4439
4440 /* Set minimum login_timeout to 4 seconds. */
4441 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4442 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4443 if (le16_to_cpu(nv->login_timeout) < 4)
4444 nv->login_timeout = __constant_cpu_to_le16(4);
4445 ha->login_timeout = le16_to_cpu(nv->login_timeout);
4446 icb->login_timeout = nv->login_timeout;
4447
4448 /* Set minimum RATOV to 100 tenths of a second. */
4449 ha->r_a_tov = 100;
4450
4451 ha->loop_reset_delay = nv->reset_delay;
4452
4453 /* Link Down Timeout = 0:
4454 *
4455 * When Port Down timer expires we will start returning
4456 * I/O's to OS with "DID_NO_CONNECT".
4457 *
4458 * Link Down Timeout != 0:
4459 *
4460 * The driver waits for the link to come up after link down
4461 * before returning I/Os to OS with "DID_NO_CONNECT".
4462 */
4463 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4464 ha->loop_down_abort_time =
4465 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4466 } else {
4467 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4468 ha->loop_down_abort_time =
4469 (LOOP_DOWN_TIME - ha->link_down_timeout);
4470 }
4471
4472 /* Need enough time to try and get the port back. */
4473 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4474 if (qlport_down_retry)
4475 ha->port_down_retry_count = qlport_down_retry;
4476
4477 /* Set login_retry_count */
4478 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4479 if (ha->port_down_retry_count ==
4480 le16_to_cpu(nv->port_down_retry_count) &&
4481 ha->port_down_retry_count > 3)
4482 ha->login_retry_count = ha->port_down_retry_count;
4483 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4484 ha->login_retry_count = ha->port_down_retry_count;
4485 if (ql2xloginretrycount)
4486 ha->login_retry_count = ql2xloginretrycount;
4487
4488 /* Enable ZIO. */
4489 if (!vha->flags.init_done) {
4490 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4491 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4492 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4493 le16_to_cpu(icb->interrupt_delay_timer): 2;
4494 }
4495 icb->firmware_options_2 &= __constant_cpu_to_le32(
4496 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4497 vha->flags.process_response_queue = 0;
4498 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4499 ha->zio_mode = QLA_ZIO_MODE_6;
4500
4501 DEBUG2(printk("scsi(%ld): ZIO mode %d enabled; timer delay "
4502 "(%d us).\n", vha->host_no, ha->zio_mode,
4503 ha->zio_timer * 100));
4504 qla_printk(KERN_INFO, ha,
4505 "ZIO mode %d enabled; timer delay (%d us).\n",
4506 ha->zio_mode, ha->zio_timer * 100);
4507
4508 icb->firmware_options_2 |= cpu_to_le32(
4509 (uint32_t)ha->zio_mode);
4510 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4511 vha->flags.process_response_queue = 1;
4512 }
4513
4514 if (rval) {
4515 DEBUG2_3(printk(KERN_WARNING
4516 "scsi(%ld): NVRAM configuration failed!\n", vha->host_no));
4517 }
4518 return (rval);
4519}
4520
4521void
4522qla81xx_update_fw_options(scsi_qla_host_t *ha)
4523{
4524}
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index dcfec7429cc7..789fc576f222 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -275,7 +275,7 @@ void
275qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb) 275qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
276{ 276{
277#define LS_UNKNOWN 2 277#define LS_UNKNOWN 2
278 static char *link_speeds[5] = { "1", "2", "?", "4", "8" }; 278 static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
279 char *link_speed; 279 char *link_speed;
280 uint16_t handle_cnt; 280 uint16_t handle_cnt;
281 uint16_t cnt; 281 uint16_t cnt;
@@ -288,6 +288,8 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
288 288
289 /* Setup to process RIO completion. */ 289 /* Setup to process RIO completion. */
290 handle_cnt = 0; 290 handle_cnt = 0;
291 if (IS_QLA81XX(ha))
292 goto skip_rio;
291 switch (mb[0]) { 293 switch (mb[0]) {
292 case MBA_SCSI_COMPLETION: 294 case MBA_SCSI_COMPLETION:
293 handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1])); 295 handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
@@ -339,7 +341,7 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
339 default: 341 default:
340 break; 342 break;
341 } 343 }
342 344skip_rio:
343 switch (mb[0]) { 345 switch (mb[0]) {
344 case MBA_SCSI_COMPLETION: /* Fast Post */ 346 case MBA_SCSI_COMPLETION: /* Fast Post */
345 if (!vha->flags.online) 347 if (!vha->flags.online)
@@ -433,6 +435,8 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
433 link_speed = link_speeds[LS_UNKNOWN]; 435 link_speed = link_speeds[LS_UNKNOWN];
434 if (mb[1] < 5) 436 if (mb[1] < 5)
435 link_speed = link_speeds[mb[1]]; 437 link_speed = link_speeds[mb[1]];
438 else if (mb[1] == 0x13)
439 link_speed = link_speeds[5];
436 ha->link_data_rate = mb[1]; 440 ha->link_data_rate = mb[1];
437 } 441 }
438 442
@@ -492,12 +496,17 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
492 qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]); 496 qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
493 break; 497 break;
494 498
499 /* case MBA_DCBX_COMPLETE: */
495 case MBA_POINT_TO_POINT: /* Point-to-Point */ 500 case MBA_POINT_TO_POINT: /* Point-to-Point */
496 if (IS_QLA2100(ha)) 501 if (IS_QLA2100(ha))
497 break; 502 break;
498 503
499 DEBUG2(printk("scsi(%ld): Asynchronous P2P MODE received.\n", 504 if (IS_QLA81XX(ha))
500 vha->host_no)); 505 DEBUG2(printk("scsi(%ld): DCBX Completed -- %04x %04x "
506 "%04x\n", vha->host_no, mb[1], mb[2], mb[3]));
507 else
508 DEBUG2(printk("scsi(%ld): Asynchronous P2P MODE "
509 "received.\n", vha->host_no));
501 510
502 /* 511 /*
503 * Until there's a transition from loop down to loop up, treat 512 * Until there's a transition from loop down to loop up, treat
@@ -692,6 +701,35 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
692 } 701 }
693 spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags); 702 spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
694 break; 703 break;
704 case MBA_DCBX_START:
705 DEBUG2(printk("scsi(%ld): DCBX Started -- %04x %04x %04x\n",
706 vha->host_no, mb[1], mb[2], mb[3]));
707 break;
708 case MBA_DCBX_PARAM_UPDATE:
709 DEBUG2(printk("scsi(%ld): DCBX Parameters Updated -- "
710 "%04x %04x %04x\n", vha->host_no, mb[1], mb[2], mb[3]));
711 break;
712 case MBA_FCF_CONF_ERR:
713 DEBUG2(printk("scsi(%ld): FCF Configuration Error -- "
714 "%04x %04x %04x\n", vha->host_no, mb[1], mb[2], mb[3]));
715 break;
716 case MBA_IDC_COMPLETE:
717 DEBUG2(printk("scsi(%ld): Inter-Driver Commucation "
718 "Complete -- %04x %04x %04x\n", vha->host_no, mb[1], mb[2],
719 mb[3]));
720 break;
721 case MBA_IDC_NOTIFY:
722 DEBUG2(printk("scsi(%ld): Inter-Driver Commucation "
723 "Request Notification -- %04x %04x %04x\n", vha->host_no,
724 mb[1], mb[2], mb[3]));
725 /**** Mailbox registers 4 - 7 valid!!! */
726 break;
727 case MBA_IDC_TIME_EXT:
728 DEBUG2(printk("scsi(%ld): Inter-Driver Commucation "
729 "Time Extension -- %04x %04x %04x\n", vha->host_no, mb[1],
730 mb[2], mb[3]));
731 /**** Mailbox registers 4 - 7 valid!!! */
732 break;
695 } 733 }
696 734
697 if (!vha->vp_idx && ha->num_vhosts) 735 if (!vha->vp_idx && ha->num_vhosts)
@@ -1504,7 +1542,7 @@ qla2xxx_check_risc_status(scsi_qla_host_t *vha)
1504 struct qla_hw_data *ha = vha->hw; 1542 struct qla_hw_data *ha = vha->hw;
1505 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1543 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1506 1544
1507 if (!IS_QLA25XX(ha)) 1545 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
1508 return; 1546 return;
1509 1547
1510 rval = QLA_SUCCESS; 1548 rval = QLA_SUCCESS;
@@ -1926,7 +1964,8 @@ qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
1926 device_reg_t __iomem *reg = ha->iobase; 1964 device_reg_t __iomem *reg = ha->iobase;
1927 1965
1928 /* If possible, enable MSI-X. */ 1966 /* If possible, enable MSI-X. */
1929 if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha)) 1967 if (!IS_QLA2432(ha) && !IS_QLA2532(ha) &&
1968 !IS_QLA8432(ha) && !IS_QLA8001(ha))
1930 goto skip_msix; 1969 goto skip_msix;
1931 1970
1932 if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX || 1971 if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX ||
@@ -1961,7 +2000,8 @@ qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
1961 "MSI-X: Falling back-to INTa mode -- %d.\n", ret); 2000 "MSI-X: Falling back-to INTa mode -- %d.\n", ret);
1962skip_msix: 2001skip_msix:
1963 2002
1964 if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha)) 2003 if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
2004 !IS_QLA8001(ha))
1965 goto skip_msi; 2005 goto skip_msi;
1966 2006
1967 ret = pci_enable_msi(ha->pdev); 2007 ret = pci_enable_msi(ha->pdev);
@@ -1982,6 +2022,12 @@ skip_msi:
1982 ha->flags.inta_enabled = 1; 2022 ha->flags.inta_enabled = 1;
1983clear_risc_ints: 2023clear_risc_ints:
1984 2024
2025 /*
2026 * FIXME: Noted that 8014s were being dropped during NK testing.
2027 * Timing deltas during MSI-X/INTa transitions?
2028 */
2029 if (IS_QLA81XX(ha))
2030 goto fail;
1985 spin_lock_irq(&ha->hardware_lock); 2031 spin_lock_irq(&ha->hardware_lock);
1986 if (IS_FWI2_CAPABLE(ha)) { 2032 if (IS_FWI2_CAPABLE(ha)) {
1987 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_HOST_INT); 2033 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_HOST_INT);
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index 4cb679146126..db4df45234a5 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -411,7 +411,8 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
411 */ 411 */
412void 412void
413qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor, 413qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
414 uint16_t *subminor, uint16_t *attributes, uint32_t *memory) 414 uint16_t *subminor, uint16_t *attributes, uint32_t *memory, uint8_t *mpi,
415 uint32_t *mpi_caps)
415{ 416{
416 int rval; 417 int rval;
417 mbx_cmd_t mc; 418 mbx_cmd_t mc;
@@ -422,6 +423,8 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
422 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 423 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
423 mcp->out_mb = MBX_0; 424 mcp->out_mb = MBX_0;
424 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 425 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
426 if (IS_QLA81XX(vha->hw))
427 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
425 mcp->flags = 0; 428 mcp->flags = 0;
426 mcp->tov = MBX_TOV_SECONDS; 429 mcp->tov = MBX_TOV_SECONDS;
427 rval = qla2x00_mailbox_command(vha, mcp); 430 rval = qla2x00_mailbox_command(vha, mcp);
@@ -435,6 +438,13 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
435 *memory = 0x1FFFF; /* Defaults to 128KB. */ 438 *memory = 0x1FFFF; /* Defaults to 128KB. */
436 else 439 else
437 *memory = (mcp->mb[5] << 16) | mcp->mb[4]; 440 *memory = (mcp->mb[5] << 16) | mcp->mb[4];
441 if (IS_QLA81XX(vha->hw)) {
442 mpi[0] = mcp->mb[10] >> 8;
443 mpi[1] = mcp->mb[10] & 0xff;
444 mpi[2] = mcp->mb[11] >> 8;
445 mpi[3] = mcp->mb[11] & 0xff;
446 *mpi_caps = (mcp->mb[12] << 16) | mcp->mb[13];
447 }
438 448
439 if (rval != QLA_SUCCESS) { 449 if (rval != QLA_SUCCESS) {
440 /*EMPTY*/ 450 /*EMPTY*/
@@ -1353,7 +1363,13 @@ qla2x00_lip_reset(scsi_qla_host_t *vha)
1353 1363
1354 DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); 1364 DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no));
1355 1365
1356 if (IS_FWI2_CAPABLE(vha->hw)) { 1366 if (IS_QLA81XX(vha->hw)) {
1367 /* Logout across all FCFs. */
1368 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1369 mcp->mb[1] = BIT_1;
1370 mcp->mb[2] = 0;
1371 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1372 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1357 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1373 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1358 mcp->mb[1] = BIT_6; 1374 mcp->mb[1] = BIT_6;
1359 mcp->mb[2] = 0; 1375 mcp->mb[2] = 0;
@@ -1843,6 +1859,9 @@ qla2x00_full_login_lip(scsi_qla_host_t *vha)
1843 mbx_cmd_t mc; 1859 mbx_cmd_t mc;
1844 mbx_cmd_t *mcp = &mc; 1860 mbx_cmd_t *mcp = &mc;
1845 1861
1862 if (IS_QLA81XX(vha->hw))
1863 return QLA_SUCCESS;
1864
1846 DEBUG11(printk("qla2x00_full_login_lip(%ld): entered.\n", 1865 DEBUG11(printk("qla2x00_full_login_lip(%ld): entered.\n",
1847 vha->host_no)); 1866 vha->host_no));
1848 1867
@@ -2502,7 +2521,7 @@ qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
2502 mbx_cmd_t mc; 2521 mbx_cmd_t mc;
2503 mbx_cmd_t *mcp = &mc; 2522 mbx_cmd_t *mcp = &mc;
2504 2523
2505 if (!IS_QLA25XX(vha->hw)) 2524 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw))
2506 return QLA_FUNCTION_FAILED; 2525 return QLA_FUNCTION_FAILED;
2507 2526
2508 DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); 2527 DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no));
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 1b475c5fa6f4..4a71f522f925 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -404,26 +404,9 @@ static char *
404qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 404qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
405{ 405{
406 struct qla_hw_data *ha = vha->hw; 406 struct qla_hw_data *ha = vha->hw;
407 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
408 ha->fw_minor_version,
409 ha->fw_subminor_version);
410 407
411 if (ha->fw_attributes & BIT_0) 408 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
412 strcat(str, "[Class 2] "); 409 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
413 if (ha->fw_attributes & BIT_1)
414 strcat(str, "[IP] ");
415 if (ha->fw_attributes & BIT_2)
416 strcat(str, "[Multi-ID] ");
417 if (ha->fw_attributes & BIT_3)
418 strcat(str, "[SB-2] ");
419 if (ha->fw_attributes & BIT_4)
420 strcat(str, "[T10 CRC] ");
421 if (ha->fw_attributes & BIT_5)
422 strcat(str, "[VI] ");
423 if (ha->fw_attributes & BIT_10)
424 strcat(str, "[84XX] ");
425 if (ha->fw_attributes & BIT_13)
426 strcat(str, "[Experimental]");
427 return str; 410 return str;
428} 411}
429 412
@@ -1489,6 +1472,44 @@ static struct isp_operations qla25xx_isp_ops = {
1489 .rd_req_reg = qla24xx_rd_req_reg, 1472 .rd_req_reg = qla24xx_rd_req_reg,
1490}; 1473};
1491 1474
1475static struct isp_operations qla81xx_isp_ops = {
1476 .pci_config = qla25xx_pci_config,
1477 .reset_chip = qla24xx_reset_chip,
1478 .chip_diag = qla24xx_chip_diag,
1479 .config_rings = qla24xx_config_rings,
1480 .reset_adapter = qla24xx_reset_adapter,
1481 .nvram_config = qla81xx_nvram_config,
1482 .update_fw_options = qla81xx_update_fw_options,
1483 .load_risc = qla24xx_load_risc,
1484 .pci_info_str = qla24xx_pci_info_str,
1485 .fw_version_str = qla24xx_fw_version_str,
1486 .intr_handler = qla24xx_intr_handler,
1487 .enable_intrs = qla24xx_enable_intrs,
1488 .disable_intrs = qla24xx_disable_intrs,
1489 .abort_command = qla24xx_abort_command,
1490 .target_reset = qla24xx_abort_target,
1491 .lun_reset = qla24xx_lun_reset,
1492 .fabric_login = qla24xx_login_fabric,
1493 .fabric_logout = qla24xx_fabric_logout,
1494 .calc_req_entries = NULL,
1495 .build_iocbs = NULL,
1496 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1497 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1498 .read_nvram = qla25xx_read_nvram_data,
1499 .write_nvram = qla25xx_write_nvram_data,
1500 .fw_dump = qla81xx_fw_dump,
1501 .beacon_on = qla24xx_beacon_on,
1502 .beacon_off = qla24xx_beacon_off,
1503 .beacon_blink = qla24xx_beacon_blink,
1504 .read_optrom = qla25xx_read_optrom_data,
1505 .write_optrom = qla24xx_write_optrom_data,
1506 .get_flash_version = qla24xx_get_flash_version,
1507 .start_scsi = qla24xx_start_scsi,
1508 .wrt_req_reg = qla24xx_wrt_req_reg,
1509 .wrt_rsp_reg = qla24xx_wrt_rsp_reg,
1510 .rd_req_reg = qla24xx_rd_req_reg,
1511};
1512
1492static inline void 1513static inline void
1493qla2x00_set_isp_flags(struct qla_hw_data *ha) 1514qla2x00_set_isp_flags(struct qla_hw_data *ha)
1494{ 1515{
@@ -1568,6 +1589,13 @@ qla2x00_set_isp_flags(struct qla_hw_data *ha)
1568 ha->device_type |= DT_IIDMA; 1589 ha->device_type |= DT_IIDMA;
1569 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1590 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1570 break; 1591 break;
1592 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1593 ha->device_type |= DT_ISP8001;
1594 ha->device_type |= DT_ZIO_SUPPORTED;
1595 ha->device_type |= DT_FWI2;
1596 ha->device_type |= DT_IIDMA;
1597 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1598 break;
1571 } 1599 }
1572} 1600}
1573 1601
@@ -1630,7 +1658,7 @@ skip_pio:
1630 1658
1631 /* Determine queue resources */ 1659 /* Determine queue resources */
1632 ha->max_queues = 1; 1660 ha->max_queues = 1;
1633 if (ql2xmaxqueues <= 1 || !IS_QLA25XX(ha)) 1661 if (ql2xmaxqueues <= 1 || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1634 goto mqiobase_exit; 1662 goto mqiobase_exit;
1635 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1663 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1636 pci_resource_len(ha->pdev, 3)); 1664 pci_resource_len(ha->pdev, 3));
@@ -1707,7 +1735,8 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1707 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 1735 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
1708 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 1736 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
1709 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 1737 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
1710 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532) { 1738 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
1739 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001) {
1711 bars = pci_select_bars(pdev, IORESOURCE_MEM); 1740 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1712 sht = &qla24xx_driver_template; 1741 sht = &qla24xx_driver_template;
1713 mem_only = 1; 1742 mem_only = 1;
@@ -1761,6 +1790,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1761 rsp_length = RESPONSE_ENTRY_CNT_2100; 1790 rsp_length = RESPONSE_ENTRY_CNT_2100;
1762 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 1791 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
1763 ha->gid_list_info_size = 4; 1792 ha->gid_list_info_size = 4;
1793 ha->flash_conf_off = ~0;
1794 ha->flash_data_off = ~0;
1795 ha->nvram_conf_off = ~0;
1796 ha->nvram_data_off = ~0;
1764 ha->isp_ops = &qla2100_isp_ops; 1797 ha->isp_ops = &qla2100_isp_ops;
1765 } else if (IS_QLA2200(ha)) { 1798 } else if (IS_QLA2200(ha)) {
1766 ha->mbx_count = MAILBOX_REGISTER_COUNT; 1799 ha->mbx_count = MAILBOX_REGISTER_COUNT;
@@ -1768,6 +1801,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1768 rsp_length = RESPONSE_ENTRY_CNT_2100; 1801 rsp_length = RESPONSE_ENTRY_CNT_2100;
1769 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 1802 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
1770 ha->gid_list_info_size = 4; 1803 ha->gid_list_info_size = 4;
1804 ha->flash_conf_off = ~0;
1805 ha->flash_data_off = ~0;
1806 ha->nvram_conf_off = ~0;
1807 ha->nvram_data_off = ~0;
1771 ha->isp_ops = &qla2100_isp_ops; 1808 ha->isp_ops = &qla2100_isp_ops;
1772 } else if (IS_QLA23XX(ha)) { 1809 } else if (IS_QLA23XX(ha)) {
1773 ha->mbx_count = MAILBOX_REGISTER_COUNT; 1810 ha->mbx_count = MAILBOX_REGISTER_COUNT;
@@ -1777,6 +1814,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1777 ha->gid_list_info_size = 6; 1814 ha->gid_list_info_size = 6;
1778 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1815 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1779 ha->optrom_size = OPTROM_SIZE_2322; 1816 ha->optrom_size = OPTROM_SIZE_2322;
1817 ha->flash_conf_off = ~0;
1818 ha->flash_data_off = ~0;
1819 ha->nvram_conf_off = ~0;
1820 ha->nvram_data_off = ~0;
1780 ha->isp_ops = &qla2300_isp_ops; 1821 ha->isp_ops = &qla2300_isp_ops;
1781 } else if (IS_QLA24XX_TYPE(ha)) { 1822 } else if (IS_QLA24XX_TYPE(ha)) {
1782 ha->mbx_count = MAILBOX_REGISTER_COUNT; 1823 ha->mbx_count = MAILBOX_REGISTER_COUNT;
@@ -1788,6 +1829,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1788 ha->optrom_size = OPTROM_SIZE_24XX; 1829 ha->optrom_size = OPTROM_SIZE_24XX;
1789 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 1830 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
1790 ha->isp_ops = &qla24xx_isp_ops; 1831 ha->isp_ops = &qla24xx_isp_ops;
1832 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
1833 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
1834 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
1835 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1791 } else if (IS_QLA25XX(ha)) { 1836 } else if (IS_QLA25XX(ha)) {
1792 ha->mbx_count = MAILBOX_REGISTER_COUNT; 1837 ha->mbx_count = MAILBOX_REGISTER_COUNT;
1793 req_length = REQUEST_ENTRY_CNT_24XX; 1838 req_length = REQUEST_ENTRY_CNT_24XX;
@@ -1798,6 +1843,23 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1798 ha->optrom_size = OPTROM_SIZE_25XX; 1843 ha->optrom_size = OPTROM_SIZE_25XX;
1799 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 1844 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
1800 ha->isp_ops = &qla25xx_isp_ops; 1845 ha->isp_ops = &qla25xx_isp_ops;
1846 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
1847 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
1848 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
1849 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1850 } else if (IS_QLA81XX(ha)) {
1851 ha->mbx_count = MAILBOX_REGISTER_COUNT;
1852 req_length = REQUEST_ENTRY_CNT_24XX;
1853 rsp_length = RESPONSE_ENTRY_CNT_2300;
1854 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
1855 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
1856 ha->gid_list_info_size = 8;
1857 ha->optrom_size = OPTROM_SIZE_81XX;
1858 ha->isp_ops = &qla81xx_isp_ops;
1859 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
1860 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
1861 ha->nvram_conf_off = ~0;
1862 ha->nvram_data_off = ~0;
1801 } 1863 }
1802 1864
1803 mutex_init(&ha->vport_lock); 1865 mutex_init(&ha->vport_lock);
@@ -2894,13 +2956,14 @@ qla2x00_timer(scsi_qla_host_t *vha)
2894 2956
2895/* Firmware interface routines. */ 2957/* Firmware interface routines. */
2896 2958
2897#define FW_BLOBS 6 2959#define FW_BLOBS 7
2898#define FW_ISP21XX 0 2960#define FW_ISP21XX 0
2899#define FW_ISP22XX 1 2961#define FW_ISP22XX 1
2900#define FW_ISP2300 2 2962#define FW_ISP2300 2
2901#define FW_ISP2322 3 2963#define FW_ISP2322 3
2902#define FW_ISP24XX 4 2964#define FW_ISP24XX 4
2903#define FW_ISP25XX 5 2965#define FW_ISP25XX 5
2966#define FW_ISP81XX 6
2904 2967
2905#define FW_FILE_ISP21XX "ql2100_fw.bin" 2968#define FW_FILE_ISP21XX "ql2100_fw.bin"
2906#define FW_FILE_ISP22XX "ql2200_fw.bin" 2969#define FW_FILE_ISP22XX "ql2200_fw.bin"
@@ -2908,6 +2971,7 @@ qla2x00_timer(scsi_qla_host_t *vha)
2908#define FW_FILE_ISP2322 "ql2322_fw.bin" 2971#define FW_FILE_ISP2322 "ql2322_fw.bin"
2909#define FW_FILE_ISP24XX "ql2400_fw.bin" 2972#define FW_FILE_ISP24XX "ql2400_fw.bin"
2910#define FW_FILE_ISP25XX "ql2500_fw.bin" 2973#define FW_FILE_ISP25XX "ql2500_fw.bin"
2974#define FW_FILE_ISP81XX "ql8100_fw.bin"
2911 2975
2912static DEFINE_MUTEX(qla_fw_lock); 2976static DEFINE_MUTEX(qla_fw_lock);
2913 2977
@@ -2918,6 +2982,7 @@ static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
2918 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 2982 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
2919 { .name = FW_FILE_ISP24XX, }, 2983 { .name = FW_FILE_ISP24XX, },
2920 { .name = FW_FILE_ISP25XX, }, 2984 { .name = FW_FILE_ISP25XX, },
2985 { .name = FW_FILE_ISP81XX, },
2921}; 2986};
2922 2987
2923struct fw_blob * 2988struct fw_blob *
@@ -2939,6 +3004,8 @@ qla2x00_request_firmware(scsi_qla_host_t *vha)
2939 blob = &qla_fw_blobs[FW_ISP24XX]; 3004 blob = &qla_fw_blobs[FW_ISP24XX];
2940 } else if (IS_QLA25XX(ha)) { 3005 } else if (IS_QLA25XX(ha)) {
2941 blob = &qla_fw_blobs[FW_ISP25XX]; 3006 blob = &qla_fw_blobs[FW_ISP25XX];
3007 } else if (IS_QLA81XX(ha)) {
3008 blob = &qla_fw_blobs[FW_ISP81XX];
2942 } 3009 }
2943 3010
2944 mutex_lock(&qla_fw_lock); 3011 mutex_lock(&qla_fw_lock);
@@ -3092,6 +3159,7 @@ static struct pci_device_id qla2xxx_pci_tbl[] = {
3092 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 3159 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
3093 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 3160 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
3094 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 3161 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3162 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
3095 { 0 }, 3163 { 0 },
3096}; 3164};
3097MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 3165MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
@@ -3180,3 +3248,4 @@ MODULE_FIRMWARE(FW_FILE_ISP2300);
3180MODULE_FIRMWARE(FW_FILE_ISP2322); 3248MODULE_FIRMWARE(FW_FILE_ISP2322);
3181MODULE_FIRMWARE(FW_FILE_ISP24XX); 3249MODULE_FIRMWARE(FW_FILE_ISP24XX);
3182MODULE_FIRMWARE(FW_FILE_ISP25XX); 3250MODULE_FIRMWARE(FW_FILE_ISP25XX);
3251MODULE_FIRMWARE(FW_FILE_ISP81XX);
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index 628d79c09733..303f8ee11f25 100644
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -425,27 +425,27 @@ qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
425#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 425#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
426 426
427static inline uint32_t 427static inline uint32_t
428flash_conf_to_access_addr(uint32_t faddr) 428flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
429{ 429{
430 return FARX_ACCESS_FLASH_CONF | faddr; 430 return ha->flash_conf_off | faddr;
431} 431}
432 432
433static inline uint32_t 433static inline uint32_t
434flash_data_to_access_addr(uint32_t faddr) 434flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
435{ 435{
436 return FARX_ACCESS_FLASH_DATA | faddr; 436 return ha->flash_data_off | faddr;
437} 437}
438 438
439static inline uint32_t 439static inline uint32_t
440nvram_conf_to_access_addr(uint32_t naddr) 440nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
441{ 441{
442 return FARX_ACCESS_NVRAM_CONF | naddr; 442 return ha->nvram_conf_off | naddr;
443} 443}
444 444
445static inline uint32_t 445static inline uint32_t
446nvram_data_to_access_addr(uint32_t naddr) 446nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
447{ 447{
448 return FARX_ACCESS_NVRAM_DATA | naddr; 448 return ha->nvram_data_off | naddr;
449} 449}
450 450
451static uint32_t 451static uint32_t
@@ -481,10 +481,12 @@ qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
481 uint32_t dwords) 481 uint32_t dwords)
482{ 482{
483 uint32_t i; 483 uint32_t i;
484 struct qla_hw_data *ha = vha->hw;
485
484 /* Dword reads to flash. */ 486 /* Dword reads to flash. */
485 for (i = 0; i < dwords; i++, faddr++) 487 for (i = 0; i < dwords; i++, faddr++)
486 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw, 488 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
487 flash_data_to_access_addr(faddr))); 489 flash_data_addr(ha, faddr)));
488 490
489 return dwptr; 491 return dwptr;
490} 492}
@@ -518,7 +520,7 @@ qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
518{ 520{
519 uint32_t ids; 521 uint32_t ids;
520 522
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab)); 523 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
522 *man_id = LSB(ids); 524 *man_id = LSB(ids);
523 *flash_id = MSB(ids); 525 *flash_id = MSB(ids);
524 526
@@ -530,8 +532,7 @@ qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
530 * Example: ATMEL 0x00 01 45 1F 532 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes. 533 * Extract MFG and Dev ID from last two bytes.
532 */ 534 */
533 ids = qla24xx_read_flash_dword(ha, 535 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
534 flash_data_to_access_addr(0xd009f));
535 *man_id = LSB(ids); 536 *man_id = LSB(ids);
536 *flash_id = MSB(ids); 537 *flash_id = MSB(ids);
537 } 538 }
@@ -555,9 +556,13 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
555 556
556 /* Begin with sane defaults. */ 557 /* Begin with sane defaults. */
557 loc = locations[0]; 558 loc = locations[0];
558 *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24: 559 *start = 0;
559 FA_FLASH_LAYOUT_ADDR; 560 if (IS_QLA24XX_TYPE(ha))
560 561 *start = FA_FLASH_LAYOUT_ADDR_24;
562 else if (IS_QLA25XX(ha))
563 *start = FA_FLASH_LAYOUT_ADDR;
564 else if (IS_QLA81XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR_81;
561 /* Begin with first PCI expansion ROM header. */ 566 /* Begin with first PCI expansion ROM header. */
562 buf = (uint8_t *)req->ring; 567 buf = (uint8_t *)req->ring;
563 dcode = (uint32_t *)req->ring; 568 dcode = (uint32_t *)req->ring;
@@ -618,6 +623,22 @@ static void
618qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 623qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
619{ 624{
620 const char *loc, *locations[] = { "DEF", "FLT" }; 625 const char *loc, *locations[] = { "DEF", "FLT" };
626 const uint32_t def_fw[] =
627 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
628 const uint32_t def_boot[] =
629 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
630 const uint32_t def_vpd_nvram[] =
631 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
632 const uint32_t def_fdt[] =
633 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
634 FA_FLASH_DESCR_ADDR_81 };
635 const uint32_t def_npiv_conf0[] =
636 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
637 FA_NPIV_CONF0_ADDR_81 };
638 const uint32_t def_npiv_conf1[] =
639 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
640 FA_NPIV_CONF1_ADDR_81 };
641 uint32_t def;
621 uint16_t *wptr; 642 uint16_t *wptr;
622 uint16_t cnt, chksum; 643 uint16_t cnt, chksum;
623 uint32_t start; 644 uint32_t start;
@@ -677,11 +698,11 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
677 ha->flt_region_fdt = start; 698 ha->flt_region_fdt = start;
678 break; 699 break;
679 case FLT_REG_NPIV_CONF_0: 700 case FLT_REG_NPIV_CONF_0:
680 if (!PCI_FUNC(ha->pdev->devfn)) 701 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
681 ha->flt_region_npiv_conf = start; 702 ha->flt_region_npiv_conf = start;
682 break; 703 break;
683 case FLT_REG_NPIV_CONF_1: 704 case FLT_REG_NPIV_CONF_1:
684 if (PCI_FUNC(ha->pdev->devfn)) 705 if (PCI_FUNC(ha->pdev->devfn) & 1)
685 ha->flt_region_npiv_conf = start; 706 ha->flt_region_npiv_conf = start;
686 break; 707 break;
687 } 708 }
@@ -691,14 +712,19 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
691no_flash_data: 712no_flash_data:
692 /* Use hardcoded defaults. */ 713 /* Use hardcoded defaults. */
693 loc = locations[0]; 714 loc = locations[0];
694 ha->flt_region_fw = FA_RISC_CODE_ADDR; 715 def = 0;
695 ha->flt_region_boot = FA_BOOT_CODE_ADDR; 716 if (IS_QLA24XX_TYPE(ha))
696 ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR; 717 def = 0;
697 ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24: 718 else if (IS_QLA25XX(ha))
698 FA_FLASH_DESCR_ADDR; 719 def = 1;
699 ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ? 720 else if (IS_QLA81XX(ha))
700 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR): 721 def = 2;
701 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR); 722 ha->flt_region_fw = def_fw[def];
723 ha->flt_region_boot = def_boot[def];
724 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
725 ha->flt_region_fdt = def_fdt[def];
726 ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
727 def_npiv_conf0[def]: def_npiv_conf1[def];
702done: 728done:
703 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x " 729 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
704 "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc, 730 "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
@@ -746,14 +772,14 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
746 mid = le16_to_cpu(fdt->man_id); 772 mid = le16_to_cpu(fdt->man_id);
747 fid = le16_to_cpu(fdt->id); 773 fid = le16_to_cpu(fdt->id);
748 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 774 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
749 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd); 775 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
750 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 776 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
751 if (fdt->unprotect_sec_cmd) { 777 if (fdt->unprotect_sec_cmd) {
752 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 | 778 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
753 fdt->unprotect_sec_cmd); 779 fdt->unprotect_sec_cmd);
754 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 780 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
755 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd): 781 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
756 flash_conf_to_access_addr(0x0336); 782 flash_conf_addr(ha, 0x0336);
757 } 783 }
758 goto done; 784 goto done;
759no_flash_data: 785no_flash_data:
@@ -762,7 +788,7 @@ no_flash_data:
762 mid = man_id; 788 mid = man_id;
763 fid = flash_id; 789 fid = flash_id;
764 ha->fdt_wrt_disable = 0x9c; 790 ha->fdt_wrt_disable = 0x9c;
765 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8); 791 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
766 switch (man_id) { 792 switch (man_id) {
767 case 0xbf: /* STT flash. */ 793 case 0xbf: /* STT flash. */
768 if (flash_id == 0x8e) 794 if (flash_id == 0x8e)
@@ -771,16 +797,16 @@ no_flash_data:
771 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 797 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
772 798
773 if (flash_id == 0x80) 799 if (flash_id == 0x80)
774 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352); 800 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
775 break; 801 break;
776 case 0x13: /* ST M25P80. */ 802 case 0x13: /* ST M25P80. */
777 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 803 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
778 break; 804 break;
779 case 0x1f: /* Atmel 26DF081A. */ 805 case 0x1f: /* Atmel 26DF081A. */
780 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 806 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
781 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320); 807 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
782 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339); 808 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
783 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336); 809 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
784 break; 810 break;
785 default: 811 default:
786 /* Default to 64 kb sector size. */ 812 /* Default to 64 kb sector size. */
@@ -802,7 +828,7 @@ qla2xxx_get_flash_info(scsi_qla_host_t *vha)
802 uint32_t flt_addr; 828 uint32_t flt_addr;
803 struct qla_hw_data *ha = vha->hw; 829 struct qla_hw_data *ha = vha->hw;
804 830
805 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 831 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
806 return QLA_SUCCESS; 832 return QLA_SUCCESS;
807 833
808 ret = qla2xxx_find_flt_start(vha, &flt_addr); 834 ret = qla2xxx_find_flt_start(vha, &flt_addr);
@@ -827,7 +853,7 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
827 struct qla_npiv_entry *entry; 853 struct qla_npiv_entry *entry;
828 struct qla_hw_data *ha = vha->hw; 854 struct qla_hw_data *ha = vha->hw;
829 855
830 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 856 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
831 return; 857 return;
832 858
833 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, 859 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
@@ -919,9 +945,9 @@ qla24xx_unprotect_flash(struct qla_hw_data *ha)
919 return; 945 return;
920 946
921 /* Disable flash write-protection. */ 947 /* Disable flash write-protection. */
922 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 948 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
923 /* Some flash parts need an additional zero-write to clear bits.*/ 949 /* Some flash parts need an additional zero-write to clear bits.*/
924 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 950 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
925} 951}
926 952
927static void 953static void
@@ -934,11 +960,10 @@ qla24xx_protect_flash(struct qla_hw_data *ha)
934 goto skip_wrt_protect; 960 goto skip_wrt_protect;
935 961
936 /* Enable flash write-protection and wait for completion. */ 962 /* Enable flash write-protection and wait for completion. */
937 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 963 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
938 ha->fdt_wrt_disable); 964 ha->fdt_wrt_disable);
939 for (cnt = 300; cnt && 965 for (cnt = 300; cnt &&
940 qla24xx_read_flash_dword(ha, 966 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
941 flash_conf_to_access_addr(0x005)) & BIT_0;
942 cnt--) { 967 cnt--) {
943 udelay(10); 968 udelay(10);
944 } 969 }
@@ -966,7 +991,7 @@ qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
966 ret = QLA_SUCCESS; 991 ret = QLA_SUCCESS;
967 992
968 /* Prepare burst-capable write on supported ISPs. */ 993 /* Prepare burst-capable write on supported ISPs. */
969 if (IS_QLA25XX(ha) && !(faddr & 0xfff) && 994 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
970 dwords > OPTROM_BURST_DWORDS) { 995 dwords > OPTROM_BURST_DWORDS) {
971 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 996 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
972 &optrom_dma, GFP_KERNEL); 997 &optrom_dma, GFP_KERNEL);
@@ -978,7 +1003,7 @@ qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
978 } 1003 }
979 1004
980 rest_addr = (ha->fdt_block_size >> 2) - 1; 1005 rest_addr = (ha->fdt_block_size >> 2) - 1;
981 sec_mask = 0x80000 - (ha->fdt_block_size >> 2); 1006 sec_mask = (ha->optrom_size >> 2) - (ha->fdt_block_size >> 2);
982 1007
983 qla24xx_unprotect_flash(ha); 1008 qla24xx_unprotect_flash(ha);
984 1009
@@ -1013,13 +1038,13 @@ qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1013 *s = cpu_to_le32(*d); 1038 *s = cpu_to_le32(*d);
1014 1039
1015 ret = qla2x00_load_ram(vha, optrom_dma, 1040 ret = qla2x00_load_ram(vha, optrom_dma,
1016 flash_data_to_access_addr(faddr), 1041 flash_data_addr(ha, faddr),
1017 OPTROM_BURST_DWORDS); 1042 OPTROM_BURST_DWORDS);
1018 if (ret != QLA_SUCCESS) { 1043 if (ret != QLA_SUCCESS) {
1019 qla_printk(KERN_WARNING, ha, 1044 qla_printk(KERN_WARNING, ha,
1020 "Unable to burst-write optrom segment " 1045 "Unable to burst-write optrom segment "
1021 "(%x/%x/%llx).\n", ret, 1046 "(%x/%x/%llx).\n", ret,
1022 flash_data_to_access_addr(faddr), 1047 flash_data_addr(ha, faddr),
1023 (unsigned long long)optrom_dma); 1048 (unsigned long long)optrom_dma);
1024 qla_printk(KERN_WARNING, ha, 1049 qla_printk(KERN_WARNING, ha,
1025 "Reverting to slow-write.\n"); 1050 "Reverting to slow-write.\n");
@@ -1036,7 +1061,7 @@ qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1036 } 1061 }
1037 1062
1038 ret = qla24xx_write_flash_dword(ha, 1063 ret = qla24xx_write_flash_dword(ha,
1039 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr)); 1064 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1040 if (ret != QLA_SUCCESS) { 1065 if (ret != QLA_SUCCESS) {
1041 DEBUG9(printk("%s(%ld) Unable to program flash " 1066 DEBUG9(printk("%s(%ld) Unable to program flash "
1042 "address=%x data=%x.\n", __func__, 1067 "address=%x data=%x.\n", __func__,
@@ -1087,12 +1112,13 @@ qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1087{ 1112{
1088 uint32_t i; 1113 uint32_t i;
1089 uint32_t *dwptr; 1114 uint32_t *dwptr;
1115 struct qla_hw_data *ha = vha->hw;
1090 1116
1091 /* Dword reads to flash. */ 1117 /* Dword reads to flash. */
1092 dwptr = (uint32_t *)buf; 1118 dwptr = (uint32_t *)buf;
1093 for (i = 0; i < bytes >> 2; i++, naddr++) 1119 for (i = 0; i < bytes >> 2; i++, naddr++)
1094 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw, 1120 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1095 nvram_data_to_access_addr(naddr))); 1121 nvram_data_addr(ha, naddr)));
1096 1122
1097 return buf; 1123 return buf;
1098} 1124}
@@ -1149,17 +1175,14 @@ qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1149 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */ 1175 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1150 1176
1151 /* Disable NVRAM write-protection. */ 1177 /* Disable NVRAM write-protection. */
1152 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 1178 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1153 0); 1179 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1154 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1155 0);
1156 1180
1157 /* Dword writes to flash. */ 1181 /* Dword writes to flash. */
1158 dwptr = (uint32_t *)buf; 1182 dwptr = (uint32_t *)buf;
1159 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 1183 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1160 ret = qla24xx_write_flash_dword(ha, 1184 ret = qla24xx_write_flash_dword(ha,
1161 nvram_data_to_access_addr(naddr), 1185 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1162 cpu_to_le32(*dwptr));
1163 if (ret != QLA_SUCCESS) { 1186 if (ret != QLA_SUCCESS) {
1164 DEBUG9(qla_printk("Unable to program nvram address=%x " 1187 DEBUG9(qla_printk("Unable to program nvram address=%x "
1165 "data=%x.\n", naddr, *dwptr)); 1188 "data=%x.\n", naddr, *dwptr));
@@ -1168,8 +1191,7 @@ qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1168 } 1191 }
1169 1192
1170 /* Enable NVRAM write-protection. */ 1193 /* Enable NVRAM write-protection. */
1171 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 1194 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1172 0x8c);
1173 1195
1174 /* Disable flash write. */ 1196 /* Disable flash write. */
1175 WRT_REG_DWORD(&reg->ctrl_status, 1197 WRT_REG_DWORD(&reg->ctrl_status,
@@ -1191,8 +1213,7 @@ qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1191 dwptr = (uint32_t *)buf; 1213 dwptr = (uint32_t *)buf;
1192 for (i = 0; i < bytes >> 2; i++, naddr++) 1214 for (i = 0; i < bytes >> 2; i++, naddr++)
1193 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1215 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1194 flash_data_to_access_addr(ha->flt_region_vpd_nvram | 1216 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1195 naddr)));
1196 1217
1197 return buf; 1218 return buf;
1198} 1219}
@@ -2235,12 +2256,12 @@ qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2235 burst = left; 2256 burst = left;
2236 2257
2237 rval = qla2x00_dump_ram(vha, optrom_dma, 2258 rval = qla2x00_dump_ram(vha, optrom_dma,
2238 flash_data_to_access_addr(faddr), burst); 2259 flash_data_addr(ha, faddr), burst);
2239 if (rval) { 2260 if (rval) {
2240 qla_printk(KERN_WARNING, ha, 2261 qla_printk(KERN_WARNING, ha,
2241 "Unable to burst-read optrom segment " 2262 "Unable to burst-read optrom segment "
2242 "(%x/%x/%llx).\n", rval, 2263 "(%x/%x/%llx).\n", rval,
2243 flash_data_to_access_addr(faddr), 2264 flash_data_addr(ha, faddr),
2244 (unsigned long long)optrom_dma); 2265 (unsigned long long)optrom_dma);
2245 qla_printk(KERN_WARNING, ha, 2266 qla_printk(KERN_WARNING, ha,
2246 "Reverting to slow-read.\n"); 2267 "Reverting to slow-read.\n");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 16:04:39 -0500