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authorChad Dupuis <chad.dupuis@qlogic.com>2012-02-09 14:15:41 -0500
committerJames Bottomley <JBottomley@Parallels.com>2012-02-19 09:18:28 -0500
commit2b29d96d7122befe50727c7f5090e783ed910826 (patch)
tree0018d8f33cd0979449ea176be6e0463b8b75f2b0 /drivers/scsi/qla2xxx/qla_nx.c
parentaa61556fa3cf7d0e39a67dc5b043b96519ce3726 (diff)
[SCSI] qla2xxx: Increase speed of flash access in ISP82xx adapters to improve firmware load speed.
Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com> Signed-off-by: Chad Dupuis <chad.dupuis@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_nx.c')
-rw-r--r--drivers/scsi/qla2xxx/qla_nx.c67
1 files changed, 27 insertions, 40 deletions
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
index 0a2f2d578803..b0df7da02018 100644
--- a/drivers/scsi/qla2xxx/qla_nx.c
+++ b/drivers/scsi/qla2xxx/qla_nx.c
@@ -908,27 +908,37 @@ qla82xx_wait_rom_done(struct qla_hw_data *ha)
908 return 0; 908 return 0;
909} 909}
910 910
911int
912qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
913{
914 uint32_t off_value, rval = 0;
915
916 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase),
917 (off & 0xFFFF0000));
918
919 /* Read back value to make sure write has gone through */
920 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
921 off_value = (off & 0x0000FFFF);
922
923 if (flag)
924 WRT_REG_DWORD((void *)
925 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
926 data);
927 else
928 rval = RD_REG_DWORD((void *)
929 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
930
931 return rval;
932}
933
911static int 934static int
912qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 935qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
913{ 936{
914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 937 /* Dword reads to flash. */
938 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
939 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
940 (addr & 0x0000FFFF), 0, 0);
915 941
916 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
917 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
918 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
919 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
920 qla82xx_wait_rom_busy(ha);
921 if (qla82xx_wait_rom_done(ha)) {
922 ql_log(ql_log_fatal, vha, 0x00ba,
923 "Error waiting for rom done.\n");
924 return -1;
925 }
926 /* Reset abyte_cnt and dummy_byte_cnt */
927 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
928 udelay(10);
929 cond_resched();
930 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
931 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
932 return 0; 942 return 0;
933} 943}
934 944
@@ -3639,29 +3649,6 @@ qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3639} 3649}
3640 3650
3641/* Minidump related functions */ 3651/* Minidump related functions */
3642int
3643qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
3644{
3645 uint32_t off_value, rval = 0;
3646
3647 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase),
3648 (off & 0xFFFF0000));
3649
3650 /* Read back value to make sure write has gone through */
3651 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
3652 off_value = (off & 0x0000FFFF);
3653
3654 if (flag)
3655 WRT_REG_DWORD((void *)
3656 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
3657 data);
3658 else
3659 rval = RD_REG_DWORD((void *)
3660 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
3661
3662 return rval;
3663}
3664
3665static int 3652static int
3666qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3653qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3667 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3654 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)