diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-14 15:16:07 -0500 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-14 15:16:07 -0500 |
commit | 12dbf3fc4d06d2c0c4c44dc0612df04248b3cfd3 (patch) | |
tree | 158610ef6c7711afb60d78956ab4b131bf6a08ef /drivers/scsi/qla2xxx/qla_mbx.c | |
parent | 61b7efddc5256225099d13185659e9ad9d8abc8a (diff) | |
parent | fc091e03820bf67e543362bd40959701a71d0c27 (diff) |
Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_mbx.c')
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mbx.c | 107 |
1 files changed, 13 insertions, 94 deletions
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c index 9746cd1e664b..3099b379de9d 100644 --- a/drivers/scsi/qla2xxx/qla_mbx.c +++ b/drivers/scsi/qla2xxx/qla_mbx.c | |||
@@ -196,7 +196,9 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp) | |||
196 | /* Check for pending interrupts. */ | 196 | /* Check for pending interrupts. */ |
197 | qla2x00_poll(ha); | 197 | qla2x00_poll(ha); |
198 | 198 | ||
199 | udelay(10); /* v4.27 */ | 199 | if (command != MBC_LOAD_RISC_RAM_EXTENDED && |
200 | !ha->flags.mbox_int) | ||
201 | msleep(10); | ||
200 | } /* while */ | 202 | } /* while */ |
201 | } | 203 | } |
202 | 204 | ||
@@ -325,113 +327,30 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp) | |||
325 | return rval; | 327 | return rval; |
326 | } | 328 | } |
327 | 329 | ||
328 | /* | ||
329 | * qla2x00_load_ram | ||
330 | * Load adapter RAM using DMA. | ||
331 | * | ||
332 | * Input: | ||
333 | * ha = adapter block pointer. | ||
334 | * | ||
335 | * Returns: | ||
336 | * qla2x00 local function return status code. | ||
337 | * | ||
338 | * Context: | ||
339 | * Kernel context. | ||
340 | */ | ||
341 | int | 330 | int |
342 | qla2x00_load_ram(scsi_qla_host_t *ha, dma_addr_t req_dma, uint16_t risc_addr, | 331 | qla2x00_load_ram(scsi_qla_host_t *ha, dma_addr_t req_dma, uint32_t risc_addr, |
343 | uint16_t risc_code_size) | 332 | uint32_t risc_code_size) |
344 | { | 333 | { |
345 | int rval; | 334 | int rval; |
346 | mbx_cmd_t mc; | 335 | mbx_cmd_t mc; |
347 | mbx_cmd_t *mcp = &mc; | 336 | mbx_cmd_t *mcp = &mc; |
348 | uint32_t req_len; | ||
349 | dma_addr_t nml_dma; | ||
350 | uint32_t nml_len; | ||
351 | uint32_t normalized; | ||
352 | |||
353 | DEBUG11(printk("qla2x00_load_ram(%ld): entered.\n", | ||
354 | ha->host_no);) | ||
355 | 337 | ||
356 | req_len = risc_code_size; | 338 | DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); |
357 | nml_dma = 0; | ||
358 | nml_len = 0; | ||
359 | |||
360 | normalized = qla2x00_normalize_dma_addr(&req_dma, &req_len, &nml_dma, | ||
361 | &nml_len); | ||
362 | |||
363 | /* Load first segment */ | ||
364 | mcp->mb[0] = MBC_LOAD_RISC_RAM; | ||
365 | mcp->mb[1] = risc_addr; | ||
366 | mcp->mb[2] = MSW(req_dma); | ||
367 | mcp->mb[3] = LSW(req_dma); | ||
368 | mcp->mb[4] = (uint16_t)req_len; | ||
369 | mcp->mb[6] = MSW(MSD(req_dma)); | ||
370 | mcp->mb[7] = LSW(MSD(req_dma)); | ||
371 | mcp->out_mb = MBX_7|MBX_6|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; | ||
372 | mcp->in_mb = MBX_0; | ||
373 | mcp->tov = 30; | ||
374 | mcp->flags = 0; | ||
375 | rval = qla2x00_mailbox_command(ha, mcp); | ||
376 | |||
377 | /* Load second segment - if necessary */ | ||
378 | if (normalized && (rval == QLA_SUCCESS)) { | ||
379 | mcp->mb[0] = MBC_LOAD_RISC_RAM; | ||
380 | mcp->mb[1] = risc_addr + (uint16_t)req_len; | ||
381 | mcp->mb[2] = MSW(nml_dma); | ||
382 | mcp->mb[3] = LSW(nml_dma); | ||
383 | mcp->mb[4] = (uint16_t)nml_len; | ||
384 | mcp->mb[6] = MSW(MSD(nml_dma)); | ||
385 | mcp->mb[7] = LSW(MSD(nml_dma)); | ||
386 | mcp->out_mb = MBX_7|MBX_6|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; | ||
387 | mcp->in_mb = MBX_0; | ||
388 | mcp->tov = 30; | ||
389 | mcp->flags = 0; | ||
390 | rval = qla2x00_mailbox_command(ha, mcp); | ||
391 | } | ||
392 | 339 | ||
393 | if (rval == QLA_SUCCESS) { | 340 | if (MSW(risc_addr) || IS_QLA24XX(ha) || IS_QLA25XX(ha)) { |
394 | /* Empty */ | 341 | mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; |
395 | DEBUG11(printk("qla2x00_load_ram(%ld): done.\n", ha->host_no);) | 342 | mcp->mb[8] = MSW(risc_addr); |
343 | mcp->out_mb = MBX_8|MBX_0; | ||
396 | } else { | 344 | } else { |
397 | /* Empty */ | 345 | mcp->mb[0] = MBC_LOAD_RISC_RAM; |
398 | DEBUG2_3_11(printk("qla2x00_load_ram(%ld): failed. rval=%x " | 346 | mcp->out_mb = MBX_0; |
399 | "mb[0]=%x.\n", ha->host_no, rval, mcp->mb[0]);) | ||
400 | } | 347 | } |
401 | return rval; | ||
402 | } | ||
403 | |||
404 | /* | ||
405 | * qla2x00_load_ram_ext | ||
406 | * Load adapter extended RAM using DMA. | ||
407 | * | ||
408 | * Input: | ||
409 | * ha = adapter block pointer. | ||
410 | * | ||
411 | * Returns: | ||
412 | * qla2x00 local function return status code. | ||
413 | * | ||
414 | * Context: | ||
415 | * Kernel context. | ||
416 | */ | ||
417 | int | ||
418 | qla2x00_load_ram_ext(scsi_qla_host_t *ha, dma_addr_t req_dma, | ||
419 | uint32_t risc_addr, uint32_t risc_code_size) | ||
420 | { | ||
421 | int rval; | ||
422 | mbx_cmd_t mc; | ||
423 | mbx_cmd_t *mcp = &mc; | ||
424 | |||
425 | DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); | ||
426 | |||
427 | mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; | ||
428 | mcp->mb[1] = LSW(risc_addr); | 348 | mcp->mb[1] = LSW(risc_addr); |
429 | mcp->mb[2] = MSW(req_dma); | 349 | mcp->mb[2] = MSW(req_dma); |
430 | mcp->mb[3] = LSW(req_dma); | 350 | mcp->mb[3] = LSW(req_dma); |
431 | mcp->mb[6] = MSW(MSD(req_dma)); | 351 | mcp->mb[6] = MSW(MSD(req_dma)); |
432 | mcp->mb[7] = LSW(MSD(req_dma)); | 352 | mcp->mb[7] = LSW(MSD(req_dma)); |
433 | mcp->mb[8] = MSW(risc_addr); | 353 | mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; |
434 | mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; | ||
435 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) { | 354 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) { |
436 | mcp->mb[4] = MSW(risc_code_size); | 355 | mcp->mb[4] = MSW(risc_code_size); |
437 | mcp->mb[5] = LSW(risc_code_size); | 356 | mcp->mb[5] = LSW(risc_code_size); |