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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2007-07-19 18:06:01 -0400
committerJames Bottomley <jejb@mulgrave.localdomain>2007-07-20 10:24:41 -0400
commitf85ec187dcd65c76dcb29f70ff3b5c7f2ae37cc8 (patch)
tree80636a2211f25ec39db8449b11279e1fdccb7a90 /drivers/scsi/qla2xxx/qla_init.c
parentfd34f55694a784052981977cb84c50ea369ffc68 (diff)
[SCSI] qla2xxx: Use PCI-X/PCI-Express read control interfaces.
Original from Peter Oruba <peter.oruba@amd.com>. Additional cleanups included. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_init.c')
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c25
1 files changed, 4 insertions, 21 deletions
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 401a8798ce52..622cf8f15fc7 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -255,7 +255,6 @@ qla24xx_pci_config(scsi_qla_host_t *ha)
255 uint32_t d; 255 uint32_t d;
256 unsigned long flags = 0; 256 unsigned long flags = 0;
257 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 257 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
258 int pcix_cmd_reg, pcie_dctl_reg;
259 258
260 pci_set_master(ha->pdev); 259 pci_set_master(ha->pdev);
261 ret = pci_set_mwi(ha->pdev); 260 ret = pci_set_mwi(ha->pdev);
@@ -268,28 +267,12 @@ qla24xx_pci_config(scsi_qla_host_t *ha)
268 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 267 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
269 268
270 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 269 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
271 pcix_cmd_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX); 270 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
272 if (pcix_cmd_reg) { 271 pcix_set_mmrbc(ha->pdev, 2048);
273 uint16_t pcix_cmd;
274
275 pcix_cmd_reg += PCI_X_CMD;
276 pci_read_config_word(ha->pdev, pcix_cmd_reg, &pcix_cmd);
277 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
278 pcix_cmd |= 0x0008;
279 pci_write_config_word(ha->pdev, pcix_cmd_reg, pcix_cmd);
280 }
281 272
282 /* PCIe -- adjust Maximum Read Request Size (2048). */ 273 /* PCIe -- adjust Maximum Read Request Size (2048). */
283 pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 274 if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
284 if (pcie_dctl_reg) { 275 pcie_set_readrq(ha->pdev, 2048);
285 uint16_t pcie_dctl;
286
287 pcie_dctl_reg += PCI_EXP_DEVCTL;
288 pci_read_config_word(ha->pdev, pcie_dctl_reg, &pcie_dctl);
289 pcie_dctl &= ~PCI_EXP_DEVCTL_READRQ;
290 pcie_dctl |= 0x4000;
291 pci_write_config_word(ha->pdev, pcie_dctl_reg, pcie_dctl);
292 }
293 276
294 /* Reset expansion ROM address decode enable */ 277 /* Reset expansion ROM address decode enable */
295 pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); 278 pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);