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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/scsi/qla2xxx/qla_def.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_def.h')
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diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
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1/********************************************************************************
2* QLOGIC LINUX SOFTWARE
3*
4* QLogic ISP2x00 device driver for Linux 2.6.x
5* Copyright (C) 2003-2004 QLogic Corporation
6* (www.qlogic.com)
7*
8* This program is free software; you can redistribute it and/or modify it
9* under the terms of the GNU General Public License as published by the
10* Free Software Foundation; either version 2, or (at your option) any
11* later version.
12*
13* This program is distributed in the hope that it will be useful, but
14* WITHOUT ANY WARRANTY; without even the implied warranty of
15* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16* General Public License for more details.
17**
18******************************************************************************/
19
20#ifndef __QLA_DEF_H
21#define __QLA_DEF_H
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/pci.h>
29#include <linux/dma-mapping.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/dmapool.h>
33#include <linux/mempool.h>
34#include <linux/spinlock.h>
35#include <linux/completion.h>
36#include <asm/semaphore.h>
37
38#include <scsi/scsi.h>
39#include <scsi/scsi_host.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_cmnd.h>
42
43/* XXX(hch): move to pci_ids.h */
44#ifndef PCI_DEVICE_ID_QLOGIC_ISP2300
45#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
46#endif
47
48#ifndef PCI_DEVICE_ID_QLOGIC_ISP2312
49#define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
50#endif
51
52#ifndef PCI_DEVICE_ID_QLOGIC_ISP2322
53#define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
54#endif
55
56#ifndef PCI_DEVICE_ID_QLOGIC_ISP6312
57#define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
58#endif
59
60#ifndef PCI_DEVICE_ID_QLOGIC_ISP6322
61#define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
62#endif
63
64#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
65#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
66#else
67#define IS_QLA2100(ha) 0
68#endif
69
70#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
71#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
72#else
73#define IS_QLA2200(ha) 0
74#endif
75
76#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
77#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
78#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
79#else
80#define IS_QLA2300(ha) 0
81#define IS_QLA2312(ha) 0
82#endif
83
84#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
85#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
86#else
87#define IS_QLA2322(ha) 0
88#endif
89
90#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
91#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
92#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
93#else
94#define IS_QLA6312(ha) 0
95#define IS_QLA6322(ha) 0
96#endif
97
98#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
99 IS_QLA6312(ha) || IS_QLA6322(ha))
100
101/*
102 * Only non-ISP2[12]00 have extended addressing support in the firmware.
103 */
104#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
105
106/*
107 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
108 * but that's fine as we don't look at the last 24 ones for
109 * ISP2100 HBAs.
110 */
111#define MAILBOX_REGISTER_COUNT_2100 8
112#define MAILBOX_REGISTER_COUNT 32
113
114#define QLA2200A_RISC_ROM_VER 4
115#define FPM_2300 6
116#define FPM_2310 7
117
118#include "qla_settings.h"
119
120/*
121 * Data bit definitions
122 */
123#define BIT_0 0x1
124#define BIT_1 0x2
125#define BIT_2 0x4
126#define BIT_3 0x8
127#define BIT_4 0x10
128#define BIT_5 0x20
129#define BIT_6 0x40
130#define BIT_7 0x80
131#define BIT_8 0x100
132#define BIT_9 0x200
133#define BIT_10 0x400
134#define BIT_11 0x800
135#define BIT_12 0x1000
136#define BIT_13 0x2000
137#define BIT_14 0x4000
138#define BIT_15 0x8000
139#define BIT_16 0x10000
140#define BIT_17 0x20000
141#define BIT_18 0x40000
142#define BIT_19 0x80000
143#define BIT_20 0x100000
144#define BIT_21 0x200000
145#define BIT_22 0x400000
146#define BIT_23 0x800000
147#define BIT_24 0x1000000
148#define BIT_25 0x2000000
149#define BIT_26 0x4000000
150#define BIT_27 0x8000000
151#define BIT_28 0x10000000
152#define BIT_29 0x20000000
153#define BIT_30 0x40000000
154#define BIT_31 0x80000000
155
156#define LSB(x) ((uint8_t)(x))
157#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
158
159#define LSW(x) ((uint16_t)(x))
160#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
161
162#define LSD(x) ((uint32_t)((uint64_t)(x)))
163#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
164
165
166/*
167 * I/O register
168*/
169
170#define RD_REG_BYTE(addr) readb(addr)
171#define RD_REG_WORD(addr) readw(addr)
172#define RD_REG_DWORD(addr) readl(addr)
173#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
174#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
175#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
176#define WRT_REG_BYTE(addr, data) writeb(data,addr)
177#define WRT_REG_WORD(addr, data) writew(data,addr)
178#define WRT_REG_DWORD(addr, data) writel(data,addr)
179
180/*
181 * Fibre Channel device definitions.
182 */
183#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
184#define MAX_FIBRE_DEVICES 512
185#define MAX_FIBRE_LUNS 256
186#define MAX_RSCN_COUNT 32
187#define MAX_HOST_COUNT 16
188
189/*
190 * Host adapter default definitions.
191 */
192#define MAX_BUSES 1 /* We only have one bus today */
193#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
194#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
195#define MAX_TARGETS MAX_FIBRE_DEVICES
196#define MIN_LUNS 8
197#define MAX_LUNS MAX_FIBRE_LUNS
198#define MAX_CMDS_PER_LUN 255
199
200/*
201 * Fibre Channel device definitions.
202 */
203#define SNS_LAST_LOOP_ID_2100 0xfe
204#define SNS_LAST_LOOP_ID_2300 0x7ff
205
206#define LAST_LOCAL_LOOP_ID 0x7d
207#define SNS_FL_PORT 0x7e
208#define FABRIC_CONTROLLER 0x7f
209#define SIMPLE_NAME_SERVER 0x80
210#define SNS_FIRST_LOOP_ID 0x81
211#define MANAGEMENT_SERVER 0xfe
212#define BROADCAST 0xff
213
214#define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
215 x < SNS_FIRST_LOOP_ID) || \
216 x == MANAGEMENT_SERVER || \
217 x == BROADCAST)
218
219/*
220 * Timeout timer counts in seconds
221 */
222#define PORT_RETRY_TIME 2
223#define LOOP_DOWN_TIMEOUT 60
224#define LOOP_DOWN_TIME 255 /* 240 */
225#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
226
227/* Maximum outstanding commands in ISP queues (1-65535) */
228#define MAX_OUTSTANDING_COMMANDS 1024
229
230/* ISP request and response entry counts (37-65535) */
231#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
232#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
233#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
234#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
235#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
236
237/*
238 * SCSI Request Block
239 */
240typedef struct srb {
241 struct list_head list;
242
243 struct scsi_qla_host *ha; /* HA the SP is queued on */
244
245 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
246
247 struct timer_list timer; /* Command timer */
248 atomic_t ref_count; /* Reference count for this structure */
249 uint16_t flags;
250
251 /* Request state */
252 uint16_t state;
253
254 /* Target/LUN queue pointers. */
255 struct os_tgt *tgt_queue; /* ptr to visible ha's target */
256 struct os_lun *lun_queue; /* ptr to visible ha's lun */
257 struct fc_lun *fclun; /* FC LUN context pointer. */
258
259 /* Timing counts. */
260 unsigned long e_start; /* Start of extend timeout */
261 unsigned long r_start; /* Start of request */
262 unsigned long u_start; /* When sent to RISC */
263 unsigned long f_start; /* When placed in FO queue*/
264
265 /* Single transfer DMA context */
266 dma_addr_t dma_handle;
267
268 uint32_t request_sense_length;
269 uint8_t *request_sense_ptr;
270
271 int ext_history;
272
273 /* Suspend delay */
274 int delay;
275
276 /* Raw completion info for use by failover ? */
277 uint8_t fo_retry_cnt; /* Retry count this request */
278 uint8_t err_id; /* error id */
279#define SRB_ERR_PORT 1 /* Request failed -- "port down" */
280#define SRB_ERR_LOOP 2 /* Request failed -- "loop down" */
281#define SRB_ERR_DEVICE 3 /* Request failed -- "device error" */
282#define SRB_ERR_OTHER 4
283
284 /* SRB magic number */
285 uint16_t magic;
286#define SRB_MAGIC 0x10CB
287} srb_t;
288
289/*
290 * SRB flag definitions
291 */
292#define SRB_TIMEOUT BIT_0 /* Command timed out */
293#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
294#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
295#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
296
297#define SRB_ABORTED BIT_4 /* Command aborted command already */
298#define SRB_RETRY BIT_5 /* Command needs retrying */
299#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
300#define SRB_FAILOVER BIT_7 /* Command in failover state */
301
302#define SRB_BUSY BIT_8 /* Command is in busy retry state */
303#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
304#define SRB_IOCTL BIT_10 /* IOCTL command. */
305#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
306
307/*
308 * SRB state definitions
309 */
310#define SRB_FREE_STATE 0 /* returned back */
311#define SRB_PENDING_STATE 1 /* queued in LUN Q */
312#define SRB_ACTIVE_STATE 2 /* in Active Array */
313#define SRB_DONE_STATE 3 /* queued in Done Queue */
314#define SRB_RETRY_STATE 4 /* in Retry Queue */
315#define SRB_SUSPENDED_STATE 5 /* in suspended state */
316#define SRB_NO_QUEUE_STATE 6 /* is in between states */
317#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
318#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
319#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
320
321
322/*
323 * ISP I/O Register Set structure definitions.
324 */
325typedef volatile struct {
326 volatile uint16_t flash_address; /* Flash BIOS address */
327 volatile uint16_t flash_data; /* Flash BIOS data */
328 uint16_t unused_1[1]; /* Gap */
329 volatile uint16_t ctrl_status; /* Control/Status */
330#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
331#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
332#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
333
334 volatile uint16_t ictrl; /* Interrupt control */
335#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
336#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
337
338 volatile uint16_t istatus; /* Interrupt status */
339#define ISR_RISC_INT BIT_3 /* RISC interrupt */
340
341 volatile uint16_t semaphore; /* Semaphore */
342 volatile uint16_t nvram; /* NVRAM register. */
343#define NVR_DESELECT 0
344#define NVR_BUSY BIT_15
345#define NVR_WRT_ENABLE BIT_14 /* Write enable */
346#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
347#define NVR_DATA_IN BIT_3
348#define NVR_DATA_OUT BIT_2
349#define NVR_SELECT BIT_1
350#define NVR_CLOCK BIT_0
351
352 union {
353 struct {
354 volatile uint16_t mailbox0;
355 volatile uint16_t mailbox1;
356 volatile uint16_t mailbox2;
357 volatile uint16_t mailbox3;
358 volatile uint16_t mailbox4;
359 volatile uint16_t mailbox5;
360 volatile uint16_t mailbox6;
361 volatile uint16_t mailbox7;
362 uint16_t unused_2[59]; /* Gap */
363 } __attribute__((packed)) isp2100;
364 struct {
365 /* Request Queue */
366 volatile uint16_t req_q_in; /* In-Pointer */
367 volatile uint16_t req_q_out; /* Out-Pointer */
368 /* Response Queue */
369 volatile uint16_t rsp_q_in; /* In-Pointer */
370 volatile uint16_t rsp_q_out; /* Out-Pointer */
371
372 /* RISC to Host Status */
373 volatile uint32_t host_status;
374#define HSR_RISC_INT BIT_15 /* RISC interrupt */
375#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
376
377 /* Host to Host Semaphore */
378 volatile uint16_t host_semaphore;
379 uint16_t unused_3[17]; /* Gap */
380 volatile uint16_t mailbox0;
381 volatile uint16_t mailbox1;
382 volatile uint16_t mailbox2;
383 volatile uint16_t mailbox3;
384 volatile uint16_t mailbox4;
385 volatile uint16_t mailbox5;
386 volatile uint16_t mailbox6;
387 volatile uint16_t mailbox7;
388 volatile uint16_t mailbox8;
389 volatile uint16_t mailbox9;
390 volatile uint16_t mailbox10;
391 volatile uint16_t mailbox11;
392 volatile uint16_t mailbox12;
393 volatile uint16_t mailbox13;
394 volatile uint16_t mailbox14;
395 volatile uint16_t mailbox15;
396 volatile uint16_t mailbox16;
397 volatile uint16_t mailbox17;
398 volatile uint16_t mailbox18;
399 volatile uint16_t mailbox19;
400 volatile uint16_t mailbox20;
401 volatile uint16_t mailbox21;
402 volatile uint16_t mailbox22;
403 volatile uint16_t mailbox23;
404 volatile uint16_t mailbox24;
405 volatile uint16_t mailbox25;
406 volatile uint16_t mailbox26;
407 volatile uint16_t mailbox27;
408 volatile uint16_t mailbox28;
409 volatile uint16_t mailbox29;
410 volatile uint16_t mailbox30;
411 volatile uint16_t mailbox31;
412 volatile uint16_t fb_cmd;
413 uint16_t unused_4[10]; /* Gap */
414 } __attribute__((packed)) isp2300;
415 } u;
416
417 volatile uint16_t fpm_diag_config;
418 uint16_t unused_5[0x6]; /* Gap */
419 volatile uint16_t pcr; /* Processor Control Register. */
420 uint16_t unused_6[0x5]; /* Gap */
421 volatile uint16_t mctr; /* Memory Configuration and Timing. */
422 uint16_t unused_7[0x3]; /* Gap */
423 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
424 uint16_t unused_8[0x3]; /* Gap */
425 volatile uint16_t hccr; /* Host command & control register. */
426#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
427#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
428 /* HCCR commands */
429#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
430#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
431#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
432#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
433#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
434#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
435#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
436#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
437
438 uint16_t unused_9[5]; /* Gap */
439 volatile uint16_t gpiod; /* GPIO Data register. */
440 volatile uint16_t gpioe; /* GPIO Enable register. */
441#define GPIO_LED_MASK 0x00C0
442#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
443#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
444#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
445#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
446
447 union {
448 struct {
449 uint16_t unused_10[8]; /* Gap */
450 volatile uint16_t mailbox8;
451 volatile uint16_t mailbox9;
452 volatile uint16_t mailbox10;
453 volatile uint16_t mailbox11;
454 volatile uint16_t mailbox12;
455 volatile uint16_t mailbox13;
456 volatile uint16_t mailbox14;
457 volatile uint16_t mailbox15;
458 volatile uint16_t mailbox16;
459 volatile uint16_t mailbox17;
460 volatile uint16_t mailbox18;
461 volatile uint16_t mailbox19;
462 volatile uint16_t mailbox20;
463 volatile uint16_t mailbox21;
464 volatile uint16_t mailbox22;
465 volatile uint16_t mailbox23; /* Also probe reg. */
466 } __attribute__((packed)) isp2200;
467 } u_end;
468} device_reg_t;
469
470#define ISP_REQ_Q_IN(ha, reg) \
471 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
472 &(reg)->u.isp2100.mailbox4 : \
473 &(reg)->u.isp2300.req_q_in)
474#define ISP_REQ_Q_OUT(ha, reg) \
475 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
476 &(reg)->u.isp2100.mailbox4 : \
477 &(reg)->u.isp2300.req_q_out)
478#define ISP_RSP_Q_IN(ha, reg) \
479 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
480 &(reg)->u.isp2100.mailbox5 : \
481 &(reg)->u.isp2300.rsp_q_in)
482#define ISP_RSP_Q_OUT(ha, reg) \
483 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
484 &(reg)->u.isp2100.mailbox5 : \
485 &(reg)->u.isp2300.rsp_q_out)
486
487#define MAILBOX_REG(ha, reg, num) \
488 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
489 (num < 8 ? \
490 &(reg)->u.isp2100.mailbox0 + (num) : \
491 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
492 &(reg)->u.isp2300.mailbox0 + (num))
493#define RD_MAILBOX_REG(ha, reg, num) \
494 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
495#define WRT_MAILBOX_REG(ha, reg, num, data) \
496 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
497
498#define FB_CMD_REG(ha, reg) \
499 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
500 &(reg)->fb_cmd_2100 : \
501 &(reg)->u.isp2300.fb_cmd)
502#define RD_FB_CMD_REG(ha, reg) \
503 RD_REG_WORD(FB_CMD_REG(ha, reg))
504#define WRT_FB_CMD_REG(ha, reg, data) \
505 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
506
507typedef struct {
508 uint32_t out_mb; /* outbound from driver */
509 uint32_t in_mb; /* Incoming from RISC */
510 uint16_t mb[MAILBOX_REGISTER_COUNT];
511 long buf_size;
512 void *bufp;
513 uint32_t tov;
514 uint8_t flags;
515#define MBX_DMA_IN BIT_0
516#define MBX_DMA_OUT BIT_1
517#define IOCTL_CMD BIT_2
518} mbx_cmd_t;
519
520#define MBX_TOV_SECONDS 30
521
522/*
523 * ISP product identification definitions in mailboxes after reset.
524 */
525#define PROD_ID_1 0x4953
526#define PROD_ID_2 0x0000
527#define PROD_ID_2a 0x5020
528#define PROD_ID_3 0x2020
529
530/*
531 * ISP mailbox Self-Test status codes
532 */
533#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
534#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
535#define MBS_BUSY 4 /* Busy. */
536
537/*
538 * ISP mailbox command complete status codes
539 */
540#define MBS_COMMAND_COMPLETE 0x4000
541#define MBS_INVALID_COMMAND 0x4001
542#define MBS_HOST_INTERFACE_ERROR 0x4002
543#define MBS_TEST_FAILED 0x4003
544#define MBS_COMMAND_ERROR 0x4005
545#define MBS_COMMAND_PARAMETER_ERROR 0x4006
546#define MBS_PORT_ID_USED 0x4007
547#define MBS_LOOP_ID_USED 0x4008
548#define MBS_ALL_IDS_IN_USE 0x4009
549#define MBS_NOT_LOGGED_IN 0x400A
550
551/*
552 * ISP mailbox asynchronous event status codes
553 */
554#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
555#define MBA_RESET 0x8001 /* Reset Detected. */
556#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
557#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
558#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
559#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
560#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
561 /* occurred. */
562#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
563#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
564#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
565#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
566#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
567#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
568#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
569#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
570#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
571#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
572#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
573#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
574#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
575#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
576#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
577#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
578 /* used. */
579#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
580#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
581#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
582#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
583#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
584#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
585#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
586#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
587#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
588#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
589#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
590#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
591#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
592
593/*
594 * Firmware options 1, 2, 3.
595 */
596#define FO1_AE_ON_LIPF8 BIT_0
597#define FO1_AE_ALL_LIP_RESET BIT_1
598#define FO1_CTIO_RETRY BIT_3
599#define FO1_DISABLE_LIP_F7_SW BIT_4
600#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
601#define FO1_DISABLE_GPIO6_7 BIT_6
602#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
603#define FO1_SET_EMPHASIS_SWING BIT_8
604#define FO1_AE_AUTO_BYPASS BIT_9
605#define FO1_ENABLE_PURE_IOCB BIT_10
606#define FO1_AE_PLOGI_RJT BIT_11
607#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
608#define FO1_AE_QUEUE_FULL BIT_13
609
610#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
611#define FO2_REV_LOOPBACK BIT_1
612
613#define FO3_ENABLE_EMERG_IOCB BIT_0
614#define FO3_AE_RND_ERROR BIT_1
615
616/*
617 * ISP mailbox commands
618 */
619#define MBC_LOAD_RAM 1 /* Load RAM. */
620#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
621#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
622#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
623#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
624#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
625#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
626#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
627#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
628#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
629#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
630#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
631#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
632#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
633#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
634#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
635#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
636#define MBC_RESET 0x18 /* Reset. */
637#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
638#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
639#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
640#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
641#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
642#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
643#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
644#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
645#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
646#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
647#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
648#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
649#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
650#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
651#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
652#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
653#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
654#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
655#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
656#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
657#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
658#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
659 /* Initialization Procedure */
660#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
661#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
662#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
663#define MBC_TARGET_RESET 0x66 /* Target Reset. */
664#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
665#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
666#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
667#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
668#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
669#define MBC_LIP_RESET 0x6c /* LIP reset. */
670#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
671 /* commandd. */
672#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
673#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
674#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
675#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
676#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
677#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
678#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
679#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
680#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
681#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
682#define MBC_LUN_RESET 0x7E /* Send LUN reset */
683
684/* Firmware return data sizes */
685#define FCAL_MAP_SIZE 128
686
687/* Mailbox bit definitions for out_mb and in_mb */
688#define MBX_31 BIT_31
689#define MBX_30 BIT_30
690#define MBX_29 BIT_29
691#define MBX_28 BIT_28
692#define MBX_27 BIT_27
693#define MBX_26 BIT_26
694#define MBX_25 BIT_25
695#define MBX_24 BIT_24
696#define MBX_23 BIT_23
697#define MBX_22 BIT_22
698#define MBX_21 BIT_21
699#define MBX_20 BIT_20
700#define MBX_19 BIT_19
701#define MBX_18 BIT_18
702#define MBX_17 BIT_17
703#define MBX_16 BIT_16
704#define MBX_15 BIT_15
705#define MBX_14 BIT_14
706#define MBX_13 BIT_13
707#define MBX_12 BIT_12
708#define MBX_11 BIT_11
709#define MBX_10 BIT_10
710#define MBX_9 BIT_9
711#define MBX_8 BIT_8
712#define MBX_7 BIT_7
713#define MBX_6 BIT_6
714#define MBX_5 BIT_5
715#define MBX_4 BIT_4
716#define MBX_3 BIT_3
717#define MBX_2 BIT_2
718#define MBX_1 BIT_1
719#define MBX_0 BIT_0
720
721/*
722 * Firmware state codes from get firmware state mailbox command
723 */
724#define FSTATE_CONFIG_WAIT 0
725#define FSTATE_WAIT_AL_PA 1
726#define FSTATE_WAIT_LOGIN 2
727#define FSTATE_READY 3
728#define FSTATE_LOSS_OF_SYNC 4
729#define FSTATE_ERROR 5
730#define FSTATE_REINIT 6
731#define FSTATE_NON_PART 7
732
733#define FSTATE_CONFIG_CORRECT 0
734#define FSTATE_P2P_RCV_LIP 1
735#define FSTATE_P2P_CHOOSE_LOOP 2
736#define FSTATE_P2P_RCV_UNIDEN_LIP 3
737#define FSTATE_FATAL_ERROR 4
738#define FSTATE_LOOP_BACK_CONN 5
739
740/*
741 * Port Database structure definition
742 * Little endian except where noted.
743 */
744#define PORT_DATABASE_SIZE 128 /* bytes */
745typedef struct {
746 uint8_t options;
747 uint8_t control;
748 uint8_t master_state;
749 uint8_t slave_state;
750 uint8_t reserved[2];
751 uint8_t hard_address;
752 uint8_t reserved_1;
753 uint8_t port_id[4];
754 uint8_t node_name[WWN_SIZE];
755 uint8_t port_name[WWN_SIZE];
756 uint16_t execution_throttle;
757 uint16_t execution_count;
758 uint8_t reset_count;
759 uint8_t reserved_2;
760 uint16_t resource_allocation;
761 uint16_t current_allocation;
762 uint16_t queue_head;
763 uint16_t queue_tail;
764 uint16_t transmit_execution_list_next;
765 uint16_t transmit_execution_list_previous;
766 uint16_t common_features;
767 uint16_t total_concurrent_sequences;
768 uint16_t RO_by_information_category;
769 uint8_t recipient;
770 uint8_t initiator;
771 uint16_t receive_data_size;
772 uint16_t concurrent_sequences;
773 uint16_t open_sequences_per_exchange;
774 uint16_t lun_abort_flags;
775 uint16_t lun_stop_flags;
776 uint16_t stop_queue_head;
777 uint16_t stop_queue_tail;
778 uint16_t port_retry_timer;
779 uint16_t next_sequence_id;
780 uint16_t frame_count;
781 uint16_t PRLI_payload_length;
782 uint8_t prli_svc_param_word_0[2]; /* Big endian */
783 /* Bits 15-0 of word 0 */
784 uint8_t prli_svc_param_word_3[2]; /* Big endian */
785 /* Bits 15-0 of word 3 */
786 uint16_t loop_id;
787 uint16_t extended_lun_info_list_pointer;
788 uint16_t extended_lun_stop_list_pointer;
789} port_database_t;
790
791/*
792 * Port database slave/master states
793 */
794#define PD_STATE_DISCOVERY 0
795#define PD_STATE_WAIT_DISCOVERY_ACK 1
796#define PD_STATE_PORT_LOGIN 2
797#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
798#define PD_STATE_PROCESS_LOGIN 4
799#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
800#define PD_STATE_PORT_LOGGED_IN 6
801#define PD_STATE_PORT_UNAVAILABLE 7
802#define PD_STATE_PROCESS_LOGOUT 8
803#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
804#define PD_STATE_PORT_LOGOUT 10
805#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
806
807
808/*
809 * ISP Initialization Control Block.
810 * Little endian except where noted.
811 */
812#define ICB_VERSION 1
813typedef struct {
814 uint8_t version;
815 uint8_t reserved_1;
816
817 /*
818 * LSB BIT 0 = Enable Hard Loop Id
819 * LSB BIT 1 = Enable Fairness
820 * LSB BIT 2 = Enable Full-Duplex
821 * LSB BIT 3 = Enable Fast Posting
822 * LSB BIT 4 = Enable Target Mode
823 * LSB BIT 5 = Disable Initiator Mode
824 * LSB BIT 6 = Enable ADISC
825 * LSB BIT 7 = Enable Target Inquiry Data
826 *
827 * MSB BIT 0 = Enable PDBC Notify
828 * MSB BIT 1 = Non Participating LIP
829 * MSB BIT 2 = Descending Loop ID Search
830 * MSB BIT 3 = Acquire Loop ID in LIPA
831 * MSB BIT 4 = Stop PortQ on Full Status
832 * MSB BIT 5 = Full Login after LIP
833 * MSB BIT 6 = Node Name Option
834 * MSB BIT 7 = Ext IFWCB enable bit
835 */
836 uint8_t firmware_options[2];
837
838 uint16_t frame_payload_size;
839 uint16_t max_iocb_allocation;
840 uint16_t execution_throttle;
841 uint8_t retry_count;
842 uint8_t retry_delay; /* unused */
843 uint8_t port_name[WWN_SIZE]; /* Big endian. */
844 uint16_t hard_address;
845 uint8_t inquiry_data;
846 uint8_t login_timeout;
847 uint8_t node_name[WWN_SIZE]; /* Big endian. */
848
849 uint16_t request_q_outpointer;
850 uint16_t response_q_inpointer;
851 uint16_t request_q_length;
852 uint16_t response_q_length;
853 uint32_t request_q_address[2];
854 uint32_t response_q_address[2];
855
856 uint16_t lun_enables;
857 uint8_t command_resource_count;
858 uint8_t immediate_notify_resource_count;
859 uint16_t timeout;
860 uint8_t reserved_2[2];
861
862 /*
863 * LSB BIT 0 = Timer Operation mode bit 0
864 * LSB BIT 1 = Timer Operation mode bit 1
865 * LSB BIT 2 = Timer Operation mode bit 2
866 * LSB BIT 3 = Timer Operation mode bit 3
867 * LSB BIT 4 = Init Config Mode bit 0
868 * LSB BIT 5 = Init Config Mode bit 1
869 * LSB BIT 6 = Init Config Mode bit 2
870 * LSB BIT 7 = Enable Non part on LIHA failure
871 *
872 * MSB BIT 0 = Enable class 2
873 * MSB BIT 1 = Enable ACK0
874 * MSB BIT 2 =
875 * MSB BIT 3 =
876 * MSB BIT 4 = FC Tape Enable
877 * MSB BIT 5 = Enable FC Confirm
878 * MSB BIT 6 = Enable command queuing in target mode
879 * MSB BIT 7 = No Logo On Link Down
880 */
881 uint8_t add_firmware_options[2];
882
883 uint8_t response_accumulation_timer;
884 uint8_t interrupt_delay_timer;
885
886 /*
887 * LSB BIT 0 = Enable Read xfr_rdy
888 * LSB BIT 1 = Soft ID only
889 * LSB BIT 2 =
890 * LSB BIT 3 =
891 * LSB BIT 4 = FCP RSP Payload [0]
892 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
893 * LSB BIT 6 = Enable Out-of-Order frame handling
894 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
895 *
896 * MSB BIT 0 = Sbus enable - 2300
897 * MSB BIT 1 =
898 * MSB BIT 2 =
899 * MSB BIT 3 =
900 * MSB BIT 4 =
901 * MSB BIT 5 = enable 50 ohm termination
902 * MSB BIT 6 = Data Rate (2300 only)
903 * MSB BIT 7 = Data Rate (2300 only)
904 */
905 uint8_t special_options[2];
906
907 uint8_t reserved_3[26];
908} init_cb_t;
909
910/*
911 * Get Link Status mailbox command return buffer.
912 */
913typedef struct {
914 uint32_t link_fail_cnt;
915 uint32_t loss_sync_cnt;
916 uint32_t loss_sig_cnt;
917 uint32_t prim_seq_err_cnt;
918 uint32_t inval_xmit_word_cnt;
919 uint32_t inval_crc_cnt;
920} link_stat_t;
921
922/*
923 * NVRAM Command values.
924 */
925#define NV_START_BIT BIT_2
926#define NV_WRITE_OP (BIT_26+BIT_24)
927#define NV_READ_OP (BIT_26+BIT_25)
928#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
929#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
930#define NV_DELAY_COUNT 10
931
932/*
933 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
934 */
935typedef struct {
936 /*
937 * NVRAM header
938 */
939 uint8_t id[4];
940 uint8_t nvram_version;
941 uint8_t reserved_0;
942
943 /*
944 * NVRAM RISC parameter block
945 */
946 uint8_t parameter_block_version;
947 uint8_t reserved_1;
948
949 /*
950 * LSB BIT 0 = Enable Hard Loop Id
951 * LSB BIT 1 = Enable Fairness
952 * LSB BIT 2 = Enable Full-Duplex
953 * LSB BIT 3 = Enable Fast Posting
954 * LSB BIT 4 = Enable Target Mode
955 * LSB BIT 5 = Disable Initiator Mode
956 * LSB BIT 6 = Enable ADISC
957 * LSB BIT 7 = Enable Target Inquiry Data
958 *
959 * MSB BIT 0 = Enable PDBC Notify
960 * MSB BIT 1 = Non Participating LIP
961 * MSB BIT 2 = Descending Loop ID Search
962 * MSB BIT 3 = Acquire Loop ID in LIPA
963 * MSB BIT 4 = Stop PortQ on Full Status
964 * MSB BIT 5 = Full Login after LIP
965 * MSB BIT 6 = Node Name Option
966 * MSB BIT 7 = Ext IFWCB enable bit
967 */
968 uint8_t firmware_options[2];
969
970 uint16_t frame_payload_size;
971 uint16_t max_iocb_allocation;
972 uint16_t execution_throttle;
973 uint8_t retry_count;
974 uint8_t retry_delay; /* unused */
975 uint8_t port_name[WWN_SIZE]; /* Big endian. */
976 uint16_t hard_address;
977 uint8_t inquiry_data;
978 uint8_t login_timeout;
979 uint8_t node_name[WWN_SIZE]; /* Big endian. */
980
981 /*
982 * LSB BIT 0 = Timer Operation mode bit 0
983 * LSB BIT 1 = Timer Operation mode bit 1
984 * LSB BIT 2 = Timer Operation mode bit 2
985 * LSB BIT 3 = Timer Operation mode bit 3
986 * LSB BIT 4 = Init Config Mode bit 0
987 * LSB BIT 5 = Init Config Mode bit 1
988 * LSB BIT 6 = Init Config Mode bit 2
989 * LSB BIT 7 = Enable Non part on LIHA failure
990 *
991 * MSB BIT 0 = Enable class 2
992 * MSB BIT 1 = Enable ACK0
993 * MSB BIT 2 =
994 * MSB BIT 3 =
995 * MSB BIT 4 = FC Tape Enable
996 * MSB BIT 5 = Enable FC Confirm
997 * MSB BIT 6 = Enable command queuing in target mode
998 * MSB BIT 7 = No Logo On Link Down
999 */
1000 uint8_t add_firmware_options[2];
1001
1002 uint8_t response_accumulation_timer;
1003 uint8_t interrupt_delay_timer;
1004
1005 /*
1006 * LSB BIT 0 = Enable Read xfr_rdy
1007 * LSB BIT 1 = Soft ID only
1008 * LSB BIT 2 =
1009 * LSB BIT 3 =
1010 * LSB BIT 4 = FCP RSP Payload [0]
1011 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1012 * LSB BIT 6 = Enable Out-of-Order frame handling
1013 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1014 *
1015 * MSB BIT 0 = Sbus enable - 2300
1016 * MSB BIT 1 =
1017 * MSB BIT 2 =
1018 * MSB BIT 3 =
1019 * MSB BIT 4 =
1020 * MSB BIT 5 = enable 50 ohm termination
1021 * MSB BIT 6 = Data Rate (2300 only)
1022 * MSB BIT 7 = Data Rate (2300 only)
1023 */
1024 uint8_t special_options[2];
1025
1026 /* Reserved for expanded RISC parameter block */
1027 uint8_t reserved_2[22];
1028
1029 /*
1030 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1031 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1032 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1033 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1034 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1035 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1036 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1037 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1038 *
1039 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1040 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1041 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1042 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1043 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1044 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1045 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1046 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1047 *
1048 * LSB BIT 0 = Output Swing 1G bit 0
1049 * LSB BIT 1 = Output Swing 1G bit 1
1050 * LSB BIT 2 = Output Swing 1G bit 2
1051 * LSB BIT 3 = Output Emphasis 1G bit 0
1052 * LSB BIT 4 = Output Emphasis 1G bit 1
1053 * LSB BIT 5 = Output Swing 2G bit 0
1054 * LSB BIT 6 = Output Swing 2G bit 1
1055 * LSB BIT 7 = Output Swing 2G bit 2
1056 *
1057 * MSB BIT 0 = Output Emphasis 2G bit 0
1058 * MSB BIT 1 = Output Emphasis 2G bit 1
1059 * MSB BIT 2 = Output Enable
1060 * MSB BIT 3 =
1061 * MSB BIT 4 =
1062 * MSB BIT 5 =
1063 * MSB BIT 6 =
1064 * MSB BIT 7 =
1065 */
1066 uint8_t seriallink_options[4];
1067
1068 /*
1069 * NVRAM host parameter block
1070 *
1071 * LSB BIT 0 = Enable spinup delay
1072 * LSB BIT 1 = Disable BIOS
1073 * LSB BIT 2 = Enable Memory Map BIOS
1074 * LSB BIT 3 = Enable Selectable Boot
1075 * LSB BIT 4 = Disable RISC code load
1076 * LSB BIT 5 = Set cache line size 1
1077 * LSB BIT 6 = PCI Parity Disable
1078 * LSB BIT 7 = Enable extended logging
1079 *
1080 * MSB BIT 0 = Enable 64bit addressing
1081 * MSB BIT 1 = Enable lip reset
1082 * MSB BIT 2 = Enable lip full login
1083 * MSB BIT 3 = Enable target reset
1084 * MSB BIT 4 = Enable database storage
1085 * MSB BIT 5 = Enable cache flush read
1086 * MSB BIT 6 = Enable database load
1087 * MSB BIT 7 = Enable alternate WWN
1088 */
1089 uint8_t host_p[2];
1090
1091 uint8_t boot_node_name[WWN_SIZE];
1092 uint8_t boot_lun_number;
1093 uint8_t reset_delay;
1094 uint8_t port_down_retry_count;
1095 uint8_t boot_id_number;
1096 uint16_t max_luns_per_target;
1097 uint8_t fcode_boot_port_name[WWN_SIZE];
1098 uint8_t alternate_port_name[WWN_SIZE];
1099 uint8_t alternate_node_name[WWN_SIZE];
1100
1101 /*
1102 * BIT 0 = Selective Login
1103 * BIT 1 = Alt-Boot Enable
1104 * BIT 2 =
1105 * BIT 3 = Boot Order List
1106 * BIT 4 =
1107 * BIT 5 = Selective LUN
1108 * BIT 6 =
1109 * BIT 7 = unused
1110 */
1111 uint8_t efi_parameters;
1112
1113 uint8_t link_down_timeout;
1114
1115 uint8_t adapter_id_0[4];
1116 uint8_t adapter_id_1[4];
1117 uint8_t adapter_id_2[4];
1118 uint8_t adapter_id_3[4];
1119
1120 uint8_t alt1_boot_node_name[WWN_SIZE];
1121 uint16_t alt1_boot_lun_number;
1122 uint8_t alt2_boot_node_name[WWN_SIZE];
1123 uint16_t alt2_boot_lun_number;
1124 uint8_t alt3_boot_node_name[WWN_SIZE];
1125 uint16_t alt3_boot_lun_number;
1126 uint8_t alt4_boot_node_name[WWN_SIZE];
1127 uint16_t alt4_boot_lun_number;
1128 uint8_t alt5_boot_node_name[WWN_SIZE];
1129 uint16_t alt5_boot_lun_number;
1130 uint8_t alt6_boot_node_name[WWN_SIZE];
1131 uint16_t alt6_boot_lun_number;
1132 uint8_t alt7_boot_node_name[WWN_SIZE];
1133 uint16_t alt7_boot_lun_number;
1134
1135 uint8_t reserved_3[2];
1136
1137 /* Offset 200-215 : Model Number */
1138 uint8_t model_number[16];
1139
1140 /* OEM related items */
1141 uint8_t oem_specific[16];
1142
1143 /*
1144 * NVRAM Adapter Features offset 232-239
1145 *
1146 * LSB BIT 0 = External GBIC
1147 * LSB BIT 1 = Risc RAM parity
1148 * LSB BIT 2 = Buffer Plus Module
1149 * LSB BIT 3 = Multi Chip Adapter
1150 * LSB BIT 4 = Internal connector
1151 * LSB BIT 5 =
1152 * LSB BIT 6 =
1153 * LSB BIT 7 =
1154 *
1155 * MSB BIT 0 =
1156 * MSB BIT 1 =
1157 * MSB BIT 2 =
1158 * MSB BIT 3 =
1159 * MSB BIT 4 =
1160 * MSB BIT 5 =
1161 * MSB BIT 6 =
1162 * MSB BIT 7 =
1163 */
1164 uint8_t adapter_features[2];
1165
1166 uint8_t reserved_4[16];
1167
1168 /* Subsystem vendor ID for ISP2200 */
1169 uint16_t subsystem_vendor_id_2200;
1170
1171 /* Subsystem device ID for ISP2200 */
1172 uint16_t subsystem_device_id_2200;
1173
1174 uint8_t reserved_5;
1175 uint8_t checksum;
1176} nvram_t;
1177
1178/*
1179 * ISP queue - response queue entry definition.
1180 */
1181typedef struct {
1182 uint8_t data[60];
1183 uint32_t signature;
1184#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1185} response_t;
1186
1187typedef union {
1188 uint16_t extended;
1189 struct {
1190 uint8_t reserved;
1191 uint8_t standard;
1192 } id;
1193} target_id_t;
1194
1195#define SET_TARGET_ID(ha, to, from) \
1196do { \
1197 if (HAS_EXTENDED_IDS(ha)) \
1198 to.extended = cpu_to_le16(from); \
1199 else \
1200 to.id.standard = (uint8_t)from; \
1201} while (0)
1202
1203/*
1204 * ISP queue - command entry structure definition.
1205 */
1206#define COMMAND_TYPE 0x11 /* Command entry */
1207#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1208typedef struct {
1209 uint8_t entry_type; /* Entry type. */
1210 uint8_t entry_count; /* Entry count. */
1211 uint8_t sys_define; /* System defined. */
1212 uint8_t entry_status; /* Entry Status. */
1213 uint32_t handle; /* System handle. */
1214 target_id_t target; /* SCSI ID */
1215 uint16_t lun; /* SCSI LUN */
1216 uint16_t control_flags; /* Control flags. */
1217#define CF_WRITE BIT_6
1218#define CF_READ BIT_5
1219#define CF_SIMPLE_TAG BIT_3
1220#define CF_ORDERED_TAG BIT_2
1221#define CF_HEAD_TAG BIT_1
1222 uint16_t reserved_1;
1223 uint16_t timeout; /* Command timeout. */
1224 uint16_t dseg_count; /* Data segment count. */
1225 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1226 uint32_t byte_count; /* Total byte count. */
1227 uint32_t dseg_0_address; /* Data segment 0 address. */
1228 uint32_t dseg_0_length; /* Data segment 0 length. */
1229 uint32_t dseg_1_address; /* Data segment 1 address. */
1230 uint32_t dseg_1_length; /* Data segment 1 length. */
1231 uint32_t dseg_2_address; /* Data segment 2 address. */
1232 uint32_t dseg_2_length; /* Data segment 2 length. */
1233} cmd_entry_t;
1234
1235/*
1236 * ISP queue - 64-Bit addressing, command entry structure definition.
1237 */
1238#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1239typedef struct {
1240 uint8_t entry_type; /* Entry type. */
1241 uint8_t entry_count; /* Entry count. */
1242 uint8_t sys_define; /* System defined. */
1243 uint8_t entry_status; /* Entry Status. */
1244 uint32_t handle; /* System handle. */
1245 target_id_t target; /* SCSI ID */
1246 uint16_t lun; /* SCSI LUN */
1247 uint16_t control_flags; /* Control flags. */
1248 uint16_t reserved_1;
1249 uint16_t timeout; /* Command timeout. */
1250 uint16_t dseg_count; /* Data segment count. */
1251 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1252 uint32_t byte_count; /* Total byte count. */
1253 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1254 uint32_t dseg_0_length; /* Data segment 0 length. */
1255 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1256 uint32_t dseg_1_length; /* Data segment 1 length. */
1257} cmd_a64_entry_t, request_t;
1258
1259/*
1260 * ISP queue - continuation entry structure definition.
1261 */
1262#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1263typedef struct {
1264 uint8_t entry_type; /* Entry type. */
1265 uint8_t entry_count; /* Entry count. */
1266 uint8_t sys_define; /* System defined. */
1267 uint8_t entry_status; /* Entry Status. */
1268 uint32_t reserved;
1269 uint32_t dseg_0_address; /* Data segment 0 address. */
1270 uint32_t dseg_0_length; /* Data segment 0 length. */
1271 uint32_t dseg_1_address; /* Data segment 1 address. */
1272 uint32_t dseg_1_length; /* Data segment 1 length. */
1273 uint32_t dseg_2_address; /* Data segment 2 address. */
1274 uint32_t dseg_2_length; /* Data segment 2 length. */
1275 uint32_t dseg_3_address; /* Data segment 3 address. */
1276 uint32_t dseg_3_length; /* Data segment 3 length. */
1277 uint32_t dseg_4_address; /* Data segment 4 address. */
1278 uint32_t dseg_4_length; /* Data segment 4 length. */
1279 uint32_t dseg_5_address; /* Data segment 5 address. */
1280 uint32_t dseg_5_length; /* Data segment 5 length. */
1281 uint32_t dseg_6_address; /* Data segment 6 address. */
1282 uint32_t dseg_6_length; /* Data segment 6 length. */
1283} cont_entry_t;
1284
1285/*
1286 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1287 */
1288#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1289typedef struct {
1290 uint8_t entry_type; /* Entry type. */
1291 uint8_t entry_count; /* Entry count. */
1292 uint8_t sys_define; /* System defined. */
1293 uint8_t entry_status; /* Entry Status. */
1294 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1295 uint32_t dseg_0_length; /* Data segment 0 length. */
1296 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1297 uint32_t dseg_1_length; /* Data segment 1 length. */
1298 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1299 uint32_t dseg_2_length; /* Data segment 2 length. */
1300 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1301 uint32_t dseg_3_length; /* Data segment 3 length. */
1302 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1303 uint32_t dseg_4_length; /* Data segment 4 length. */
1304} cont_a64_entry_t;
1305
1306/*
1307 * ISP queue - status entry structure definition.
1308 */
1309#define STATUS_TYPE 0x03 /* Status entry. */
1310typedef struct {
1311 uint8_t entry_type; /* Entry type. */
1312 uint8_t entry_count; /* Entry count. */
1313 uint8_t sys_define; /* System defined. */
1314 uint8_t entry_status; /* Entry Status. */
1315 uint32_t handle; /* System handle. */
1316 uint16_t scsi_status; /* SCSI status. */
1317 uint16_t comp_status; /* Completion status. */
1318 uint16_t state_flags; /* State flags. */
1319 uint16_t status_flags; /* Status flags. */
1320 uint16_t rsp_info_len; /* Response Info Length. */
1321 uint16_t req_sense_length; /* Request sense data length. */
1322 uint32_t residual_length; /* Residual transfer length. */
1323 uint8_t rsp_info[8]; /* FCP response information. */
1324 uint8_t req_sense_data[32]; /* Request sense data. */
1325} sts_entry_t;
1326
1327/*
1328 * Status entry entry status
1329 */
1330#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1331#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1332#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1333#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1334#define RF_BUSY BIT_1 /* Busy */
1335
1336/*
1337 * Status entry SCSI status bit definitions.
1338 */
1339#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1340#define SS_RESIDUAL_UNDER BIT_11
1341#define SS_RESIDUAL_OVER BIT_10
1342#define SS_SENSE_LEN_VALID BIT_9
1343#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1344
1345#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1346#define SS_BUSY_CONDITION BIT_3
1347#define SS_CONDITION_MET BIT_2
1348#define SS_CHECK_CONDITION BIT_1
1349
1350/*
1351 * Status entry completion status
1352 */
1353#define CS_COMPLETE 0x0 /* No errors */
1354#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1355#define CS_DMA 0x2 /* A DMA direction error. */
1356#define CS_TRANSPORT 0x3 /* Transport error. */
1357#define CS_RESET 0x4 /* SCSI bus reset occurred */
1358#define CS_ABORTED 0x5 /* System aborted command. */
1359#define CS_TIMEOUT 0x6 /* Timeout error. */
1360#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1361
1362#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1363#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1364#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1365 /* (selection timeout) */
1366#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1367#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1368#define CS_PORT_BUSY 0x2B /* Port Busy */
1369#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1370#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1371#define CS_UNKNOWN 0x81 /* Driver defined */
1372#define CS_RETRY 0x82 /* Driver defined */
1373#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1374
1375/*
1376 * Status entry status flags
1377 */
1378#define SF_ABTS_TERMINATED BIT_10
1379#define SF_LOGOUT_SENT BIT_13
1380
1381/*
1382 * ISP queue - status continuation entry structure definition.
1383 */
1384#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1385typedef struct {
1386 uint8_t entry_type; /* Entry type. */
1387 uint8_t entry_count; /* Entry count. */
1388 uint8_t sys_define; /* System defined. */
1389 uint8_t entry_status; /* Entry Status. */
1390 uint8_t data[60]; /* data */
1391} sts_cont_entry_t;
1392
1393/*
1394 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1395 * structure definition.
1396 */
1397#define STATUS_TYPE_21 0x21 /* Status entry. */
1398typedef struct {
1399 uint8_t entry_type; /* Entry type. */
1400 uint8_t entry_count; /* Entry count. */
1401 uint8_t handle_count; /* Handle count. */
1402 uint8_t entry_status; /* Entry Status. */
1403 uint32_t handle[15]; /* System handles. */
1404} sts21_entry_t;
1405
1406/*
1407 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1408 * structure definition.
1409 */
1410#define STATUS_TYPE_22 0x22 /* Status entry. */
1411typedef struct {
1412 uint8_t entry_type; /* Entry type. */
1413 uint8_t entry_count; /* Entry count. */
1414 uint8_t handle_count; /* Handle count. */
1415 uint8_t entry_status; /* Entry Status. */
1416 uint16_t handle[30]; /* System handles. */
1417} sts22_entry_t;
1418
1419/*
1420 * ISP queue - marker entry structure definition.
1421 */
1422#define MARKER_TYPE 0x04 /* Marker entry. */
1423typedef struct {
1424 uint8_t entry_type; /* Entry type. */
1425 uint8_t entry_count; /* Entry count. */
1426 uint8_t handle_count; /* Handle count. */
1427 uint8_t entry_status; /* Entry Status. */
1428 uint32_t sys_define_2; /* System defined. */
1429 target_id_t target; /* SCSI ID */
1430 uint8_t modifier; /* Modifier (7-0). */
1431#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1432#define MK_SYNC_ID 1 /* Synchronize ID */
1433#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1434#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1435 /* clear port changed, */
1436 /* use sequence number. */
1437 uint8_t reserved_1;
1438 uint16_t sequence_number; /* Sequence number of event */
1439 uint16_t lun; /* SCSI LUN */
1440 uint8_t reserved_2[48];
1441} mrk_entry_t;
1442
1443/*
1444 * ISP queue - Management Server entry structure definition.
1445 */
1446#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1447typedef struct {
1448 uint8_t entry_type; /* Entry type. */
1449 uint8_t entry_count; /* Entry count. */
1450 uint8_t handle_count; /* Handle count. */
1451 uint8_t entry_status; /* Entry Status. */
1452 uint32_t handle1; /* System handle. */
1453 target_id_t loop_id;
1454 uint16_t status;
1455 uint16_t control_flags; /* Control flags. */
1456 uint16_t reserved2;
1457 uint16_t timeout;
1458 uint16_t cmd_dsd_count;
1459 uint16_t total_dsd_count;
1460 uint8_t type;
1461 uint8_t r_ctl;
1462 uint16_t rx_id;
1463 uint16_t reserved3;
1464 uint32_t handle2;
1465 uint32_t rsp_bytecount;
1466 uint32_t req_bytecount;
1467 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1468 uint32_t dseg_req_length; /* Data segment 0 length. */
1469 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1470 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1471} ms_iocb_entry_t;
1472
1473
1474/*
1475 * ISP queue - Mailbox Command entry structure definition.
1476 */
1477#define MBX_IOCB_TYPE 0x39
1478struct mbx_entry {
1479 uint8_t entry_type;
1480 uint8_t entry_count;
1481 uint8_t sys_define1;
1482 /* Use sys_define1 for source type */
1483#define SOURCE_SCSI 0x00
1484#define SOURCE_IP 0x01
1485#define SOURCE_VI 0x02
1486#define SOURCE_SCTP 0x03
1487#define SOURCE_MP 0x04
1488#define SOURCE_MPIOCTL 0x05
1489#define SOURCE_ASYNC_IOCB 0x07
1490
1491 uint8_t entry_status;
1492
1493 uint32_t handle;
1494 target_id_t loop_id;
1495
1496 uint16_t status;
1497 uint16_t state_flags;
1498 uint16_t status_flags;
1499
1500 uint32_t sys_define2[2];
1501
1502 uint16_t mb0;
1503 uint16_t mb1;
1504 uint16_t mb2;
1505 uint16_t mb3;
1506 uint16_t mb6;
1507 uint16_t mb7;
1508 uint16_t mb9;
1509 uint16_t mb10;
1510 uint32_t reserved_2[2];
1511 uint8_t node_name[WWN_SIZE];
1512 uint8_t port_name[WWN_SIZE];
1513};
1514
1515/*
1516 * ISP request and response queue entry sizes
1517 */
1518#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1519#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1520
1521
1522/*
1523 * 24 bit port ID type definition.
1524 */
1525typedef union {
1526 uint32_t b24 : 24;
1527
1528 struct {
1529 uint8_t d_id[3];
1530 uint8_t rsvd_1;
1531 } r;
1532
1533 struct {
1534 uint8_t al_pa;
1535 uint8_t area;
1536 uint8_t domain;
1537 uint8_t rsvd_1;
1538 } b;
1539} port_id_t;
1540#define INVALID_PORT_ID 0xFFFFFF
1541
1542/*
1543 * Switch info gathering structure.
1544 */
1545typedef struct {
1546 port_id_t d_id;
1547 uint8_t node_name[WWN_SIZE];
1548 uint8_t port_name[WWN_SIZE];
1549 uint32_t type;
1550#define SW_TYPE_IP BIT_1
1551#define SW_TYPE_SCSI BIT_0
1552} sw_info_t;
1553
1554/*
1555 * Inquiry command structure.
1556 */
1557#define INQ_DATA_SIZE 36
1558
1559/*
1560 * Inquiry mailbox IOCB packet definition.
1561 */
1562typedef struct {
1563 union {
1564 cmd_a64_entry_t cmd;
1565 sts_entry_t rsp;
1566 } p;
1567 uint8_t inq[INQ_DATA_SIZE];
1568} inq_cmd_rsp_t;
1569
1570/*
1571 * Report LUN command structure.
1572 */
1573#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1574
1575typedef struct {
1576 uint32_t len;
1577 uint32_t rsrv;
1578} rpt_hdr_t;
1579
1580typedef struct {
1581 struct {
1582 uint8_t b : 6;
1583 uint8_t address_method : 2;
1584 } msb;
1585 uint8_t lsb;
1586 uint8_t unused[6];
1587} rpt_lun_t;
1588
1589typedef struct {
1590 rpt_hdr_t hdr;
1591 rpt_lun_t lst[MAX_LUNS];
1592} rpt_lun_lst_t;
1593
1594/*
1595 * Report Lun mailbox IOCB packet definition.
1596 */
1597typedef struct {
1598 union {
1599 cmd_a64_entry_t cmd;
1600 sts_entry_t rsp;
1601 } p;
1602 rpt_lun_lst_t list;
1603} rpt_lun_cmd_rsp_t;
1604
1605/*
1606 * SCSI Target Queue structure
1607 */
1608typedef struct os_tgt {
1609 struct os_lun *olun[MAX_LUNS]; /* LUN context pointer. */
1610 struct fc_port *fcport;
1611 unsigned long flags;
1612 uint8_t port_down_retry_count;
1613 uint32_t down_timer;
1614 struct scsi_qla_host *ha;
1615
1616 /* Persistent binding information */
1617 port_id_t d_id;
1618 uint8_t node_name[WWN_SIZE];
1619 uint8_t port_name[WWN_SIZE];
1620} os_tgt_t;
1621
1622/*
1623 * SCSI Target Queue flags
1624 */
1625#define TQF_ONLINE 0 /* Device online to OS. */
1626#define TQF_SUSPENDED 1
1627#define TQF_RETRY_CMDS 2
1628
1629/*
1630 * SCSI LUN Queue structure
1631 */
1632typedef struct os_lun {
1633 struct fc_lun *fclun; /* FC LUN context pointer. */
1634 spinlock_t q_lock; /* Lun Lock */
1635
1636 unsigned long q_flag;
1637#define LUN_MPIO_RESET_CNTS 1 /* Lun */
1638#define LUN_MPIO_BUSY 2 /* Lun is changing paths */
1639#define LUN_EXEC_DELAYED 7 /* Lun execution is delayed */
1640
1641 u_long q_timeout; /* total command timeouts */
1642 atomic_t q_timer; /* suspend timer */
1643 uint32_t q_count; /* current count */
1644 uint32_t q_max; /* maxmum count lun can be suspended */
1645 uint8_t q_state; /* lun State */
1646#define LUN_STATE_READY 1 /* lun is ready for i/o */
1647#define LUN_STATE_RUN 2 /* lun has a timer running */
1648#define LUN_STATE_WAIT 3 /* lun is suspended */
1649#define LUN_STATE_TIMEOUT 4 /* lun has timed out */
1650
1651 u_long io_cnt; /* total xfer count since boot */
1652 u_long out_cnt; /* total outstanding IO count */
1653 u_long w_cnt; /* total writes */
1654 u_long r_cnt; /* total reads */
1655 u_long avg_time; /* */
1656} os_lun_t;
1657
1658
1659/* LUN BitMask structure definition, array of 32bit words,
1660 * 1 bit per lun. When bit == 1, the lun is masked.
1661 * Most significant bit of mask[0] is lun 0, bit 24 is lun 7.
1662 */
1663typedef struct lun_bit_mask {
1664 /* Must allocate at least enough bits to accomodate all LUNs */
1665#if ((MAX_FIBRE_LUNS & 0x7) == 0)
1666 uint8_t mask[MAX_FIBRE_LUNS >> 3];
1667#else
1668 uint8_t mask[(MAX_FIBRE_LUNS + 8) >> 3];
1669#endif
1670} lun_bit_mask_t;
1671
1672/*
1673 * Fibre channel port type.
1674 */
1675 typedef enum {
1676 FCT_UNKNOWN,
1677 FCT_RSCN,
1678 FCT_SWITCH,
1679 FCT_BROADCAST,
1680 FCT_INITIATOR,
1681 FCT_TARGET
1682} fc_port_type_t;
1683
1684/*
1685 * Fibre channel port structure.
1686 */
1687typedef struct fc_port {
1688 struct list_head list;
1689 struct list_head fcluns;
1690
1691 struct scsi_qla_host *ha;
1692 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1693
1694 uint8_t node_name[WWN_SIZE];
1695 uint8_t port_name[WWN_SIZE];
1696 port_id_t d_id;
1697 uint16_t loop_id;
1698 uint16_t old_loop_id;
1699
1700 fc_port_type_t port_type;
1701
1702 atomic_t state;
1703 uint32_t flags;
1704
1705 os_tgt_t *tgt_queue;
1706 uint16_t os_target_id;
1707
1708 uint16_t iodesc_idx_sent;
1709
1710 int port_login_retry_count;
1711 int login_retry;
1712 atomic_t port_down_timer;
1713
1714 uint8_t device_type;
1715 uint8_t unused;
1716
1717 uint8_t mp_byte; /* multi-path byte (not used) */
1718 uint8_t cur_path; /* current path id */
1719
1720 lun_bit_mask_t lun_mask;
1721} fc_port_t;
1722
1723/*
1724 * Fibre channel port/lun states.
1725 */
1726#define FCS_UNCONFIGURED 1
1727#define FCS_DEVICE_DEAD 2
1728#define FCS_DEVICE_LOST 3
1729#define FCS_ONLINE 4
1730#define FCS_NOT_SUPPORTED 5
1731#define FCS_FAILOVER 6
1732#define FCS_FAILOVER_FAILED 7
1733
1734/*
1735 * FC port flags.
1736 */
1737#define FCF_FABRIC_DEVICE BIT_0
1738#define FCF_LOGIN_NEEDED BIT_1
1739#define FCF_FO_MASKED BIT_2
1740#define FCF_FAILOVER_NEEDED BIT_3
1741#define FCF_RESET_NEEDED BIT_4
1742#define FCF_PERSISTENT_BOUND BIT_5
1743#define FCF_TAPE_PRESENT BIT_6
1744#define FCF_FARP_DONE BIT_7
1745#define FCF_FARP_FAILED BIT_8
1746#define FCF_FARP_REPLY_NEEDED BIT_9
1747#define FCF_AUTH_REQ BIT_10
1748#define FCF_SEND_AUTH_REQ BIT_11
1749#define FCF_RECEIVE_AUTH_REQ BIT_12
1750#define FCF_AUTH_SUCCESS BIT_13
1751#define FCF_RLC_SUPPORT BIT_14
1752#define FCF_CONFIG BIT_15 /* Needed? */
1753#define FCF_RESCAN_NEEDED BIT_16
1754#define FCF_XP_DEVICE BIT_17
1755#define FCF_MSA_DEVICE BIT_18
1756#define FCF_EVA_DEVICE BIT_19
1757#define FCF_MSA_PORT_ACTIVE BIT_20
1758#define FCF_FAILBACK_DISABLE BIT_21
1759#define FCF_FAILOVER_DISABLE BIT_22
1760#define FCF_DSXXX_DEVICE BIT_23
1761#define FCF_AA_EVA_DEVICE BIT_24
1762
1763/* No loop ID flag. */
1764#define FC_NO_LOOP_ID 0x1000
1765
1766/*
1767 * Fibre channel LUN structure.
1768 */
1769typedef struct fc_lun {
1770 struct list_head list;
1771
1772 fc_port_t *fcport;
1773 fc_port_t *o_fcport;
1774 uint16_t lun;
1775 atomic_t state;
1776 uint8_t device_type;
1777
1778 uint8_t max_path_retries;
1779 uint32_t flags;
1780} fc_lun_t;
1781
1782#define FLF_VISIBLE_LUN BIT_0
1783#define FLF_ACTIVE_LUN BIT_1
1784
1785/*
1786 * FC-CT interface
1787 *
1788 * NOTE: All structures are big-endian in form.
1789 */
1790
1791#define CT_REJECT_RESPONSE 0x8001
1792#define CT_ACCEPT_RESPONSE 0x8002
1793
1794#define NS_N_PORT_TYPE 0x01
1795#define NS_NL_PORT_TYPE 0x02
1796#define NS_NX_PORT_TYPE 0x7F
1797
1798#define GA_NXT_CMD 0x100
1799#define GA_NXT_REQ_SIZE (16 + 4)
1800#define GA_NXT_RSP_SIZE (16 + 620)
1801
1802#define GID_PT_CMD 0x1A1
1803#define GID_PT_REQ_SIZE (16 + 4)
1804#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1805
1806#define GPN_ID_CMD 0x112
1807#define GPN_ID_REQ_SIZE (16 + 4)
1808#define GPN_ID_RSP_SIZE (16 + 8)
1809
1810#define GNN_ID_CMD 0x113
1811#define GNN_ID_REQ_SIZE (16 + 4)
1812#define GNN_ID_RSP_SIZE (16 + 8)
1813
1814#define GFT_ID_CMD 0x117
1815#define GFT_ID_REQ_SIZE (16 + 4)
1816#define GFT_ID_RSP_SIZE (16 + 32)
1817
1818#define RFT_ID_CMD 0x217
1819#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1820#define RFT_ID_RSP_SIZE 16
1821
1822#define RFF_ID_CMD 0x21F
1823#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1824#define RFF_ID_RSP_SIZE 16
1825
1826#define RNN_ID_CMD 0x213
1827#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1828#define RNN_ID_RSP_SIZE 16
1829
1830#define RSNN_NN_CMD 0x239
1831#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1832#define RSNN_NN_RSP_SIZE 16
1833
1834/* CT command header -- request/response common fields */
1835struct ct_cmd_hdr {
1836 uint8_t revision;
1837 uint8_t in_id[3];
1838 uint8_t gs_type;
1839 uint8_t gs_subtype;
1840 uint8_t options;
1841 uint8_t reserved;
1842};
1843
1844/* CT command request */
1845struct ct_sns_req {
1846 struct ct_cmd_hdr header;
1847 uint16_t command;
1848 uint16_t max_rsp_size;
1849 uint8_t fragment_id;
1850 uint8_t reserved[3];
1851
1852 union {
1853 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1854 struct {
1855 uint8_t reserved;
1856 uint8_t port_id[3];
1857 } port_id;
1858
1859 struct {
1860 uint8_t port_type;
1861 uint8_t domain;
1862 uint8_t area;
1863 uint8_t reserved;
1864 } gid_pt;
1865
1866 struct {
1867 uint8_t reserved;
1868 uint8_t port_id[3];
1869 uint8_t fc4_types[32];
1870 } rft_id;
1871
1872 struct {
1873 uint8_t reserved;
1874 uint8_t port_id[3];
1875 uint16_t reserved2;
1876 uint8_t fc4_feature;
1877 uint8_t fc4_type;
1878 } rff_id;
1879
1880 struct {
1881 uint8_t reserved;
1882 uint8_t port_id[3];
1883 uint8_t node_name[8];
1884 } rnn_id;
1885
1886 struct {
1887 uint8_t node_name[8];
1888 uint8_t name_len;
1889 uint8_t sym_node_name[255];
1890 } rsnn_nn;
1891 } req;
1892};
1893
1894/* CT command response header */
1895struct ct_rsp_hdr {
1896 struct ct_cmd_hdr header;
1897 uint16_t response;
1898 uint16_t residual;
1899 uint8_t fragment_id;
1900 uint8_t reason_code;
1901 uint8_t explanation_code;
1902 uint8_t vendor_unique;
1903};
1904
1905struct ct_sns_gid_pt_data {
1906 uint8_t control_byte;
1907 uint8_t port_id[3];
1908};
1909
1910struct ct_sns_rsp {
1911 struct ct_rsp_hdr header;
1912
1913 union {
1914 struct {
1915 uint8_t port_type;
1916 uint8_t port_id[3];
1917 uint8_t port_name[8];
1918 uint8_t sym_port_name_len;
1919 uint8_t sym_port_name[255];
1920 uint8_t node_name[8];
1921 uint8_t sym_node_name_len;
1922 uint8_t sym_node_name[255];
1923 uint8_t init_proc_assoc[8];
1924 uint8_t node_ip_addr[16];
1925 uint8_t class_of_service[4];
1926 uint8_t fc4_types[32];
1927 uint8_t ip_address[16];
1928 uint8_t fabric_port_name[8];
1929 uint8_t reserved;
1930 uint8_t hard_address[3];
1931 } ga_nxt;
1932
1933 struct {
1934 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1935 } gid_pt;
1936
1937 struct {
1938 uint8_t port_name[8];
1939 } gpn_id;
1940
1941 struct {
1942 uint8_t node_name[8];
1943 } gnn_id;
1944
1945 struct {
1946 uint8_t fc4_types[32];
1947 } gft_id;
1948 } rsp;
1949};
1950
1951struct ct_sns_pkt {
1952 union {
1953 struct ct_sns_req req;
1954 struct ct_sns_rsp rsp;
1955 } p;
1956};
1957
1958/*
1959 * SNS command structures -- for 2200 compatability.
1960 */
1961#define RFT_ID_SNS_SCMD_LEN 22
1962#define RFT_ID_SNS_CMD_SIZE 60
1963#define RFT_ID_SNS_DATA_SIZE 16
1964
1965#define RNN_ID_SNS_SCMD_LEN 10
1966#define RNN_ID_SNS_CMD_SIZE 36
1967#define RNN_ID_SNS_DATA_SIZE 16
1968
1969#define GA_NXT_SNS_SCMD_LEN 6
1970#define GA_NXT_SNS_CMD_SIZE 28
1971#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1972
1973#define GID_PT_SNS_SCMD_LEN 6
1974#define GID_PT_SNS_CMD_SIZE 28
1975#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1976
1977#define GPN_ID_SNS_SCMD_LEN 6
1978#define GPN_ID_SNS_CMD_SIZE 28
1979#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1980
1981#define GNN_ID_SNS_SCMD_LEN 6
1982#define GNN_ID_SNS_CMD_SIZE 28
1983#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1984
1985struct sns_cmd_pkt {
1986 union {
1987 struct {
1988 uint16_t buffer_length;
1989 uint16_t reserved_1;
1990 uint32_t buffer_address[2];
1991 uint16_t subcommand_length;
1992 uint16_t reserved_2;
1993 uint16_t subcommand;
1994 uint16_t size;
1995 uint32_t reserved_3;
1996 uint8_t param[36];
1997 } cmd;
1998
1999 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2000 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2001 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2002 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2003 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2004 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2005 } p;
2006};
2007
2008/* IO descriptors */
2009#define MAX_IO_DESCRIPTORS 32
2010
2011#define ABORT_IOCB_CB 0
2012#define ADISC_PORT_IOCB_CB 1
2013#define LOGOUT_PORT_IOCB_CB 2
2014#define LOGIN_PORT_IOCB_CB 3
2015#define LAST_IOCB_CB 4
2016
2017#define IODESC_INVALID_INDEX 0xFFFF
2018#define IODESC_ADISC_NEEDED 0xFFFE
2019#define IODESC_LOGIN_NEEDED 0xFFFD
2020
2021struct io_descriptor {
2022 uint16_t used:1;
2023 uint16_t idx:11;
2024 uint16_t cb_idx:4;
2025
2026 struct timer_list timer;
2027
2028 struct scsi_qla_host *ha;
2029
2030 port_id_t d_id;
2031 fc_port_t *remote_fcport;
2032
2033 uint32_t signature;
2034};
2035
2036struct qla_fw_info {
2037 unsigned short addressing; /* addressing method used to load fw */
2038#define FW_INFO_ADDR_NORMAL 0
2039#define FW_INFO_ADDR_EXTENDED 1
2040#define FW_INFO_ADDR_NOMORE 0xffff
2041 unsigned short *fwcode; /* pointer to FW array */
2042 unsigned short *fwlen; /* number of words in array */
2043 unsigned short *fwstart; /* start address for F/W */
2044 unsigned long *lfwstart; /* start address (long) for F/W */
2045};
2046
2047struct qla_board_info {
2048 char *drv_name;
2049
2050 char isp_name[8];
2051 struct qla_fw_info *fw_info;
2052};
2053
2054/* Return data from MBC_GET_ID_LIST call. */
2055struct gid_list_info {
2056 uint8_t al_pa;
2057 uint8_t area;
2058 uint8_t domain;
2059 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2060 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2061};
2062#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2063
2064/*
2065 * Linux Host Adapter structure
2066 */
2067typedef struct scsi_qla_host {
2068 struct list_head list;
2069
2070 /* Commonly used flags and state information. */
2071 struct Scsi_Host *host;
2072 struct pci_dev *pdev;
2073
2074 unsigned long host_no;
2075 unsigned long instance;
2076
2077 volatile struct {
2078 uint32_t init_done :1;
2079 uint32_t online :1;
2080 uint32_t mbox_int :1;
2081 uint32_t mbox_busy :1;
2082 uint32_t rscn_queue_overflow :1;
2083 uint32_t reset_active :1;
2084
2085 uint32_t management_server_logged_in :1;
2086 uint32_t process_response_queue :1;
2087
2088 uint32_t disable_risc_code_load :1;
2089 uint32_t enable_64bit_addressing :1;
2090 uint32_t enable_lip_reset :1;
2091 uint32_t enable_lip_full_login :1;
2092 uint32_t enable_target_reset :1;
2093 uint32_t enable_led_scheme :1;
2094 } flags;
2095
2096 atomic_t loop_state;
2097#define LOOP_TIMEOUT 1
2098#define LOOP_DOWN 2
2099#define LOOP_UP 3
2100#define LOOP_UPDATE 4
2101#define LOOP_READY 5
2102#define LOOP_DEAD 6
2103
2104 unsigned long dpc_flags;
2105#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2106#define RESET_ACTIVE 1
2107#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2108#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2109#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2110#define LOOP_RESYNC_ACTIVE 5
2111#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2112#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2113#define MAILBOX_RETRY 8
2114#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2115#define FAILOVER_EVENT_NEEDED 10
2116#define FAILOVER_EVENT 11
2117#define FAILOVER_NEEDED 12
2118#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2119#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2120#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2121#define ABORT_QUEUES_NEEDED 16
2122#define RELOGIN_NEEDED 17
2123#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2124#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2125#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2126#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2127#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2128#define IOCTL_ERROR_RECOVERY 23
2129#define LOOP_RESET_NEEDED 24
2130
2131 uint32_t device_flags;
2132#define DFLG_LOCAL_DEVICES BIT_0
2133#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2134#define DFLG_FABRIC_DEVICES BIT_2
2135#define SWITCH_FOUND BIT_3
2136#define DFLG_NO_CABLE BIT_4
2137
2138 /* SRB cache. */
2139#define SRB_MIN_REQ 128
2140 mempool_t *srb_mempool;
2141
2142 /* This spinlock is used to protect "io transactions", you must
2143 * aquire it before doing any IO to the card, eg with RD_REG*() and
2144 * WRT_REG*() for the duration of your entire commandtransaction.
2145 *
2146 * This spinlock is of lower priority than the io request lock.
2147 */
2148
2149 spinlock_t hardware_lock ____cacheline_aligned;
2150
2151 device_reg_t __iomem *iobase; /* Base I/O address */
2152 unsigned long pio_address;
2153 unsigned long pio_length;
2154#define MIN_IOBASE_LEN 0x100
2155
2156 /* ISP ring lock, rings, and indexes */
2157 dma_addr_t request_dma; /* Physical address. */
2158 request_t *request_ring; /* Base virtual address */
2159 request_t *request_ring_ptr; /* Current address. */
2160 uint16_t req_ring_index; /* Current index. */
2161 uint16_t req_q_cnt; /* Number of available entries. */
2162 uint16_t request_q_length;
2163
2164 dma_addr_t response_dma; /* Physical address. */
2165 response_t *response_ring; /* Base virtual address */
2166 response_t *response_ring_ptr; /* Current address. */
2167 uint16_t rsp_ring_index; /* Current index. */
2168 uint16_t response_q_length;
2169
2170 uint16_t (*calc_request_entries)(uint16_t);
2171 void (*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
2172
2173 /* Outstandings ISP commands. */
2174 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2175 uint32_t current_outstanding_cmd;
2176 srb_t *status_srb; /* Status continuation entry. */
2177
2178 /*
2179 * Need to hold the list_lock with irq's disabled in order to access
2180 * the following list.
2181 *
2182 * This list_lock is of lower priority than the host_lock.
2183 */
2184 spinlock_t list_lock ____cacheline_aligned;
2185 /* lock to guard lists which
2186 * hold srb_t's */
2187 struct list_head retry_queue; /* watchdog queue */
2188 struct list_head done_queue; /* job on done queue */
2189 struct list_head failover_queue; /* failover list link. */
2190 struct list_head scsi_retry_queue; /* SCSI retry queue */
2191 struct list_head pending_queue; /* SCSI command pending queue */
2192
2193 unsigned long done_q_cnt;
2194 unsigned long pending_in_q;
2195 uint32_t retry_q_cnt;
2196 uint32_t scsi_retry_q_cnt;
2197 uint32_t failover_cnt;
2198
2199 unsigned long last_irq_cpu; /* cpu where we got our last irq */
2200
2201 uint16_t revision;
2202 uint8_t ports;
2203 u_long actthreads;
2204 u_long ipreq_cnt;
2205 u_long qthreads;
2206
2207 uint32_t total_isr_cnt; /* Interrupt count */
2208 uint32_t total_isp_aborts; /* controller err cnt */
2209 uint32_t total_lip_cnt; /* LIP cnt */
2210 uint32_t total_dev_errs; /* device error cnt */
2211 uint32_t total_ios; /* IO cnt */
2212 uint64_t total_bytes; /* xfr byte cnt */
2213 uint32_t total_mbx_timeout; /* mailbox timeout cnt */
2214 uint32_t total_loop_resync; /* loop resyn cnt */
2215 uint32_t dropped_frame_error_cnt;
2216
2217 /* ISP configuration data. */
2218 uint16_t loop_id; /* Host adapter loop id */
2219 uint16_t fb_rev;
2220
2221 port_id_t d_id; /* Host adapter port id */
2222 uint16_t max_public_loop_ids;
2223 uint16_t min_external_loopid; /* First external loop Id */
2224
2225 uint16_t link_data_rate; /* F/W operating speed */
2226
2227 uint8_t current_topology;
2228 uint8_t prev_topology;
2229#define ISP_CFG_NL 1
2230#define ISP_CFG_N 2
2231#define ISP_CFG_FL 4
2232#define ISP_CFG_F 8
2233
2234 uint8_t operating_mode; /* F/W operating mode */
2235#define LOOP 0
2236#define P2P 1
2237#define LOOP_P2P 2
2238#define P2P_LOOP 3
2239
2240 uint8_t marker_needed;
2241 uint8_t sns_retry_cnt;
2242 uint8_t mem_err;
2243
2244 uint8_t interrupts_on;
2245
2246 /* HBA serial number */
2247 uint8_t serial0;
2248 uint8_t serial1;
2249 uint8_t serial2;
2250
2251 /* NVRAM configuration data */
2252 uint16_t nvram_base;
2253
2254 uint16_t loop_reset_delay;
2255 uint16_t minimum_timeout;
2256 uint8_t retry_count;
2257 uint8_t login_timeout;
2258 uint16_t r_a_tov;
2259 int port_down_retry_count;
2260 uint8_t loop_down_timeout;
2261 uint8_t mbx_count;
2262 uint16_t max_probe_luns;
2263 uint16_t max_luns;
2264 uint16_t max_targets;
2265 uint16_t last_loop_id;
2266
2267 uint32_t login_retry_count;
2268
2269 /* Fibre Channel Device List. */
2270 struct list_head fcports;
2271 struct list_head rscn_fcports;
2272
2273 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2274 uint16_t iodesc_signature;
2275
2276 /* OS target queue pointers. */
2277 os_tgt_t *otgt[MAX_FIBRE_DEVICES];
2278
2279 /* RSCN queue. */
2280 uint32_t rscn_queue[MAX_RSCN_COUNT];
2281 uint8_t rscn_in_ptr;
2282 uint8_t rscn_out_ptr;
2283
2284 /* SNS command interfaces. */
2285 ms_iocb_entry_t *ms_iocb;
2286 dma_addr_t ms_iocb_dma;
2287 struct ct_sns_pkt *ct_sns;
2288 dma_addr_t ct_sns_dma;
2289 /* SNS command interfaces for 2200. */
2290 struct sns_cmd_pkt *sns_cmd;
2291 dma_addr_t sns_cmd_dma;
2292
2293 pid_t dpc_pid;
2294 int dpc_should_die;
2295 struct completion dpc_inited;
2296 struct completion dpc_exited;
2297 struct semaphore *dpc_wait;
2298 uint8_t dpc_active; /* DPC routine is active */
2299
2300 /* Timeout timers. */
2301 uint8_t queue_restart_timer;
2302 uint8_t loop_down_abort_time; /* port down timer */
2303 atomic_t loop_down_timer; /* loop down timer */
2304 uint8_t link_down_timeout; /* link down timeout */
2305
2306 uint32_t timer_active;
2307 struct timer_list timer;
2308
2309 dma_addr_t gid_list_dma;
2310 struct gid_list_info *gid_list;
2311
2312 dma_addr_t rlc_rsp_dma;
2313 rpt_lun_cmd_rsp_t *rlc_rsp;
2314
2315 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2316#define DMA_POOL_SIZE 256
2317 struct dma_pool *s_dma_pool;
2318
2319 dma_addr_t init_cb_dma;
2320 init_cb_t *init_cb;
2321
2322 dma_addr_t iodesc_pd_dma;
2323 port_database_t *iodesc_pd;
2324
2325 /* These are used by mailbox operations. */
2326 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2327
2328 mbx_cmd_t *mcp;
2329 unsigned long mbx_cmd_flags;
2330#define MBX_INTERRUPT 1
2331#define MBX_INTR_WAIT 2
2332#define MBX_UPDATE_FLASH_ACTIVE 3
2333
2334 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2335
2336 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2337 struct semaphore mbx_intr_sem; /* Used for completion notification */
2338
2339 uint32_t mbx_flags;
2340#define MBX_IN_PROGRESS BIT_0
2341#define MBX_BUSY BIT_1 /* Got the Access */
2342#define MBX_SLEEPING_ON_SEM BIT_2
2343#define MBX_POLLING_FOR_COMP BIT_3
2344#define MBX_COMPLETED BIT_4
2345#define MBX_TIMEDOUT BIT_5
2346#define MBX_ACCESS_TIMEDOUT BIT_6
2347
2348 mbx_cmd_t mc;
2349
2350 uint8_t *cmdline;
2351
2352 uint32_t failover_type;
2353 uint32_t failback_delay;
2354 unsigned long cfg_flags;
2355#define CFG_ACTIVE 0 /* CFG during a failover, event update, or ioctl */
2356#define CFG_FAILOVER 1 /* CFG during path change */
2357
2358 uint32_t binding_type;
2359#define BIND_BY_PORT_NAME 0
2360#define BIND_BY_PORT_ID 1
2361
2362 /* Basic firmware related information. */
2363 struct qla_board_info *brd_info;
2364 uint16_t fw_major_version;
2365 uint16_t fw_minor_version;
2366 uint16_t fw_subminor_version;
2367 uint16_t fw_attributes;
2368 uint32_t fw_memory_size;
2369 uint32_t fw_transfer_size;
2370
2371 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2372 uint8_t fw_seriallink_options[4];
2373
2374 /* Firmware dump information. */
2375 void *fw_dump;
2376 int fw_dump_order;
2377 int fw_dump_reading;
2378 char *fw_dump_buffer;
2379 int fw_dump_buffer_len;
2380
2381 uint8_t host_str[16];
2382 uint16_t pci_attr;
2383
2384 uint16_t product_id[4];
2385
2386 uint8_t model_number[16+1];
2387#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2388 char *model_desc;
2389
2390 uint8_t node_name[WWN_SIZE];
2391 uint8_t nvram_version;
2392 uint32_t isp_abort_cnt;
2393
2394 /* Adapter I/O statistics for failover */
2395 uint64_t IosRequested;
2396 uint64_t BytesRequested;
2397 uint64_t IosExecuted;
2398 uint64_t BytesExecuted;
2399
2400 /* Needed for BEACON */
2401 uint16_t beacon_blink_led;
2402 uint16_t beacon_green_on;
2403} scsi_qla_host_t;
2404
2405
2406/*
2407 * Macros to help code, maintain, etc.
2408 */
2409#define LOOP_TRANSITION(ha) \
2410 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2411 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2412
2413#define LOOP_NOT_READY(ha) \
2414 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2415 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2416 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2417 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2418 atomic_read(&ha->loop_state) == LOOP_DOWN)
2419
2420#define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2421
2422#define TGT_Q(ha, t) (ha->otgt[t])
2423#define LUN_Q(ha, t, l) (TGT_Q(ha, t)->olun[l])
2424#define GET_LU_Q(ha, t, l) ((TGT_Q(ha,t) != NULL)? TGT_Q(ha, t)->olun[l] : NULL)
2425
2426#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2427
2428#define qla_printk(level, ha, format, arg...) \
2429 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2430
2431/*
2432 * qla2x00 local function return status codes
2433 */
2434#define MBS_MASK 0x3fff
2435
2436#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2437#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2438#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2439#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2440#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2441#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2442#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2443#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2444#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2445#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2446
2447#define QLA_FUNCTION_TIMEOUT 0x100
2448#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2449#define QLA_FUNCTION_FAILED 0x102
2450#define QLA_MEMORY_ALLOC_FAILED 0x103
2451#define QLA_LOCK_TIMEOUT 0x104
2452#define QLA_ABORTED 0x105
2453#define QLA_SUSPENDED 0x106
2454#define QLA_BUSY 0x107
2455#define QLA_RSCNS_HANDLED 0x108
2456
2457/*
2458* Stat info for all adpaters
2459*/
2460struct _qla2x00stats {
2461 unsigned long mboxtout; /* mailbox timeouts */
2462 unsigned long mboxerr; /* mailbox errors */
2463 unsigned long ispAbort; /* ISP aborts */
2464 unsigned long debugNo;
2465 unsigned long loop_resync;
2466 unsigned long outarray_full;
2467 unsigned long retry_q_cnt;
2468};
2469
2470#define NVRAM_DELAY() udelay(10)
2471
2472#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2473
2474/*
2475 * Flash support definitions
2476 */
2477#define FLASH_IMAGE_SIZE 131072
2478
2479#include "qla_gbl.h"
2480#include "qla_dbg.h"
2481#include "qla_inline.h"
2482#include "qla_listops.h"
2483
2484/*
2485* String arrays
2486*/
2487#define LINESIZE 256
2488#define MAXARGS 26
2489
2490#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2491#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2492#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2493#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2494#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2495#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2496
2497#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 10:14:13 -0500