diff options
author | Andrew Vasquez <andrew.vasquez@qlogic.com> | 2007-09-20 17:07:38 -0400 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.localdomain> | 2007-10-12 14:49:54 -0400 |
commit | c3b058afaea11273835f59694f8645a89915be9c (patch) | |
tree | b89494dd44d9aa4b088848aff9034c89cb4056ed /drivers/scsi/qla2xxx/qla_dbg.c | |
parent | 05236a050f8e3a20962bad98ad8ceb94bbdb748c (diff) |
[SCSI] qla2xxx: Correct staging of RISC while attempting to pause.
There's no need to reset the RISC prior to pausing.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_dbg.c')
-rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index b52fa8977d91..2defe0c21df4 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c | |||
@@ -172,19 +172,16 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |||
172 | int rval = QLA_SUCCESS; | 172 | int rval = QLA_SUCCESS; |
173 | uint32_t cnt; | 173 | uint32_t cnt; |
174 | 174 | ||
175 | if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { | 175 | if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) |
176 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | | 176 | return rval; |
177 | HCCRX_CLR_HOST_INT); | 177 | |
178 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | 178 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
179 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); | 179 | for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && |
180 | for (cnt = 30000; | 180 | rval == QLA_SUCCESS; cnt--) { |
181 | (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && | 181 | if (cnt) |
182 | rval == QLA_SUCCESS; cnt--) { | 182 | udelay(100); |
183 | if (cnt) | 183 | else |
184 | udelay(100); | 184 | rval = QLA_FUNCTION_TIMEOUT; |
185 | else | ||
186 | rval = QLA_FUNCTION_TIMEOUT; | ||
187 | } | ||
188 | } | 185 | } |
189 | 186 | ||
190 | return rval; | 187 | return rval; |