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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2007-07-19 23:37:34 -0400
committerJames Bottomley <jejb@mulgrave.localdomain>2007-07-20 10:25:29 -0400
commitc3a2f0dfe1cecac76950f340f540c1a887dd2500 (patch)
treebe6cce05e0fba81e9bf91351aebab23918ae5115 /drivers/scsi/qla2xxx/qla_dbg.c
parentaf6177d88d76834b4d05499482d471d64559a6af (diff)
[SCSI] qla2xxx: Add ISP25XX support.
Large code-reuse from ISP24xx, consolidate RISC memory extraction routines during firmware-dump. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_dbg.c')
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c1114
1 files changed, 910 insertions, 204 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 996c47a63074..563d18f4ff50 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -37,6 +37,121 @@ qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
37 return ptr + (ha->response_q_length * sizeof(response_t)); 37 return ptr + (ha->response_q_length * sizeof(response_t));
38} 38}
39 39
40static int
41qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
42 uint32_t cram_size, uint32_t *ext_mem, void **nxt)
43{
44 int rval;
45 uint32_t cnt, stat, timer, risc_address, ext_mem_cnt;
46 uint16_t mb[4];
47 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
48
49 rval = QLA_SUCCESS;
50 risc_address = ext_mem_cnt = 0;
51 memset(mb, 0, sizeof(mb));
52
53 /* Code RAM. */
54 risc_address = 0x20000;
55 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
56 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
57
58 for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS;
59 cnt++, risc_address++) {
60 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
61 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
62 RD_REG_WORD(&reg->mailbox8);
63 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
64
65 for (timer = 6000000; timer; timer--) {
66 /* Check for pending interrupts. */
67 stat = RD_REG_DWORD(&reg->host_status);
68 if (stat & HSRX_RISC_INT) {
69 stat &= 0xff;
70
71 if (stat == 0x1 || stat == 0x2 ||
72 stat == 0x10 || stat == 0x11) {
73 set_bit(MBX_INTERRUPT,
74 &ha->mbx_cmd_flags);
75
76 mb[0] = RD_REG_WORD(&reg->mailbox0);
77 mb[2] = RD_REG_WORD(&reg->mailbox2);
78 mb[3] = RD_REG_WORD(&reg->mailbox3);
79
80 WRT_REG_DWORD(&reg->hccr,
81 HCCRX_CLR_RISC_INT);
82 RD_REG_DWORD(&reg->hccr);
83 break;
84 }
85
86 /* Clear this intr; it wasn't a mailbox intr */
87 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
88 RD_REG_DWORD(&reg->hccr);
89 }
90 udelay(5);
91 }
92
93 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
94 rval = mb[0] & MBS_MASK;
95 code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
96 } else {
97 rval = QLA_FUNCTION_FAILED;
98 }
99 }
100
101 if (rval == QLA_SUCCESS) {
102 /* External Memory. */
103 risc_address = 0x100000;
104 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
105 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
106 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
107 }
108 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
109 cnt++, risc_address++) {
110 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
111 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
112 RD_REG_WORD(&reg->mailbox8);
113 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
114
115 for (timer = 6000000; timer; timer--) {
116 /* Check for pending interrupts. */
117 stat = RD_REG_DWORD(&reg->host_status);
118 if (stat & HSRX_RISC_INT) {
119 stat &= 0xff;
120
121 if (stat == 0x1 || stat == 0x2 ||
122 stat == 0x10 || stat == 0x11) {
123 set_bit(MBX_INTERRUPT,
124 &ha->mbx_cmd_flags);
125
126 mb[0] = RD_REG_WORD(&reg->mailbox0);
127 mb[2] = RD_REG_WORD(&reg->mailbox2);
128 mb[3] = RD_REG_WORD(&reg->mailbox3);
129
130 WRT_REG_DWORD(&reg->hccr,
131 HCCRX_CLR_RISC_INT);
132 RD_REG_DWORD(&reg->hccr);
133 break;
134 }
135
136 /* Clear this intr; it wasn't a mailbox intr */
137 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
138 RD_REG_DWORD(&reg->hccr);
139 }
140 udelay(5);
141 }
142
143 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
144 rval = mb[0] & MBS_MASK;
145 ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
146 } else {
147 rval = QLA_FUNCTION_FAILED;
148 }
149 }
150
151 *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL;
152 return rval;
153}
154
40/** 155/**
41 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 156 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
42 * @ha: HA context 157 * @ha: HA context
@@ -633,11 +748,10 @@ void
633qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 748qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
634{ 749{
635 int rval; 750 int rval;
636 uint32_t cnt, timer; 751 uint32_t cnt;
637 uint32_t risc_address; 752 uint32_t risc_address;
638 uint16_t mb[4], wd; 753 uint16_t mb0, wd;
639 754
640 uint32_t stat;
641 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 755 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
642 uint32_t __iomem *dmp_reg; 756 uint32_t __iomem *dmp_reg;
643 uint32_t *iter_reg; 757 uint32_t *iter_reg;
@@ -645,10 +759,9 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
645 unsigned long flags; 759 unsigned long flags;
646 struct qla24xx_fw_dump *fw; 760 struct qla24xx_fw_dump *fw;
647 uint32_t ext_mem_cnt; 761 uint32_t ext_mem_cnt;
648 void *eft; 762 void *nxt;
649 763
650 risc_address = ext_mem_cnt = 0; 764 risc_address = ext_mem_cnt = 0;
651 memset(mb, 0, sizeof(mb));
652 flags = 0; 765 flags = 0;
653 766
654 if (!hardware_locked) 767 if (!hardware_locked)
@@ -701,250 +814,236 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
701 /* Shadow registers. */ 814 /* Shadow registers. */
702 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 815 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
703 RD_REG_DWORD(&reg->iobase_addr); 816 RD_REG_DWORD(&reg->iobase_addr);
704 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 817 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
705 WRT_REG_DWORD(dmp_reg, 0xB0000000); 818 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
706 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 819
707 fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg)); 820 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
708 821 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
709 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 822
710 WRT_REG_DWORD(dmp_reg, 0xB0100000); 823 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
711 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 824 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
712 fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg)); 825
713 826 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
714 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 827 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
715 WRT_REG_DWORD(dmp_reg, 0xB0200000); 828
716 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 829 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
717 fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg)); 830 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
718 831
719 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 832 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
720 WRT_REG_DWORD(dmp_reg, 0xB0300000); 833 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
721 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 834
722 fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg)); 835 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
723 836 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
724 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
725 WRT_REG_DWORD(dmp_reg, 0xB0400000);
726 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
727 fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg));
728
729 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
730 WRT_REG_DWORD(dmp_reg, 0xB0500000);
731 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
732 fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg));
733
734 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
735 WRT_REG_DWORD(dmp_reg, 0xB0600000);
736 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
737 fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg));
738 837
739 /* Mailbox registers. */ 838 /* Mailbox registers. */
740 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 839 mbx_reg = &reg->mailbox0;
741 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 840 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
742 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 841 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
743 842
744 /* Transfer sequence registers. */ 843 /* Transfer sequence registers. */
745 iter_reg = fw->xseq_gp_reg; 844 iter_reg = fw->xseq_gp_reg;
746 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 845 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
747 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 846 dmp_reg = &reg->iobase_window;
748 for (cnt = 0; cnt < 16; cnt++) 847 for (cnt = 0; cnt < 16; cnt++)
749 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 848 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
750 849
751 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 850 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
752 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 851 dmp_reg = &reg->iobase_window;
753 for (cnt = 0; cnt < 16; cnt++) 852 for (cnt = 0; cnt < 16; cnt++)
754 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 853 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
755 854
756 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 855 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
757 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 856 dmp_reg = &reg->iobase_window;
758 for (cnt = 0; cnt < 16; cnt++) 857 for (cnt = 0; cnt < 16; cnt++)
759 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 858 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
760 859
761 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 860 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
762 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 861 dmp_reg = &reg->iobase_window;
763 for (cnt = 0; cnt < 16; cnt++) 862 for (cnt = 0; cnt < 16; cnt++)
764 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 863 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
765 864
766 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 865 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
767 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 866 dmp_reg = &reg->iobase_window;
768 for (cnt = 0; cnt < 16; cnt++) 867 for (cnt = 0; cnt < 16; cnt++)
769 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 868 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
770 869
771 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 870 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
772 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 871 dmp_reg = &reg->iobase_window;
773 for (cnt = 0; cnt < 16; cnt++) 872 for (cnt = 0; cnt < 16; cnt++)
774 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 873 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
775 874
776 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 875 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
777 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 876 dmp_reg = &reg->iobase_window;
778 for (cnt = 0; cnt < 16; cnt++) 877 for (cnt = 0; cnt < 16; cnt++)
779 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 878 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
780 879
781 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 880 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
782 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 881 dmp_reg = &reg->iobase_window;
783 for (cnt = 0; cnt < 16; cnt++) 882 for (cnt = 0; cnt < 16; cnt++)
784 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 883 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
785 884
786 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 885 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
787 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 886 dmp_reg = &reg->iobase_window;
788 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) 887 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
789 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 888 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
790 889
791 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 890 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
792 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 891 dmp_reg = &reg->iobase_window;
793 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 892 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
794 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 893 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
795 894
796 /* Receive sequence registers. */ 895 /* Receive sequence registers. */
797 iter_reg = fw->rseq_gp_reg; 896 iter_reg = fw->rseq_gp_reg;
798 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 897 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
799 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 898 dmp_reg = &reg->iobase_window;
800 for (cnt = 0; cnt < 16; cnt++) 899 for (cnt = 0; cnt < 16; cnt++)
801 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 900 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
802 901
803 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 902 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
804 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 903 dmp_reg = &reg->iobase_window;
805 for (cnt = 0; cnt < 16; cnt++) 904 for (cnt = 0; cnt < 16; cnt++)
806 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 905 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
807 906
808 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 907 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
809 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 908 dmp_reg = &reg->iobase_window;
810 for (cnt = 0; cnt < 16; cnt++) 909 for (cnt = 0; cnt < 16; cnt++)
811 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 910 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
812 911
813 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 912 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
814 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 913 dmp_reg = &reg->iobase_window;
815 for (cnt = 0; cnt < 16; cnt++) 914 for (cnt = 0; cnt < 16; cnt++)
816 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 915 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
817 916
818 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 917 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
819 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 918 dmp_reg = &reg->iobase_window;
820 for (cnt = 0; cnt < 16; cnt++) 919 for (cnt = 0; cnt < 16; cnt++)
821 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 920 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
822 921
823 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 922 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
824 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 923 dmp_reg = &reg->iobase_window;
825 for (cnt = 0; cnt < 16; cnt++) 924 for (cnt = 0; cnt < 16; cnt++)
826 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 925 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
827 926
828 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 927 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
829 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 928 dmp_reg = &reg->iobase_window;
830 for (cnt = 0; cnt < 16; cnt++) 929 for (cnt = 0; cnt < 16; cnt++)
831 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 930 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
832 931
833 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 932 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
834 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 933 dmp_reg = &reg->iobase_window;
835 for (cnt = 0; cnt < 16; cnt++) 934 for (cnt = 0; cnt < 16; cnt++)
836 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 935 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
837 936
838 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 937 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
839 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 938 dmp_reg = &reg->iobase_window;
840 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) 939 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
841 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 940 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
842 941
843 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 942 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
844 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 943 dmp_reg = &reg->iobase_window;
845 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 944 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
846 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 945 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
847 946
848 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 947 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
849 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 948 dmp_reg = &reg->iobase_window;
850 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 949 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
851 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 950 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
852 951
853 /* Command DMA registers. */ 952 /* Command DMA registers. */
854 WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 953 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
855 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 954 dmp_reg = &reg->iobase_window;
856 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 955 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
857 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 956 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
858 957
859 /* Queues. */ 958 /* Queues. */
860 iter_reg = fw->req0_dma_reg; 959 iter_reg = fw->req0_dma_reg;
861 WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 960 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
862 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 961 dmp_reg = &reg->iobase_window;
863 for (cnt = 0; cnt < 8; cnt++) 962 for (cnt = 0; cnt < 8; cnt++)
864 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 963 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
865 964
866 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 965 dmp_reg = &reg->iobase_q;
867 for (cnt = 0; cnt < 7; cnt++) 966 for (cnt = 0; cnt < 7; cnt++)
868 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 967 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
869 968
870 iter_reg = fw->resp0_dma_reg; 969 iter_reg = fw->resp0_dma_reg;
871 WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 970 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
872 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 971 dmp_reg = &reg->iobase_window;
873 for (cnt = 0; cnt < 8; cnt++) 972 for (cnt = 0; cnt < 8; cnt++)
874 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
875 974
876 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 975 dmp_reg = &reg->iobase_q;
877 for (cnt = 0; cnt < 7; cnt++) 976 for (cnt = 0; cnt < 7; cnt++)
878 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 977 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
879 978
880 iter_reg = fw->req1_dma_reg; 979 iter_reg = fw->req1_dma_reg;
881 WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 980 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
882 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 981 dmp_reg = &reg->iobase_window;
883 for (cnt = 0; cnt < 8; cnt++) 982 for (cnt = 0; cnt < 8; cnt++)
884 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 983 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
885 984
886 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 985 dmp_reg = &reg->iobase_q;
887 for (cnt = 0; cnt < 7; cnt++) 986 for (cnt = 0; cnt < 7; cnt++)
888 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 987 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
889 988
890 /* Transmit DMA registers. */ 989 /* Transmit DMA registers. */
891 iter_reg = fw->xmt0_dma_reg; 990 iter_reg = fw->xmt0_dma_reg;
892 WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 991 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
893 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 992 dmp_reg = &reg->iobase_window;
894 for (cnt = 0; cnt < 16; cnt++) 993 for (cnt = 0; cnt < 16; cnt++)
895 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 994 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
896 995
897 WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 996 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
898 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 997 dmp_reg = &reg->iobase_window;
899 for (cnt = 0; cnt < 16; cnt++) 998 for (cnt = 0; cnt < 16; cnt++)
900 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 999 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
901 1000
902 iter_reg = fw->xmt1_dma_reg; 1001 iter_reg = fw->xmt1_dma_reg;
903 WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 1002 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
904 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1003 dmp_reg = &reg->iobase_window;
905 for (cnt = 0; cnt < 16; cnt++) 1004 for (cnt = 0; cnt < 16; cnt++)
906 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
907 1006
908 WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 1007 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
909 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1008 dmp_reg = &reg->iobase_window;
910 for (cnt = 0; cnt < 16; cnt++) 1009 for (cnt = 0; cnt < 16; cnt++)
911 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
912 1011
913 iter_reg = fw->xmt2_dma_reg; 1012 iter_reg = fw->xmt2_dma_reg;
914 WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 1013 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
915 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1014 dmp_reg = &reg->iobase_window;
916 for (cnt = 0; cnt < 16; cnt++) 1015 for (cnt = 0; cnt < 16; cnt++)
917 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1016 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
918 1017
919 WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 1018 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
920 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1019 dmp_reg = &reg->iobase_window;
921 for (cnt = 0; cnt < 16; cnt++) 1020 for (cnt = 0; cnt < 16; cnt++)
922 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1021 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
923 1022
924 iter_reg = fw->xmt3_dma_reg; 1023 iter_reg = fw->xmt3_dma_reg;
925 WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 1024 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
926 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1025 dmp_reg = &reg->iobase_window;
927 for (cnt = 0; cnt < 16; cnt++) 1026 for (cnt = 0; cnt < 16; cnt++)
928 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
929 1028
930 WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 1029 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
931 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1030 dmp_reg = &reg->iobase_window;
932 for (cnt = 0; cnt < 16; cnt++) 1031 for (cnt = 0; cnt < 16; cnt++)
933 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
934 1033
935 iter_reg = fw->xmt4_dma_reg; 1034 iter_reg = fw->xmt4_dma_reg;
936 WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 1035 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
937 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1036 dmp_reg = &reg->iobase_window;
938 for (cnt = 0; cnt < 16; cnt++) 1037 for (cnt = 0; cnt < 16; cnt++)
939 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1038 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
940 1039
941 WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 1040 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
942 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1041 dmp_reg = &reg->iobase_window;
943 for (cnt = 0; cnt < 16; cnt++) 1042 for (cnt = 0; cnt < 16; cnt++)
944 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1043 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
945 1044
946 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 1045 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
947 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1046 dmp_reg = &reg->iobase_window;
948 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 1047 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
949 fw->xmt_data_dma_reg[cnt] = 1048 fw->xmt_data_dma_reg[cnt] =
950 htonl(RD_REG_DWORD(dmp_reg++)); 1049 htonl(RD_REG_DWORD(dmp_reg++));
@@ -952,221 +1051,221 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
952 /* Receive DMA registers. */ 1051 /* Receive DMA registers. */
953 iter_reg = fw->rcvt0_data_dma_reg; 1052 iter_reg = fw->rcvt0_data_dma_reg;
954 WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 1053 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
955 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1054 dmp_reg = &reg->iobase_window;
956 for (cnt = 0; cnt < 16; cnt++) 1055 for (cnt = 0; cnt < 16; cnt++)
957 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1056 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
958 1057
959 WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 1058 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
960 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1059 dmp_reg = &reg->iobase_window;
961 for (cnt = 0; cnt < 16; cnt++) 1060 for (cnt = 0; cnt < 16; cnt++)
962 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1061 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
963 1062
964 iter_reg = fw->rcvt1_data_dma_reg; 1063 iter_reg = fw->rcvt1_data_dma_reg;
965 WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 1064 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
966 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1065 dmp_reg = &reg->iobase_window;
967 for (cnt = 0; cnt < 16; cnt++) 1066 for (cnt = 0; cnt < 16; cnt++)
968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1067 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
969 1068
970 WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 1069 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
971 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1070 dmp_reg = &reg->iobase_window;
972 for (cnt = 0; cnt < 16; cnt++) 1071 for (cnt = 0; cnt < 16; cnt++)
973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1072 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
974 1073
975 /* RISC registers. */ 1074 /* RISC registers. */
976 iter_reg = fw->risc_gp_reg; 1075 iter_reg = fw->risc_gp_reg;
977 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 1076 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
978 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1077 dmp_reg = &reg->iobase_window;
979 for (cnt = 0; cnt < 16; cnt++) 1078 for (cnt = 0; cnt < 16; cnt++)
980 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
981 1080
982 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 1081 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
983 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1082 dmp_reg = &reg->iobase_window;
984 for (cnt = 0; cnt < 16; cnt++) 1083 for (cnt = 0; cnt < 16; cnt++)
985 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
986 1085
987 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 1086 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
988 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1087 dmp_reg = &reg->iobase_window;
989 for (cnt = 0; cnt < 16; cnt++) 1088 for (cnt = 0; cnt < 16; cnt++)
990 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
991 1090
992 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 1091 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
993 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1092 dmp_reg = &reg->iobase_window;
994 for (cnt = 0; cnt < 16; cnt++) 1093 for (cnt = 0; cnt < 16; cnt++)
995 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
996 1095
997 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 1096 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
998 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1097 dmp_reg = &reg->iobase_window;
999 for (cnt = 0; cnt < 16; cnt++) 1098 for (cnt = 0; cnt < 16; cnt++)
1000 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1001 1100
1002 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1101 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1003 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1102 dmp_reg = &reg->iobase_window;
1004 for (cnt = 0; cnt < 16; cnt++) 1103 for (cnt = 0; cnt < 16; cnt++)
1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1006 1105
1007 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1106 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1008 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1107 dmp_reg = &reg->iobase_window;
1009 for (cnt = 0; cnt < 16; cnt++) 1108 for (cnt = 0; cnt < 16; cnt++)
1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1011 1110
1012 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1111 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1013 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1112 dmp_reg = &reg->iobase_window;
1014 for (cnt = 0; cnt < 16; cnt++) 1113 for (cnt = 0; cnt < 16; cnt++)
1015 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1016 1115
1017 /* Local memory controller registers. */ 1116 /* Local memory controller registers. */
1018 iter_reg = fw->lmc_reg; 1117 iter_reg = fw->lmc_reg;
1019 WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1118 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1020 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1119 dmp_reg = &reg->iobase_window;
1021 for (cnt = 0; cnt < 16; cnt++) 1120 for (cnt = 0; cnt < 16; cnt++)
1022 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1023 1122
1024 WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1123 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1025 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1124 dmp_reg = &reg->iobase_window;
1026 for (cnt = 0; cnt < 16; cnt++) 1125 for (cnt = 0; cnt < 16; cnt++)
1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1028 1127
1029 WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1128 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1030 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1129 dmp_reg = &reg->iobase_window;
1031 for (cnt = 0; cnt < 16; cnt++) 1130 for (cnt = 0; cnt < 16; cnt++)
1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1033 1132
1034 WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1133 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1035 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1134 dmp_reg = &reg->iobase_window;
1036 for (cnt = 0; cnt < 16; cnt++) 1135 for (cnt = 0; cnt < 16; cnt++)
1037 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1038 1137
1039 WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1138 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1040 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1139 dmp_reg = &reg->iobase_window;
1041 for (cnt = 0; cnt < 16; cnt++) 1140 for (cnt = 0; cnt < 16; cnt++)
1042 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1043 1142
1044 WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1143 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1045 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1144 dmp_reg = &reg->iobase_window;
1046 for (cnt = 0; cnt < 16; cnt++) 1145 for (cnt = 0; cnt < 16; cnt++)
1047 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1048 1147
1049 WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1148 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1050 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1149 dmp_reg = &reg->iobase_window;
1051 for (cnt = 0; cnt < 16; cnt++) 1150 for (cnt = 0; cnt < 16; cnt++)
1052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1053 1152
1054 /* Fibre Protocol Module registers. */ 1153 /* Fibre Protocol Module registers. */
1055 iter_reg = fw->fpm_hdw_reg; 1154 iter_reg = fw->fpm_hdw_reg;
1056 WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1155 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1057 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1156 dmp_reg = &reg->iobase_window;
1058 for (cnt = 0; cnt < 16; cnt++) 1157 for (cnt = 0; cnt < 16; cnt++)
1059 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1158 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1060 1159
1061 WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1160 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1062 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1161 dmp_reg = &reg->iobase_window;
1063 for (cnt = 0; cnt < 16; cnt++) 1162 for (cnt = 0; cnt < 16; cnt++)
1064 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1163 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1065 1164
1066 WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1165 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1166 dmp_reg = &reg->iobase_window;
1068 for (cnt = 0; cnt < 16; cnt++) 1167 for (cnt = 0; cnt < 16; cnt++)
1069 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1168 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1070 1169
1071 WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1170 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1171 dmp_reg = &reg->iobase_window;
1073 for (cnt = 0; cnt < 16; cnt++) 1172 for (cnt = 0; cnt < 16; cnt++)
1074 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1173 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1075 1174
1076 WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1175 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1176 dmp_reg = &reg->iobase_window;
1078 for (cnt = 0; cnt < 16; cnt++) 1177 for (cnt = 0; cnt < 16; cnt++)
1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1178 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1080 1179
1081 WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1180 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1181 dmp_reg = &reg->iobase_window;
1083 for (cnt = 0; cnt < 16; cnt++) 1182 for (cnt = 0; cnt < 16; cnt++)
1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1183 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1085 1184
1086 WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1185 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1186 dmp_reg = &reg->iobase_window;
1088 for (cnt = 0; cnt < 16; cnt++) 1187 for (cnt = 0; cnt < 16; cnt++)
1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1188 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1090 1189
1091 WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1190 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1092 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1191 dmp_reg = &reg->iobase_window;
1093 for (cnt = 0; cnt < 16; cnt++) 1192 for (cnt = 0; cnt < 16; cnt++)
1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1193 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1095 1194
1096 WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1195 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1097 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1196 dmp_reg = &reg->iobase_window;
1098 for (cnt = 0; cnt < 16; cnt++) 1197 for (cnt = 0; cnt < 16; cnt++)
1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1198 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1100 1199
1101 WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1200 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1102 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1201 dmp_reg = &reg->iobase_window;
1103 for (cnt = 0; cnt < 16; cnt++) 1202 for (cnt = 0; cnt < 16; cnt++)
1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1203 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1105 1204
1106 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1205 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1107 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1206 dmp_reg = &reg->iobase_window;
1108 for (cnt = 0; cnt < 16; cnt++) 1207 for (cnt = 0; cnt < 16; cnt++)
1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1208 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1110 1209
1111 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1210 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1112 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1211 dmp_reg = &reg->iobase_window;
1113 for (cnt = 0; cnt < 16; cnt++) 1212 for (cnt = 0; cnt < 16; cnt++)
1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1213 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1115 1214
1116 /* Frame Buffer registers. */ 1215 /* Frame Buffer registers. */
1117 iter_reg = fw->fb_hdw_reg; 1216 iter_reg = fw->fb_hdw_reg;
1118 WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1217 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1218 dmp_reg = &reg->iobase_window;
1120 for (cnt = 0; cnt < 16; cnt++) 1219 for (cnt = 0; cnt < 16; cnt++)
1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1220 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1122 1221
1123 WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1222 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1223 dmp_reg = &reg->iobase_window;
1125 for (cnt = 0; cnt < 16; cnt++) 1224 for (cnt = 0; cnt < 16; cnt++)
1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1225 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1127 1226
1128 WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1227 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1228 dmp_reg = &reg->iobase_window;
1130 for (cnt = 0; cnt < 16; cnt++) 1229 for (cnt = 0; cnt < 16; cnt++)
1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1230 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1132 1231
1133 WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1232 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1233 dmp_reg = &reg->iobase_window;
1135 for (cnt = 0; cnt < 16; cnt++) 1234 for (cnt = 0; cnt < 16; cnt++)
1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1235 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1137 1236
1138 WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1237 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1238 dmp_reg = &reg->iobase_window;
1140 for (cnt = 0; cnt < 16; cnt++) 1239 for (cnt = 0; cnt < 16; cnt++)
1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1240 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1142 1241
1143 WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1242 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1243 dmp_reg = &reg->iobase_window;
1145 for (cnt = 0; cnt < 16; cnt++) 1244 for (cnt = 0; cnt < 16; cnt++)
1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1245 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1147 1246
1148 WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1247 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1149 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1248 dmp_reg = &reg->iobase_window;
1150 for (cnt = 0; cnt < 16; cnt++) 1249 for (cnt = 0; cnt < 16; cnt++)
1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1250 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1152 1251
1153 WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1252 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1154 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1253 dmp_reg = &reg->iobase_window;
1155 for (cnt = 0; cnt < 16; cnt++) 1254 for (cnt = 0; cnt < 16; cnt++)
1156 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1255 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1157 1256
1158 WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1257 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1159 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1258 dmp_reg = &reg->iobase_window;
1160 for (cnt = 0; cnt < 16; cnt++) 1259 for (cnt = 0; cnt < 16; cnt++)
1161 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1260 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1162 1261
1163 WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1262 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1164 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1263 dmp_reg = &reg->iobase_window;
1165 for (cnt = 0; cnt < 16; cnt++) 1264 for (cnt = 0; cnt < 16; cnt++)
1166 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1265 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1167 1266
1168 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1267 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1268 dmp_reg = &reg->iobase_window;
1170 for (cnt = 0; cnt < 16; cnt++) 1269 for (cnt = 0; cnt < 16; cnt++)
1171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1270 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1172 1271
@@ -1187,10 +1286,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1187 1286
1188 udelay(100); 1287 udelay(100);
1189 /* Wait for firmware to complete NVRAM accesses. */ 1288 /* Wait for firmware to complete NVRAM accesses. */
1190 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1289 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1191 for (cnt = 10000 ; cnt && mb[0]; cnt--) { 1290 for (cnt = 10000 ; cnt && mb0; cnt--) {
1192 udelay(5); 1291 udelay(5);
1193 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1292 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1194 barrier(); 1293 barrier();
1195 } 1294 }
1196 1295
@@ -1214,110 +1313,717 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1214 rval = QLA_FUNCTION_TIMEOUT; 1313 rval = QLA_FUNCTION_TIMEOUT;
1215 } 1314 }
1216 1315
1217 /* Memory. */ 1316 if (rval == QLA_SUCCESS)
1317 rval = qla2xxx_dump_memory(ha, fw->code_ram,
1318 sizeof(fw->code_ram), fw->ext_mem, &nxt);
1319
1218 if (rval == QLA_SUCCESS) { 1320 if (rval == QLA_SUCCESS) {
1219 /* Code RAM. */ 1321 nxt = qla2xxx_copy_queues(ha, nxt);
1220 risc_address = 0x20000; 1322 if (ha->eft)
1221 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 1323 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1222 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1223 } 1324 }
1224 for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
1225 cnt++, risc_address++) {
1226 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1227 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1228 RD_REG_WORD(&reg->mailbox8);
1229 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1230 1325
1231 for (timer = 6000000; timer; timer--) { 1326 if (rval != QLA_SUCCESS) {
1232 /* Check for pending interrupts. */ 1327 qla_printk(KERN_WARNING, ha,
1233 stat = RD_REG_DWORD(&reg->host_status); 1328 "Failed to dump firmware (%x)!!!\n", rval);
1234 if (stat & HSRX_RISC_INT) { 1329 ha->fw_dumped = 0;
1235 stat &= 0xff;
1236 1330
1237 if (stat == 0x1 || stat == 0x2 || 1331 } else {
1238 stat == 0x10 || stat == 0x11) { 1332 qla_printk(KERN_INFO, ha,
1239 set_bit(MBX_INTERRUPT, 1333 "Firmware dump saved to temp buffer (%ld/%p).\n",
1240 &ha->mbx_cmd_flags); 1334 ha->host_no, ha->fw_dump);
1335 ha->fw_dumped = 1;
1336 }
1241 1337
1242 mb[0] = RD_REG_WORD(&reg->mailbox0); 1338qla24xx_fw_dump_failed:
1243 mb[2] = RD_REG_WORD(&reg->mailbox2); 1339 if (!hardware_locked)
1244 mb[3] = RD_REG_WORD(&reg->mailbox3); 1340 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1341}
1245 1342
1246 WRT_REG_DWORD(&reg->hccr, 1343void
1247 HCCRX_CLR_RISC_INT); 1344qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1248 RD_REG_DWORD(&reg->hccr); 1345{
1249 break; 1346 int rval;
1250 } 1347 uint32_t cnt;
1348 uint32_t risc_address;
1349 uint16_t mb0, wd;
1251 1350
1252 /* Clear this intr; it wasn't a mailbox intr */ 1351 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1253 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 1352 uint32_t __iomem *dmp_reg;
1254 RD_REG_DWORD(&reg->hccr); 1353 uint32_t *iter_reg;
1255 } 1354 uint16_t __iomem *mbx_reg;
1256 udelay(5); 1355 unsigned long flags;
1257 } 1356 struct qla25xx_fw_dump *fw;
1357 uint32_t ext_mem_cnt;
1358 void *nxt;
1258 1359
1259 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1360 risc_address = ext_mem_cnt = 0;
1260 rval = mb[0] & MBS_MASK; 1361 flags = 0;
1261 fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); 1362
1262 } else { 1363 if (!hardware_locked)
1263 rval = QLA_FUNCTION_FAILED; 1364 spin_lock_irqsave(&ha->hardware_lock, flags);
1365
1366 if (!ha->fw_dump) {
1367 qla_printk(KERN_WARNING, ha,
1368 "No buffer available for dump!!!\n");
1369 goto qla25xx_fw_dump_failed;
1370 }
1371
1372 if (ha->fw_dumped) {
1373 qla_printk(KERN_WARNING, ha,
1374 "Firmware has been previously dumped (%p) -- ignoring "
1375 "request...\n", ha->fw_dump);
1376 goto qla25xx_fw_dump_failed;
1377 }
1378 fw = &ha->fw_dump->isp.isp25;
1379 qla2xxx_prep_dump(ha, ha->fw_dump);
1380
1381 rval = QLA_SUCCESS;
1382 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1383
1384 /* Pause RISC. */
1385 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) {
1386 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
1387 HCCRX_CLR_HOST_INT);
1388 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1389 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
1390 for (cnt = 30000;
1391 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
1392 rval == QLA_SUCCESS; cnt--) {
1393 if (cnt)
1394 udelay(100);
1395 else
1396 rval = QLA_FUNCTION_TIMEOUT;
1264 } 1397 }
1265 } 1398 }
1266 1399
1267 if (rval == QLA_SUCCESS) { 1400 if (rval == QLA_SUCCESS) {
1268 /* External Memory. */ 1401 /* Host interface registers. */
1269 risc_address = 0x100000; 1402 dmp_reg = (uint32_t __iomem *)(reg + 0);
1270 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; 1403 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1271 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 1404 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1272 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1273 }
1274 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
1275 cnt++, risc_address++) {
1276 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1277 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1278 RD_REG_WORD(&reg->mailbox8);
1279 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1280 1405
1281 for (timer = 6000000; timer; timer--) { 1406 /* Disable interrupts. */
1282 /* Check for pending interrupts. */ 1407 WRT_REG_DWORD(&reg->ictrl, 0);
1283 stat = RD_REG_DWORD(&reg->host_status); 1408 RD_REG_DWORD(&reg->ictrl);
1284 if (stat & HSRX_RISC_INT) {
1285 stat &= 0xff;
1286 1409
1287 if (stat == 0x1 || stat == 0x2 || 1410 /* Shadow registers. */
1288 stat == 0x10 || stat == 0x11) { 1411 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1289 set_bit(MBX_INTERRUPT, 1412 RD_REG_DWORD(&reg->iobase_addr);
1290 &ha->mbx_cmd_flags); 1413 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1414 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1291 1415
1292 mb[0] = RD_REG_WORD(&reg->mailbox0); 1416 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1293 mb[2] = RD_REG_WORD(&reg->mailbox2); 1417 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1294 mb[3] = RD_REG_WORD(&reg->mailbox3);
1295 1418
1296 WRT_REG_DWORD(&reg->hccr, 1419 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1297 HCCRX_CLR_RISC_INT); 1420 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1298 RD_REG_DWORD(&reg->hccr);
1299 break;
1300 }
1301 1421
1302 /* Clear this intr; it wasn't a mailbox intr */ 1422 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1303 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 1423 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1304 RD_REG_DWORD(&reg->hccr); 1424
1305 } 1425 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1426 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1427
1428 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1429 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1430
1431 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1432 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1433
1434 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1435 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1436
1437 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1438 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1439
1440 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1441 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1442
1443 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1444 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1445
1446 /* RISC I/O register. */
1447 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1448 RD_REG_DWORD(&reg->iobase_addr);
1449 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1450
1451 /* Mailbox registers. */
1452 mbx_reg = &reg->mailbox0;
1453 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1454 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1455
1456 /* Transfer sequence registers. */
1457 iter_reg = fw->xseq_gp_reg;
1458 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1459 dmp_reg = &reg->iobase_window;
1460 for (cnt = 0; cnt < 16; cnt++)
1461 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1462
1463 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1464 dmp_reg = &reg->iobase_window;
1465 for (cnt = 0; cnt < 16; cnt++)
1466 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1467
1468 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1469 dmp_reg = &reg->iobase_window;
1470 for (cnt = 0; cnt < 16; cnt++)
1471 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1472
1473 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1474 dmp_reg = &reg->iobase_window;
1475 for (cnt = 0; cnt < 16; cnt++)
1476 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1477
1478 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1479 dmp_reg = &reg->iobase_window;
1480 for (cnt = 0; cnt < 16; cnt++)
1481 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1482
1483 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1484 dmp_reg = &reg->iobase_window;
1485 for (cnt = 0; cnt < 16; cnt++)
1486 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1487
1488 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1489 dmp_reg = &reg->iobase_window;
1490 for (cnt = 0; cnt < 16; cnt++)
1491 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1492
1493 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1494 dmp_reg = &reg->iobase_window;
1495 for (cnt = 0; cnt < 16; cnt++)
1496 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1497
1498 iter_reg = fw->xseq_0_reg;
1499 WRT_REG_DWORD(&reg->iobase_addr, 0xBFC0);
1500 dmp_reg = &reg->iobase_window;
1501 for (cnt = 0; cnt < 16; cnt++)
1502 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1503
1504 WRT_REG_DWORD(&reg->iobase_addr, 0xBFD0);
1505 dmp_reg = &reg->iobase_window;
1506 for (cnt = 0; cnt < 16; cnt++)
1507 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1508
1509 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1510 dmp_reg = &reg->iobase_window;
1511 for (cnt = 0; cnt < 16; cnt++)
1512 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1513
1514 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1515 dmp_reg = &reg->iobase_window;
1516 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1517 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1518
1519 /* Receive sequence registers. */
1520 iter_reg = fw->rseq_gp_reg;
1521 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1522 dmp_reg = &reg->iobase_window;
1523 for (cnt = 0; cnt < 16; cnt++)
1524 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1525
1526 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1527 dmp_reg = &reg->iobase_window;
1528 for (cnt = 0; cnt < 16; cnt++)
1529 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1530
1531 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1532 dmp_reg = &reg->iobase_window;
1533 for (cnt = 0; cnt < 16; cnt++)
1534 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1535
1536 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1537 dmp_reg = &reg->iobase_window;
1538 for (cnt = 0; cnt < 16; cnt++)
1539 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1540
1541 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1542 dmp_reg = &reg->iobase_window;
1543 for (cnt = 0; cnt < 16; cnt++)
1544 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1545
1546 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1547 dmp_reg = &reg->iobase_window;
1548 for (cnt = 0; cnt < 16; cnt++)
1549 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1550
1551 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1552 dmp_reg = &reg->iobase_window;
1553 for (cnt = 0; cnt < 16; cnt++)
1554 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1555
1556 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1557 dmp_reg = &reg->iobase_window;
1558 for (cnt = 0; cnt < 16; cnt++)
1559 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1560
1561 iter_reg = fw->rseq_0_reg;
1562 WRT_REG_DWORD(&reg->iobase_addr, 0xFFC0);
1563 dmp_reg = &reg->iobase_window;
1564 for (cnt = 0; cnt < 16; cnt++)
1565 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1566
1567 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1568 dmp_reg = &reg->iobase_window;
1569 for (cnt = 0; cnt < 16; cnt++)
1570 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1571
1572 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1573 dmp_reg = &reg->iobase_window;
1574 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1575 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1576
1577 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1578 dmp_reg = &reg->iobase_window;
1579 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1580 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1581
1582 /* Auxiliary sequence registers. */
1583 iter_reg = fw->aseq_gp_reg;
1584 WRT_REG_DWORD(&reg->iobase_addr, 0xB000);
1585 dmp_reg = &reg->iobase_window;
1586 for (cnt = 0; cnt < 16; cnt++)
1587 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1588
1589 WRT_REG_DWORD(&reg->iobase_addr, 0xB010);
1590 dmp_reg = &reg->iobase_window;
1591 for (cnt = 0; cnt < 16; cnt++)
1592 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1593
1594 WRT_REG_DWORD(&reg->iobase_addr, 0xB020);
1595 dmp_reg = &reg->iobase_window;
1596 for (cnt = 0; cnt < 16; cnt++)
1597 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1598
1599 WRT_REG_DWORD(&reg->iobase_addr, 0xB030);
1600 dmp_reg = &reg->iobase_window;
1601 for (cnt = 0; cnt < 16; cnt++)
1602 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1603
1604 WRT_REG_DWORD(&reg->iobase_addr, 0xB040);
1605 dmp_reg = &reg->iobase_window;
1606 for (cnt = 0; cnt < 16; cnt++)
1607 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1608
1609 WRT_REG_DWORD(&reg->iobase_addr, 0xB050);
1610 dmp_reg = &reg->iobase_window;
1611 for (cnt = 0; cnt < 16; cnt++)
1612 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1613
1614 WRT_REG_DWORD(&reg->iobase_addr, 0xB060);
1615 dmp_reg = &reg->iobase_window;
1616 for (cnt = 0; cnt < 16; cnt++)
1617 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1618
1619 WRT_REG_DWORD(&reg->iobase_addr, 0xB070);
1620 dmp_reg = &reg->iobase_window;
1621 for (cnt = 0; cnt < 16; cnt++)
1622 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1623
1624 iter_reg = fw->aseq_0_reg;
1625 WRT_REG_DWORD(&reg->iobase_addr, 0xB0C0);
1626 dmp_reg = &reg->iobase_window;
1627 for (cnt = 0; cnt < 16; cnt++)
1628 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1629
1630 WRT_REG_DWORD(&reg->iobase_addr, 0xB0D0);
1631 dmp_reg = &reg->iobase_window;
1632 for (cnt = 0; cnt < 16; cnt++)
1633 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1634
1635 WRT_REG_DWORD(&reg->iobase_addr, 0xB0E0);
1636 dmp_reg = &reg->iobase_window;
1637 for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++)
1638 fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1639
1640 WRT_REG_DWORD(&reg->iobase_addr, 0xB0F0);
1641 dmp_reg = &reg->iobase_window;
1642 for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++)
1643 fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1644
1645 /* Command DMA registers. */
1646 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1647 dmp_reg = &reg->iobase_window;
1648 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1649 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1650
1651 /* Queues. */
1652 iter_reg = fw->req0_dma_reg;
1653 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1654 dmp_reg = &reg->iobase_window;
1655 for (cnt = 0; cnt < 8; cnt++)
1656 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1657
1658 dmp_reg = &reg->iobase_q;
1659 for (cnt = 0; cnt < 7; cnt++)
1660 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1661
1662 iter_reg = fw->resp0_dma_reg;
1663 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1664 dmp_reg = &reg->iobase_window;
1665 for (cnt = 0; cnt < 8; cnt++)
1666 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1667
1668 dmp_reg = &reg->iobase_q;
1669 for (cnt = 0; cnt < 7; cnt++)
1670 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1671
1672 iter_reg = fw->req1_dma_reg;
1673 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1674 dmp_reg = &reg->iobase_window;
1675 for (cnt = 0; cnt < 8; cnt++)
1676 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1677
1678 dmp_reg = &reg->iobase_q;
1679 for (cnt = 0; cnt < 7; cnt++)
1680 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1681
1682 /* Transmit DMA registers. */
1683 iter_reg = fw->xmt0_dma_reg;
1684 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1685 dmp_reg = &reg->iobase_window;
1686 for (cnt = 0; cnt < 16; cnt++)
1687 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1688
1689 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1690 dmp_reg = &reg->iobase_window;
1691 for (cnt = 0; cnt < 16; cnt++)
1692 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1693
1694 iter_reg = fw->xmt1_dma_reg;
1695 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1696 dmp_reg = &reg->iobase_window;
1697 for (cnt = 0; cnt < 16; cnt++)
1698 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1699
1700 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1701 dmp_reg = &reg->iobase_window;
1702 for (cnt = 0; cnt < 16; cnt++)
1703 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1704
1705 iter_reg = fw->xmt2_dma_reg;
1706 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1707 dmp_reg = &reg->iobase_window;
1708 for (cnt = 0; cnt < 16; cnt++)
1709 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1710
1711 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1712 dmp_reg = &reg->iobase_window;
1713 for (cnt = 0; cnt < 16; cnt++)
1714 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1715
1716 iter_reg = fw->xmt3_dma_reg;
1717 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1718 dmp_reg = &reg->iobase_window;
1719 for (cnt = 0; cnt < 16; cnt++)
1720 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1721
1722 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1723 dmp_reg = &reg->iobase_window;
1724 for (cnt = 0; cnt < 16; cnt++)
1725 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1726
1727 iter_reg = fw->xmt4_dma_reg;
1728 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1729 dmp_reg = &reg->iobase_window;
1730 for (cnt = 0; cnt < 16; cnt++)
1731 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1732
1733 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1734 dmp_reg = &reg->iobase_window;
1735 for (cnt = 0; cnt < 16; cnt++)
1736 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1737
1738 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1739 dmp_reg = &reg->iobase_window;
1740 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1741 fw->xmt_data_dma_reg[cnt] =
1742 htonl(RD_REG_DWORD(dmp_reg++));
1743
1744 /* Receive DMA registers. */
1745 iter_reg = fw->rcvt0_data_dma_reg;
1746 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1747 dmp_reg = &reg->iobase_window;
1748 for (cnt = 0; cnt < 16; cnt++)
1749 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1750
1751 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1752 dmp_reg = &reg->iobase_window;
1753 for (cnt = 0; cnt < 16; cnt++)
1754 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1755
1756 iter_reg = fw->rcvt1_data_dma_reg;
1757 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1758 dmp_reg = &reg->iobase_window;
1759 for (cnt = 0; cnt < 16; cnt++)
1760 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1761
1762 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1763 dmp_reg = &reg->iobase_window;
1764 for (cnt = 0; cnt < 16; cnt++)
1765 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1766
1767 /* RISC registers. */
1768 iter_reg = fw->risc_gp_reg;
1769 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1770 dmp_reg = &reg->iobase_window;
1771 for (cnt = 0; cnt < 16; cnt++)
1772 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1773
1774 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1775 dmp_reg = &reg->iobase_window;
1776 for (cnt = 0; cnt < 16; cnt++)
1777 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1778
1779 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1780 dmp_reg = &reg->iobase_window;
1781 for (cnt = 0; cnt < 16; cnt++)
1782 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1783
1784 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1785 dmp_reg = &reg->iobase_window;
1786 for (cnt = 0; cnt < 16; cnt++)
1787 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1788
1789 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1790 dmp_reg = &reg->iobase_window;
1791 for (cnt = 0; cnt < 16; cnt++)
1792 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1793
1794 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1795 dmp_reg = &reg->iobase_window;
1796 for (cnt = 0; cnt < 16; cnt++)
1797 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1798
1799 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1800 dmp_reg = &reg->iobase_window;
1801 for (cnt = 0; cnt < 16; cnt++)
1802 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1803
1804 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1805 dmp_reg = &reg->iobase_window;
1806 for (cnt = 0; cnt < 16; cnt++)
1807 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1808
1809 /* Local memory controller registers. */
1810 iter_reg = fw->lmc_reg;
1811 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1812 dmp_reg = &reg->iobase_window;
1813 for (cnt = 0; cnt < 16; cnt++)
1814 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1815
1816 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1817 dmp_reg = &reg->iobase_window;
1818 for (cnt = 0; cnt < 16; cnt++)
1819 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1820
1821 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1822 dmp_reg = &reg->iobase_window;
1823 for (cnt = 0; cnt < 16; cnt++)
1824 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1825
1826 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1827 dmp_reg = &reg->iobase_window;
1828 for (cnt = 0; cnt < 16; cnt++)
1829 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1830
1831 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1832 dmp_reg = &reg->iobase_window;
1833 for (cnt = 0; cnt < 16; cnt++)
1834 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1835
1836 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1837 dmp_reg = &reg->iobase_window;
1838 for (cnt = 0; cnt < 16; cnt++)
1839 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1840
1841 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1842 dmp_reg = &reg->iobase_window;
1843 for (cnt = 0; cnt < 16; cnt++)
1844 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1845
1846 WRT_REG_DWORD(&reg->iobase_addr, 0x3070);
1847 dmp_reg = &reg->iobase_window;
1848 for (cnt = 0; cnt < 16; cnt++)
1849 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1850
1851 /* Fibre Protocol Module registers. */
1852 iter_reg = fw->fpm_hdw_reg;
1853 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1854 dmp_reg = &reg->iobase_window;
1855 for (cnt = 0; cnt < 16; cnt++)
1856 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1857
1858 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1859 dmp_reg = &reg->iobase_window;
1860 for (cnt = 0; cnt < 16; cnt++)
1861 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1862
1863 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1864 dmp_reg = &reg->iobase_window;
1865 for (cnt = 0; cnt < 16; cnt++)
1866 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1867
1868 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1869 dmp_reg = &reg->iobase_window;
1870 for (cnt = 0; cnt < 16; cnt++)
1871 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1872
1873 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1874 dmp_reg = &reg->iobase_window;
1875 for (cnt = 0; cnt < 16; cnt++)
1876 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1877
1878 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1879 dmp_reg = &reg->iobase_window;
1880 for (cnt = 0; cnt < 16; cnt++)
1881 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1882
1883 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1884 dmp_reg = &reg->iobase_window;
1885 for (cnt = 0; cnt < 16; cnt++)
1886 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1887
1888 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1889 dmp_reg = &reg->iobase_window;
1890 for (cnt = 0; cnt < 16; cnt++)
1891 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1892
1893 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1894 dmp_reg = &reg->iobase_window;
1895 for (cnt = 0; cnt < 16; cnt++)
1896 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1897
1898 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1899 dmp_reg = &reg->iobase_window;
1900 for (cnt = 0; cnt < 16; cnt++)
1901 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1902
1903 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1904 dmp_reg = &reg->iobase_window;
1905 for (cnt = 0; cnt < 16; cnt++)
1906 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1907
1908 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1909 dmp_reg = &reg->iobase_window;
1910 for (cnt = 0; cnt < 16; cnt++)
1911 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1912
1913 /* Frame Buffer registers. */
1914 iter_reg = fw->fb_hdw_reg;
1915 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1916 dmp_reg = &reg->iobase_window;
1917 for (cnt = 0; cnt < 16; cnt++)
1918 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1919
1920 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1921 dmp_reg = &reg->iobase_window;
1922 for (cnt = 0; cnt < 16; cnt++)
1923 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1924
1925 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1926 dmp_reg = &reg->iobase_window;
1927 for (cnt = 0; cnt < 16; cnt++)
1928 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1929
1930 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1931 dmp_reg = &reg->iobase_window;
1932 for (cnt = 0; cnt < 16; cnt++)
1933 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1934
1935 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1936 dmp_reg = &reg->iobase_window;
1937 for (cnt = 0; cnt < 16; cnt++)
1938 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1939
1940 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1941 dmp_reg = &reg->iobase_window;
1942 for (cnt = 0; cnt < 16; cnt++)
1943 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1944
1945 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1946 dmp_reg = &reg->iobase_window;
1947 for (cnt = 0; cnt < 16; cnt++)
1948 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1949
1950 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1951 dmp_reg = &reg->iobase_window;
1952 for (cnt = 0; cnt < 16; cnt++)
1953 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1954
1955 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1956 dmp_reg = &reg->iobase_window;
1957 for (cnt = 0; cnt < 16; cnt++)
1958 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1959
1960 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1961 dmp_reg = &reg->iobase_window;
1962 for (cnt = 0; cnt < 16; cnt++)
1963 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1964
1965 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1966 dmp_reg = &reg->iobase_window;
1967 for (cnt = 0; cnt < 16; cnt++)
1968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1969
1970 WRT_REG_DWORD(&reg->iobase_addr, 0x6F00);
1971 dmp_reg = &reg->iobase_window;
1972 for (cnt = 0; cnt < 16; cnt++)
1973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1974
1975 /* Reset RISC. */
1976 WRT_REG_DWORD(&reg->ctrl_status,
1977 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1978 for (cnt = 0; cnt < 30000; cnt++) {
1979 if ((RD_REG_DWORD(&reg->ctrl_status) &
1980 CSRX_DMA_ACTIVE) == 0)
1981 break;
1982
1983 udelay(10);
1984 }
1985
1986 WRT_REG_DWORD(&reg->ctrl_status,
1987 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1988 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1989
1990 udelay(100);
1991 /* Wait for firmware to complete NVRAM accesses. */
1992 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1993 for (cnt = 10000 ; cnt && mb0; cnt--) {
1306 udelay(5); 1994 udelay(5);
1995 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1996 barrier();
1307 } 1997 }
1308 1998
1309 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1999 /* Wait for soft-reset to complete. */
1310 rval = mb[0] & MBS_MASK; 2000 for (cnt = 0; cnt < 30000; cnt++) {
1311 fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 2001 if ((RD_REG_DWORD(&reg->ctrl_status) &
1312 } else { 2002 CSRX_ISP_SOFT_RESET) == 0)
1313 rval = QLA_FUNCTION_FAILED; 2003 break;
2004
2005 udelay(10);
1314 } 2006 }
2007 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2008 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1315 } 2009 }
1316 2010
2011 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2012 rval == QLA_SUCCESS; cnt--) {
2013 if (cnt)
2014 udelay(100);
2015 else
2016 rval = QLA_FUNCTION_TIMEOUT;
2017 }
2018
2019 if (rval == QLA_SUCCESS)
2020 rval = qla2xxx_dump_memory(ha, fw->code_ram,
2021 sizeof(fw->code_ram), fw->ext_mem, &nxt);
2022
1317 if (rval == QLA_SUCCESS) { 2023 if (rval == QLA_SUCCESS) {
1318 eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]); 2024 nxt = qla2xxx_copy_queues(ha, nxt);
1319 if (ha->eft) 2025 if (ha->eft)
1320 memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size)); 2026 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1321 } 2027 }
1322 2028
1323 if (rval != QLA_SUCCESS) { 2029 if (rval != QLA_SUCCESS) {
@@ -1332,7 +2038,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1332 ha->fw_dumped = 1; 2038 ha->fw_dumped = 1;
1333 } 2039 }
1334 2040
1335qla24xx_fw_dump_failed: 2041qla25xx_fw_dump_failed:
1336 if (!hardware_locked) 2042 if (!hardware_locked)
1337 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2043 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1338} 2044}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 13:28:11 -0500