diff options
author | Sakthivel K <Sakthivel.SaravananKamalRaju@pmcs.com> | 2013-04-17 06:56:36 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2013-05-10 10:47:45 -0400 |
commit | e574210170c4a9a1bf1d3afd158d06edd3a840de (patch) | |
tree | 00423e7125d999bef9b9aff810e7f673cc89f3ed /drivers/scsi/pm8001/pm8001_hwi.c | |
parent | 6a7252fdb0c3259d123c39c365ea4a7740885279 (diff) |
[SCSI] pm80xx: Added SPCv/ve specific ids, variables and modify for SPC
Updated pci id table with device, vendor, subdevice and subvendor ids
for 8081, 8088, 8089 SAS/SATA controllers. Added SPCv/ve related macros.
Updated macros, hba info structure and other structures for SPCv/ve.
Update of structure and variable names for SPC hardware functionalities.
Signed-off-by: Sakthivel K <Sakthivel.SaravananKamalRaju@pmcs.com>
Signed-off-by: Anand Kumar S <AnandKumar.Santhanam@pmcs.com>
Acked-by: Jack Wang <jack_wang@usish.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/pm8001/pm8001_hwi.c')
-rw-r--r-- | drivers/scsi/pm8001/pm8001_hwi.c | 213 |
1 files changed, 128 insertions, 85 deletions
diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c index b8dd05074abb..9846ee648384 100644 --- a/drivers/scsi/pm8001/pm8001_hwi.c +++ b/drivers/scsi/pm8001/pm8001_hwi.c | |||
@@ -50,32 +50,39 @@ | |||
50 | static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) | 50 | static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) |
51 | { | 51 | { |
52 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; | 52 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; |
53 | pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00); | 53 | pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = |
54 | pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04); | 54 | pm8001_mr32(address, 0x00); |
55 | pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08); | 55 | pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = |
56 | pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C); | 56 | pm8001_mr32(address, 0x04); |
57 | pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10); | 57 | pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = |
58 | pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14); | 58 | pm8001_mr32(address, 0x08); |
59 | pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18); | 59 | pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = |
60 | pm8001_ha->main_cfg_tbl.inbound_queue_offset = | 60 | pm8001_mr32(address, 0x0C); |
61 | pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = | ||
62 | pm8001_mr32(address, 0x10); | ||
63 | pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = | ||
64 | pm8001_mr32(address, 0x14); | ||
65 | pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = | ||
66 | pm8001_mr32(address, 0x18); | ||
67 | pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = | ||
61 | pm8001_mr32(address, MAIN_IBQ_OFFSET); | 68 | pm8001_mr32(address, MAIN_IBQ_OFFSET); |
62 | pm8001_ha->main_cfg_tbl.outbound_queue_offset = | 69 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = |
63 | pm8001_mr32(address, MAIN_OBQ_OFFSET); | 70 | pm8001_mr32(address, MAIN_OBQ_OFFSET); |
64 | pm8001_ha->main_cfg_tbl.hda_mode_flag = | 71 | pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = |
65 | pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); | 72 | pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); |
66 | 73 | ||
67 | /* read analog Setting offset from the configuration table */ | 74 | /* read analog Setting offset from the configuration table */ |
68 | pm8001_ha->main_cfg_tbl.anolog_setup_table_offset = | 75 | pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = |
69 | pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); | 76 | pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); |
70 | 77 | ||
71 | /* read Error Dump Offset and Length */ | 78 | /* read Error Dump Offset and Length */ |
72 | pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 = | 79 | pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = |
73 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); | 80 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); |
74 | pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 = | 81 | pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = |
75 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); | 82 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); |
76 | pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 = | 83 | pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = |
77 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); | 84 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); |
78 | pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 = | 85 | pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = |
79 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); | 86 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); |
80 | } | 87 | } |
81 | 88 | ||
@@ -86,31 +93,56 @@ static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) | |||
86 | static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) | 93 | static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) |
87 | { | 94 | { |
88 | void __iomem *address = pm8001_ha->general_stat_tbl_addr; | 95 | void __iomem *address = pm8001_ha->general_stat_tbl_addr; |
89 | pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00); | 96 | pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = |
90 | pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04); | 97 | pm8001_mr32(address, 0x00); |
91 | pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08); | 98 | pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = |
92 | pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C); | 99 | pm8001_mr32(address, 0x04); |
93 | pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10); | 100 | pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = |
94 | pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14); | 101 | pm8001_mr32(address, 0x08); |
95 | pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18); | 102 | pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = |
96 | pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C); | 103 | pm8001_mr32(address, 0x0C); |
97 | pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20); | 104 | pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = |
98 | pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24); | 105 | pm8001_mr32(address, 0x10); |
99 | pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28); | 106 | pm8001_ha->gs_tbl.pm8001_tbl.rsvd = |
100 | pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C); | 107 | pm8001_mr32(address, 0x14); |
101 | pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30); | 108 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = |
102 | pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34); | 109 | pm8001_mr32(address, 0x18); |
103 | pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38); | 110 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = |
104 | pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C); | 111 | pm8001_mr32(address, 0x1C); |
105 | pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40); | 112 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = |
106 | pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44); | 113 | pm8001_mr32(address, 0x20); |
107 | pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48); | 114 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = |
108 | pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C); | 115 | pm8001_mr32(address, 0x24); |
109 | pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50); | 116 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = |
110 | pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54); | 117 | pm8001_mr32(address, 0x28); |
111 | pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58); | 118 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = |
112 | pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C); | 119 | pm8001_mr32(address, 0x2C); |
113 | pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60); | 120 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = |
121 | pm8001_mr32(address, 0x30); | ||
122 | pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = | ||
123 | pm8001_mr32(address, 0x34); | ||
124 | pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = | ||
125 | pm8001_mr32(address, 0x38); | ||
126 | pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = | ||
127 | pm8001_mr32(address, 0x3C); | ||
128 | pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = | ||
129 | pm8001_mr32(address, 0x40); | ||
130 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = | ||
131 | pm8001_mr32(address, 0x44); | ||
132 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = | ||
133 | pm8001_mr32(address, 0x48); | ||
134 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = | ||
135 | pm8001_mr32(address, 0x4C); | ||
136 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = | ||
137 | pm8001_mr32(address, 0x50); | ||
138 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = | ||
139 | pm8001_mr32(address, 0x54); | ||
140 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = | ||
141 | pm8001_mr32(address, 0x58); | ||
142 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = | ||
143 | pm8001_mr32(address, 0x5C); | ||
144 | pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = | ||
145 | pm8001_mr32(address, 0x60); | ||
114 | } | 146 | } |
115 | 147 | ||
116 | /** | 148 | /** |
@@ -155,38 +187,41 @@ static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) | |||
155 | */ | 187 | */ |
156 | static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) | 188 | static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) |
157 | { | 189 | { |
158 | int qn = 1; | ||
159 | int i; | 190 | int i; |
160 | u32 offsetib, offsetob; | 191 | u32 offsetib, offsetob; |
161 | void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; | 192 | void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; |
162 | void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; | 193 | void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; |
163 | 194 | ||
164 | pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0; | 195 | pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; |
165 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0; | 196 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; |
166 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0; | 197 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; |
167 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0; | 198 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; |
168 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0; | 199 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; |
169 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0; | 200 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = |
170 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0; | 201 | 0; |
171 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0; | 202 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = |
172 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0; | 203 | 0; |
173 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0; | 204 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; |
174 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0; | 205 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; |
175 | 206 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; | |
176 | pm8001_ha->main_cfg_tbl.upper_event_log_addr = | 207 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; |
208 | |||
209 | pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = | ||
177 | pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; | 210 | pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; |
178 | pm8001_ha->main_cfg_tbl.lower_event_log_addr = | 211 | pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = |
179 | pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; | 212 | pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; |
180 | pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE; | 213 | pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = |
181 | pm8001_ha->main_cfg_tbl.event_log_option = 0x01; | 214 | PM8001_EVENT_LOG_SIZE; |
182 | pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr = | 215 | pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; |
216 | pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = | ||
183 | pm8001_ha->memoryMap.region[IOP].phys_addr_hi; | 217 | pm8001_ha->memoryMap.region[IOP].phys_addr_hi; |
184 | pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr = | 218 | pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = |
185 | pm8001_ha->memoryMap.region[IOP].phys_addr_lo; | 219 | pm8001_ha->memoryMap.region[IOP].phys_addr_lo; |
186 | pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE; | 220 | pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = |
187 | pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01; | 221 | PM8001_EVENT_LOG_SIZE; |
188 | pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01; | 222 | pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; |
189 | for (i = 0; i < qn; i++) { | 223 | pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; |
224 | for (i = 0; i < PM8001_MAX_INB_NUM; i++) { | ||
190 | pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = | 225 | pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = |
191 | PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30); | 226 | PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30); |
192 | pm8001_ha->inbnd_q_tbl[i].upper_base_addr = | 227 | pm8001_ha->inbnd_q_tbl[i].upper_base_addr = |
@@ -212,7 +247,7 @@ static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) | |||
212 | pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; | 247 | pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; |
213 | pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; | 248 | pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; |
214 | } | 249 | } |
215 | for (i = 0; i < qn; i++) { | 250 | for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { |
216 | pm8001_ha->outbnd_q_tbl[i].element_size_cnt = | 251 | pm8001_ha->outbnd_q_tbl[i].element_size_cnt = |
217 | PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30); | 252 | PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30); |
218 | pm8001_ha->outbnd_q_tbl[i].upper_base_addr = | 253 | pm8001_ha->outbnd_q_tbl[i].upper_base_addr = |
@@ -250,42 +285,51 @@ static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) | |||
250 | { | 285 | { |
251 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; | 286 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; |
252 | pm8001_mw32(address, 0x24, | 287 | pm8001_mw32(address, 0x24, |
253 | pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd); | 288 | pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); |
254 | pm8001_mw32(address, 0x28, | 289 | pm8001_mw32(address, 0x28, |
255 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3); | 290 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); |
256 | pm8001_mw32(address, 0x2C, | 291 | pm8001_mw32(address, 0x2C, |
257 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7); | 292 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); |
258 | pm8001_mw32(address, 0x30, | 293 | pm8001_mw32(address, 0x30, |
259 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3); | 294 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); |
260 | pm8001_mw32(address, 0x34, | 295 | pm8001_mw32(address, 0x34, |
261 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7); | 296 | pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); |
262 | pm8001_mw32(address, 0x38, | 297 | pm8001_mw32(address, 0x38, |
263 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3); | 298 | pm8001_ha->main_cfg_tbl.pm8001_tbl. |
299 | outbound_tgt_ITNexus_event_pid0_3); | ||
264 | pm8001_mw32(address, 0x3C, | 300 | pm8001_mw32(address, 0x3C, |
265 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7); | 301 | pm8001_ha->main_cfg_tbl.pm8001_tbl. |
302 | outbound_tgt_ITNexus_event_pid4_7); | ||
266 | pm8001_mw32(address, 0x40, | 303 | pm8001_mw32(address, 0x40, |
267 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3); | 304 | pm8001_ha->main_cfg_tbl.pm8001_tbl. |
305 | outbound_tgt_ssp_event_pid0_3); | ||
268 | pm8001_mw32(address, 0x44, | 306 | pm8001_mw32(address, 0x44, |
269 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7); | 307 | pm8001_ha->main_cfg_tbl.pm8001_tbl. |
308 | outbound_tgt_ssp_event_pid4_7); | ||
270 | pm8001_mw32(address, 0x48, | 309 | pm8001_mw32(address, 0x48, |
271 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3); | 310 | pm8001_ha->main_cfg_tbl.pm8001_tbl. |
311 | outbound_tgt_smp_event_pid0_3); | ||
272 | pm8001_mw32(address, 0x4C, | 312 | pm8001_mw32(address, 0x4C, |
273 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7); | 313 | pm8001_ha->main_cfg_tbl.pm8001_tbl. |
314 | outbound_tgt_smp_event_pid4_7); | ||
274 | pm8001_mw32(address, 0x50, | 315 | pm8001_mw32(address, 0x50, |
275 | pm8001_ha->main_cfg_tbl.upper_event_log_addr); | 316 | pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); |
276 | pm8001_mw32(address, 0x54, | 317 | pm8001_mw32(address, 0x54, |
277 | pm8001_ha->main_cfg_tbl.lower_event_log_addr); | 318 | pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); |
278 | pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size); | 319 | pm8001_mw32(address, 0x58, |
279 | pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option); | 320 | pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); |
321 | pm8001_mw32(address, 0x5C, | ||
322 | pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); | ||
280 | pm8001_mw32(address, 0x60, | 323 | pm8001_mw32(address, 0x60, |
281 | pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr); | 324 | pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); |
282 | pm8001_mw32(address, 0x64, | 325 | pm8001_mw32(address, 0x64, |
283 | pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr); | 326 | pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); |
284 | pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size); | 327 | pm8001_mw32(address, 0x68, |
328 | pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); | ||
285 | pm8001_mw32(address, 0x6C, | 329 | pm8001_mw32(address, 0x6C, |
286 | pm8001_ha->main_cfg_tbl.iop_event_log_option); | 330 | pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); |
287 | pm8001_mw32(address, 0x70, | 331 | pm8001_mw32(address, 0x70, |
288 | pm8001_ha->main_cfg_tbl.fatal_err_interrupt); | 332 | pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); |
289 | } | 333 | } |
290 | 334 | ||
291 | /** | 335 | /** |
@@ -4706,4 +4750,3 @@ const struct pm8001_dispatch pm8001_8001_dispatch = { | |||
4706 | .set_dev_state_req = pm8001_chip_set_dev_state_req, | 4750 | .set_dev_state_req = pm8001_chip_set_dev_state_req, |
4707 | .sas_re_init_req = pm8001_chip_sas_re_initialization, | 4751 | .sas_re_init_req = pm8001_chip_sas_re_initialization, |
4708 | }; | 4752 | }; |
4709 | |||