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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/scsi/nsp32.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/scsi/nsp32.h')
-rw-r--r--drivers/scsi/nsp32.h664
1 files changed, 664 insertions, 0 deletions
diff --git a/drivers/scsi/nsp32.h b/drivers/scsi/nsp32.h
new file mode 100644
index 000000000000..5664398fa0ad
--- /dev/null
+++ b/drivers/scsi/nsp32.h
@@ -0,0 +1,664 @@
1/*
2 * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
3 * Basic data header
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#ifndef _NSP32_H
17#define _NSP32_H
18
19//#define NSP32_DEBUG 9
20
21/*
22 * VENDOR/DEVICE ID
23 */
24#define PCI_VENDOR_ID_IODATA 0x10fc
25#define PCI_VENDOR_ID_WORKBIT 0x1145
26
27#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
28#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
29#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
30#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
31#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
32#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
33#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
34#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
35#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
36
37/*
38 * MODEL
39 */
40enum {
41 MODEL_IODATA = 0,
42 MODEL_KME = 1,
43 MODEL_WORKBIT = 2,
44 MODEL_LOGITEC = 3,
45 MODEL_PCI_WORKBIT = 4,
46 MODEL_PCI_LOGITEC = 5,
47 MODEL_PCI_MELCO = 6,
48};
49
50static char * nsp32_model[] = {
51 "I-O DATA CBSC-II CardBus card",
52 "KME SCSI CardBus card",
53 "Workbit duo SCSI CardBus card",
54 "Logitec CardBus card with external ROM",
55 "Workbit / I-O DATA PCI card",
56 "Logitec PCI card with external ROM",
57 "Melco CardBus/PCI card with external ROM",
58};
59
60
61/*
62 * SCSI Generic Definitions
63 */
64#define EXTENDED_SDTR_LEN 0x03
65
66/* Little Endian */
67typedef u32 u32_le;
68typedef u16 u16_le;
69
70/*
71 * MACRO
72 */
73#define BIT(x) (1UL << (x))
74
75/*
76 * BASIC Definitions
77 */
78#ifndef TRUE
79# define TRUE 1
80#endif
81#ifndef FALSE
82# define FALSE 0
83#endif
84#define ASSERT 1
85#define NEGATE 0
86
87
88/*******************/
89/* normal register */
90/*******************/
91/*
92 * Don't access below register with Double Word:
93 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
94 */
95#define IRQ_CONTROL 0x00 /* BASE+00, W, W */
96#define IRQ_STATUS 0x00 /* BASE+00, W, R */
97# define IRQSTATUS_LATCHED_MSG BIT(0)
98# define IRQSTATUS_LATCHED_IO BIT(1)
99# define IRQSTATUS_LATCHED_CD BIT(2)
100# define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
101# define IRQSTATUS_RESELECT_OCCUER BIT(4)
102# define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
103# define IRQSTATUS_SCSIRESET_IRQ BIT(6)
104# define IRQSTATUS_TIMER_IRQ BIT(7)
105# define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
106# define IRQSTATUS_PCI_IRQ BIT(9)
107# define IRQSTATUS_BMCNTERR_IRQ BIT(10)
108# define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
109# define PCI_IRQ_MASK BIT(12)
110# define TIMER_IRQ_MASK BIT(13)
111# define FIFO_IRQ_MASK BIT(14)
112# define SCSI_IRQ_MASK BIT(15)
113# define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
114 TIMER_IRQ_MASK | \
115 FIFO_IRQ_MASK | \
116 SCSI_IRQ_MASK )
117# define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
118 IRQSTATUS_PHASE_CHANGE_IRQ | \
119 IRQSTATUS_SCSIRESET_IRQ | \
120 IRQSTATUS_TIMER_IRQ | \
121 IRQSTATUS_FIFO_SHLD_IRQ | \
122 IRQSTATUS_PCI_IRQ | \
123 IRQSTATUS_BMCNTERR_IRQ | \
124 IRQSTATUS_AUTOSCSI_IRQ )
125
126#define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
127#define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
128# define CB_MMIO_MODE BIT(0)
129# define CB_IO_MODE BIT(1)
130# define BM_TEST BIT(2)
131# define BM_TEST_DIR BIT(3)
132# define DUAL_EDGE_ENABLE BIT(4)
133# define NO_TRANSFER_TO_HOST BIT(5)
134# define TRANSFER_GO BIT(7)
135# define BLIEND_MODE BIT(8)
136# define BM_START BIT(9)
137# define ADVANCED_BM_WRITE BIT(10)
138# define BM_SINGLE_MODE BIT(11)
139# define FIFO_TRUE_FULL BIT(12)
140# define FIFO_TRUE_EMPTY BIT(13)
141# define ALL_COUNTER_CLR BIT(14)
142# define FIFOTEST BIT(15)
143
144#define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
145
146#define TIMER_SET 0x06 /* BASE+06, W, R/W */
147# define TIMER_CNT_MASK (0xff)
148# define TIMER_STOP BIT(8)
149
150#define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
151#define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
152
153#define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
154# define FIFO_REST_MASK 0x1ff
155# define FIFO_EMPTY_SHLD_FLAG BIT(14)
156# define FIFO_FULL_SHLD_FLAG BIT(15)
157
158#define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
159# define SREQSMPLRATE_RATE0 BIT(0)
160# define SREQSMPLRATE_RATE1 BIT(1)
161# define SAMPLING_ENABLE BIT(2)
162# define SMPL_40M (0) /* 40MHz: 0-100ns/period */
163# define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
164# define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
165
166#define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
167# define BUSCTL_SEL BIT(0)
168# define BUSCTL_RST BIT(1)
169# define BUSCTL_DATAOUT_ENB BIT(2)
170# define BUSCTL_ATN BIT(3)
171# define BUSCTL_ACK BIT(4)
172# define BUSCTL_BSY BIT(5)
173# define AUTODIRECTION BIT(6)
174# define ACKENB BIT(7)
175
176#define CLR_COUNTER 0x12 /* BASE+12, B, W */
177# define ACK_COUNTER_CLR BIT(0)
178# define SREQ_COUNTER_CLR BIT(1)
179# define FIFO_HOST_POINTER_CLR BIT(2)
180# define FIFO_REST_COUNT_CLR BIT(3)
181# define BM_COUNTER_CLR BIT(4)
182# define SAVED_ACK_CLR BIT(5)
183# define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
184 SREQ_COUNTER_CLR | \
185 FIFO_HOST_POINTER_CLR | \
186 FIFO_REST_COUNT_CLR | \
187 BM_COUNTER_CLR | \
188 SAVED_ACK_CLR )
189
190#define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
191# define BUSMON_MSG BIT(0)
192# define BUSMON_IO BIT(1)
193# define BUSMON_CD BIT(2)
194# define BUSMON_BSY BIT(3)
195# define BUSMON_ACK BIT(4)
196# define BUSMON_REQ BIT(5)
197# define BUSMON_SEL BIT(6)
198# define BUSMON_ATN BIT(7)
199
200#define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
201
202#define PARITY_CONTROL 0x16 /* BASE+16, B, W */
203# define PARITY_CHECK_ENABLE BIT(0)
204# define PARITY_ERROR_CLEAR BIT(1)
205#define PARITY_STATUS 0x16 /* BASE+16, B, R */
206//# define PARITY_CHECK_ENABLE BIT(0)
207# define PARITY_ERROR_NORMAL BIT(1)
208# define PARITY_ERROR_LSB BIT(1)
209# define PARITY_ERROR_MSB BIT(2)
210
211#define RESELECT_ID 0x18 /* BASE+18, B, R */
212
213#define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
214# define CLEAR_CDB_FIFO_POINTER BIT(0)
215# define AUTO_COMMAND_PHASE BIT(1)
216# define AUTOSCSI_START BIT(2)
217# define AUTOSCSI_RESTART BIT(3)
218# define AUTO_PARAMETER BIT(4)
219# define AUTO_ATN BIT(5)
220# define AUTO_MSGIN_00_OR_04 BIT(6)
221# define AUTO_MSGIN_02 BIT(7)
222# define AUTO_MSGIN_03 BIT(8)
223
224#define SET_ARBIT 0x1a /* BASE+1a, B, W */
225# define ARBIT_GO BIT(0)
226# define ARBIT_CLEAR BIT(1)
227
228#define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
229//# define ARBIT_GO BIT(0)
230# define ARBIT_WIN BIT(1)
231# define ARBIT_FAIL BIT(2)
232# define AUTO_PARAMETER_VALID BIT(3)
233# define SGT_VALID BIT(4)
234
235#define SYNC_REG 0x1c /* BASE+1c, B, R/W */
236
237#define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
238
239#define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
240#define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
241#define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
242
243#define SCAM_CONTROL 0x24 /* BASE+24, B, W */
244#define SCAM_STATUS 0x24 /* BASE+24, B, R */
245# define SCAM_MSG BIT(0)
246# define SCAM_IO BIT(1)
247# define SCAM_CD BIT(2)
248# define SCAM_BSY BIT(3)
249# define SCAM_SEL BIT(4)
250# define SCAM_XFEROK BIT(5)
251
252#define SCAM_DATA 0x26 /* BASE+26, B, R/W */
253# define SD0 BIT(0)
254# define SD1 BIT(1)
255# define SD2 BIT(2)
256# define SD3 BIT(3)
257# define SD4 BIT(4)
258# define SD5 BIT(5)
259# define SD6 BIT(6)
260# define SD7 BIT(7)
261
262#define SACK_CNT 0x28 /* BASE+28, DW, R/W */
263#define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
264
265#define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
266#define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
267#define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
268
269#define BM_CNT 0x38 /* BASE+38, DW, R/W */
270# define BM_COUNT_MASK 0x0001ffffUL
271# define SGTEND BIT(31) /* Last SGT marker */
272
273#define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
274#define WAIT_REG 0x40 /* Bi only */
275
276#define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
277# define COMMAND_PHASE BIT(0)
278# define DATA_IN_PHASE BIT(1)
279# define DATA_OUT_PHASE BIT(2)
280# define MSGOUT_PHASE BIT(3)
281# define STATUS_PHASE BIT(4)
282# define ILLEGAL_PHASE BIT(5)
283# define BUS_FREE_OCCUER BIT(6)
284# define MSG_IN_OCCUER BIT(7)
285# define MSG_OUT_OCCUER BIT(8)
286# define SELECTION_TIMEOUT BIT(9)
287# define MSGIN_00_VALID BIT(10)
288# define MSGIN_02_VALID BIT(11)
289# define MSGIN_03_VALID BIT(12)
290# define MSGIN_04_VALID BIT(13)
291# define AUTOSCSI_BUSY BIT(15)
292
293#define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
294
295#define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
296# define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
297# define MV_VALID BIT(7)
298
299#define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
300#define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
301
302#define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
303#define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
304#define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
305#define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
306
307
308/********************/
309/* indexed register */
310/********************/
311
312#define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
313# define CLOCK_2 BIT(0) /* MCLK/2 */
314# define CLOCK_4 BIT(1) /* MCLK/4 */
315# define PCICLK BIT(7) /* PCICLK (33MHz) */
316
317#define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
318# define BPWR BIT(0)
319# define SENSE BIT(1) /* Read Only */
320
321#define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
322#define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
323# define LED_ON (0)
324# define LED_OFF BIT(0)
325
326#define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
327# define IRQSELECT_RESELECT_IRQ BIT(0)
328# define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
329# define IRQSELECT_SCSIRESET_IRQ BIT(2)
330# define IRQSELECT_TIMER_IRQ BIT(3)
331# define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
332# define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
333# define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
334# define IRQSELECT_SERR_IRQ BIT(7)
335# define IRQSELECT_PERR_IRQ BIT(8)
336# define IRQSELECT_BMCNTERR_IRQ BIT(9)
337# define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
338
339#define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
340# define OLD_MSG BIT(0)
341# define OLD_IO BIT(1)
342# define OLD_CD BIT(2)
343# define OLD_BUSY BIT(3)
344
345#define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
346#define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
347
348#define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
349# define ROM_WRITE_ENB BIT(0)
350# define IO_ACCESS_ENB BIT(1)
351# define ROM_ADR_CLEAR BIT(2)
352
353#define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
354
355#define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
356
357#define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
358# define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
359# define OEM1 BIT(2) /* OEM select */
360# define OPTB BIT(3) /* KME mode select */
361# define OPTC BIT(4) /* KME mode select */
362# define OPTD BIT(5) /* KME mode select */
363# define OPTE BIT(6) /* KME mode select */
364# define OPTF BIT(7) /* Power management */
365
366#define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
367#define MISC_RD 0x0c
368# define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
369# define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
370# define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
371# define DELAYED_BMSTART BIT(3)
372# define MASTER_TERMINATION_SELECT BIT(4)
373# define BMREQ_NEGATE_TIMING_SEL BIT(5)
374# define AUTOSEL_TIMING_SEL BIT(6)
375# define MISC_MABORT_MASK BIT(7)
376# define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
377
378#define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
379# define BM_CYCLE0 BIT(0)
380# define BM_CYCLE1 BIT(1)
381# define BM_FRAME_ASSERT_TIMING BIT(2)
382# define BM_IRDY_ASSERT_TIMING BIT(3)
383# define BM_SINGLE_BUS_MASTER BIT(4)
384# define MEMRD_CMD0 BIT(5)
385# define SGT_AUTO_PARA_MEMED_CMD BIT(6)
386# define MEMRD_CMD1 BIT(7)
387
388
389#define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
390# define SREQ_EDGH_SELECT BIT(0)
391
392#define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
393# define REQCNT_UP BIT(0)
394# define ACKCNT_UP BIT(1)
395# define BMADR_UP BIT(4)
396# define BMCNT_UP BIT(5)
397# define SGT_CNT_UP BIT(7)
398
399#define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
400#define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
401#define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
402#define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
403#define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
404
405#define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
406# define SCL BIT(0)
407# define ENA BIT(1)
408# define SDA BIT(2)
409
410#define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
411#define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
412#define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
413#define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
414#define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
415#define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
416#define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
417#define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
418#define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
419#define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
420#define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
421#define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
422#define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
423#define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
424
425
426/*
427 * Useful Bus Monitor status combinations.
428 */
429#define BUSMON_BUS_FREE 0
430#define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
431#define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
432#define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
433#define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
434#define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
435#define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
436#define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
437#define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
438
439#define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
440#define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
441#define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
442#define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
443#define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
444#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
445#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
446
447
448/************************************************************************
449 * structure for DMA/Scatter Gather list
450 */
451#define NSP32_SG_SIZE SG_ALL
452
453typedef struct _nsp32_sgtable {
454 /* values must be little endian */
455 u32_le addr; /* transfer address */
456 u32_le len; /* transfer length. BIT(31) is for SGT_END mark */
457} __attribute__ ((packed)) nsp32_sgtable;
458
459typedef struct _nsp32_sglun {
460 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
461} __attribute__ ((packed)) nsp32_sglun;
462#define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
463
464/* Auto parameter mode memory map. */
465/* All values must be little endian. */
466typedef struct _nsp32_autoparam {
467 u8 cdb[4 * 0x10]; /* SCSI Command */
468 u32_le msgout; /* outgoing messages */
469 u8 syncreg; /* sync register value */
470 u8 ackwidth; /* ack width register value */
471 u8 target_id; /* target/host device id */
472 u8 sample_reg; /* hazard killer sampling rate */
473 u16_le command_control; /* command control register */
474 u16_le transfer_control; /* transfer control register */
475 u32_le sgt_pointer; /* SG table physical address for DMA */
476 u32_le dummy[2];
477} __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
478
479/*
480 * host data structure
481 */
482/* message in/out buffer */
483#define MSGOUTBUF_MAX 20
484#define MSGINBUF_MAX 20
485
486/* flag for trans_method */
487#define NSP32_TRANSFER_BUSMASTER BIT(0)
488#define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
489#define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
490
491
492/*
493 * structure for connected LUN dynamic data
494 *
495 * Note: Currently tagged queuing is disabled, each nsp32_lunt holds
496 * one SCSI command and one state.
497 */
498#define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
499#define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
500
501typedef struct _nsp32_lunt {
502 struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */
503 unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
504 int msgin03; /* auto msg in 03 flag */
505 unsigned int sg_num; /* Total number of SG entries */
506 int cur_entry; /* Current SG entry number */
507 nsp32_sglun *sglun; /* sg table per lun */
508 dma_addr_t sglun_paddr; /* sglun physical address */
509} nsp32_lunt;
510
511
512/*
513 * SCSI TARGET/LUN definition
514 */
515#define NSP32_HOST_SCSIID 7 /* SCSI initiator is everytime defined as 7 */
516#define MAX_TARGET 8
517#define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
518
519
520typedef struct _nsp32_sync_table {
521 unsigned char period_num; /* period number */
522 unsigned char ackwidth; /* ack width designated by period */
523 unsigned char start_period; /* search range - start period */
524 unsigned char end_period; /* search range - end period */
525 unsigned char sample_rate; /* hazard killer parameter */
526} nsp32_sync_table;
527
528
529/*
530 * structure for target device static data
531 */
532/* flag for nsp32_target.sync_flag */
533#define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
534#define SDTR_TARGET BIT(1) /* sending SDTR from target */
535#define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
536
537/* syncronous period value for nsp32_target.config_max */
538#define FAST5M 0x32
539#define FAST10M 0x19
540#define ULTRA20M 0x0c
541
542/* flag for nsp32_target.{sync_offset}, period */
543#define ASYNC_OFFSET 0 /* asynchronous transfer */
544#define SYNC_OFFSET 0xf /* synchronous transfer max offset */
545
546/* syncreg:
547 bit:07 06 05 04 03 02 01 00
548 ---PERIOD-- ---OFFSET-- */
549#define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
550
551typedef struct _nsp32_target {
552 unsigned char syncreg; /* value for SYNCREG */
553 unsigned char ackwidth; /* value for ACKWIDTH */
554 unsigned char period; /* sync period (0-255) */
555 unsigned char offset; /* sync offset (0-15) */
556 int sync_flag; /* SDTR_*, 0 */
557 int limit_entry; /* max speed limit entry designated
558 by EEPROM configuration */
559 unsigned char sample_reg; /* SREQ hazard killer register */
560} nsp32_target;
561
562typedef struct _nsp32_hw_data {
563 int IrqNumber;
564 int BaseAddress;
565 int NumAddress;
566 void __iomem *MmioAddress;
567#define NSP32_MMIO_OFFSET 0x0800
568 unsigned long MmioLength;
569
570 struct scsi_cmnd *CurrentSC;
571
572 struct pci_dev *Pci;
573 const struct pci_device_id *pci_devid;
574 struct Scsi_Host *Host;
575 spinlock_t Lock;
576
577 char info_str[100];
578
579 /* allocated memory region */
580 nsp32_sglun *sg_list; /* sglist virtuxal address */
581 dma_addr_t sg_paddr; /* physical address of hw_sg_table */
582 nsp32_autoparam *autoparam; /* auto parameter transfer region */
583 dma_addr_t auto_paddr; /* physical address of autoparam */
584 int cur_entry; /* current sgt entry */
585
586 /* target/LUN */
587 nsp32_lunt *cur_lunt; /* Current connected LUN table */
588 nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
589
590 nsp32_target *cur_target; /* Current connected SCSI ID */
591 nsp32_target target[MAX_TARGET]; /* SCSI ID */
592 int cur_id; /* Current connected target ID */
593 int cur_lun; /* Current connected target LUN */
594
595 /* behavior setting parameters */
596 int trans_method; /* transfer method flag */
597 int resettime; /* Reset time */
598 int clock; /* clock dividing flag */
599 nsp32_sync_table *synct; /* sync_table determined by clock */
600 int syncnum; /* the max number of synct element */
601
602 /* message buffer */
603 unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
604 char msgout_len; /* msgoutbuf length */
605 unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
606 char msgin_len; /* msginbuf length */
607
608} nsp32_hw_data;
609
610/*
611 * TIME definition
612 */
613#define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
614 minimum is 25us) */
615#define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
616 (25.6us/1unit) */
617#define ARBIT_TIMEOUT_TIME 100 /* 100us */
618#define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
619 or negation, 10000us == 10ms */
620
621/**************************************************************************
622 * Compatibility functions
623 */
624
625/* for Kernel 2.4 */
626#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
627# define scsi_register_host(template) scsi_register_module(MODULE_SCSI_HA, template)
628# define scsi_unregister_host(template) scsi_unregister_module(MODULE_SCSI_HA, template)
629# define scsi_host_put(host) scsi_unregister(host)
630# define pci_name(pci_dev) ((pci_dev)->slot_name)
631
632typedef void irqreturn_t;
633# define IRQ_NONE /* */
634# define IRQ_HANDLED /* */
635# define IRQ_RETVAL(x) /* */
636
637/* This is ad-hoc version of scsi_host_get_next() */
638static inline struct Scsi_Host *scsi_host_get_next(struct Scsi_Host *host)
639{
640 if (host == NULL) {
641 return scsi_hostlist;
642 } else {
643 return host->next;
644 }
645}
646
647/* This is ad-hoc version of scsi_host_hn_get() */
648static inline struct Scsi_Host *scsi_host_hn_get(unsigned short hostno)
649{
650 struct Scsi_Host *host;
651
652 for (host = scsi_host_get_next(NULL); host != NULL;
653 host = scsi_host_get_next(host)) {
654 if (host->host_no == hostno) {
655 break;
656 }
657 }
658
659 return host;
660}
661#endif
662
663#endif /* _NSP32_H */
664/* end */