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authorAndy Yan <ayan@marvell.com>2009-05-08 17:46:40 -0400
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2009-05-20 18:21:12 -0400
commit20b09c2992fefbe78f8cede7b404fb143a413c52 (patch)
treec7e2368e4dd3f38b66db95fa4982ef009e2df00a /drivers/scsi/mvsas/mv_chips.h
parentdd4969a892ea522ecf9d7d826ba1531ce044d46f (diff)
[SCSI] mvsas: add support for 94xx; layout change; bug fixes
This version contains following main changes - Switch to new layout to support more types of ASIC. - SSP TMF supported and related Error Handing enhanced. - Support flash feature with delay 2*HZ when PHY changed. - Support Marvell 94xx series ASIC for 6G SAS/SATA, which has 2 88SE64xx chips but any different register description. - Support SPI flash for HBA-related configuration info. - Other patch enhanced from kernel side such as increasing PHY type [jejb: fold back in DMA_BIT_MASK changes] Signed-off-by: Ying Chu <jasonchu@marvell.com> Signed-off-by: Andy Yan <ayan@marvell.com> Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers/scsi/mvsas/mv_chips.h')
-rw-r--r--drivers/scsi/mvsas/mv_chips.h212
1 files changed, 187 insertions, 25 deletions
diff --git a/drivers/scsi/mvsas/mv_chips.h b/drivers/scsi/mvsas/mv_chips.h
index cf74b7a3f643..a67e1c4172f9 100644
--- a/drivers/scsi/mvsas/mv_chips.h
+++ b/drivers/scsi/mvsas/mv_chips.h
@@ -1,46 +1,81 @@
1/*
2 * Marvell 88SE64xx/88SE94xx register IO interface
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23*/
24
25
1#ifndef _MV_CHIPS_H_ 26#ifndef _MV_CHIPS_H_
2#define _MV_CHIPS_H_ 27#define _MV_CHIPS_H_
3 28
4#define mr32(reg) readl(regs + MVS_##reg) 29#define mr32(reg) readl(regs + reg)
5#define mw32(reg,val) writel((val), regs + MVS_##reg) 30#define mw32(reg, val) writel((val), regs + reg)
6#define mw32_f(reg,val) do { \ 31#define mw32_f(reg, val) do { \
7 writel((val), regs + MVS_##reg); \ 32 mw32(reg, val); \
8 readl(regs + MVS_##reg); \ 33 mr32(reg); \
9 } while (0) 34 } while (0)
10 35
11static inline u32 mvs_cr32(void __iomem *regs, u32 addr) 36#define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
37#define ior32(reg) inl((unsigned long)(regs + reg))
38#define iow16(reg, val) outw((unsigned long)(val, regs + reg))
39#define ior16(reg) inw((unsigned long)(regs + reg))
40#define iow8(reg, val) outb((unsigned long)(val, regs + reg))
41#define ior8(reg) inb((unsigned long)(regs + reg))
42
43static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
12{ 44{
13 mw32(CMD_ADDR, addr); 45 void __iomem *regs = mvi->regs;
14 return mr32(CMD_DATA); 46 mw32(MVS_CMD_ADDR, addr);
47 return mr32(MVS_CMD_DATA);
15} 48}
16 49
17static inline void mvs_cw32(void __iomem *regs, u32 addr, u32 val) 50static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
18{ 51{
19 mw32(CMD_ADDR, addr); 52 void __iomem *regs = mvi->regs;
20 mw32(CMD_DATA, val); 53 mw32(MVS_CMD_ADDR, addr);
54 mw32(MVS_CMD_DATA, val);
21} 55}
22 56
23static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port) 57static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
24{ 58{
25 void __iomem *regs = mvi->regs; 59 void __iomem *regs = mvi->regs;
26 return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4): 60 return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
27 mr32(P4_SER_CTLSTAT + (port - 4) * 4); 61 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
28} 62}
29 63
30static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val) 64static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
31{ 65{
32 void __iomem *regs = mvi->regs; 66 void __iomem *regs = mvi->regs;
33 if (port < 4) 67 if (port < 4)
34 mw32(P0_SER_CTLSTAT + port * 4, val); 68 mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
35 else 69 else
36 mw32(P4_SER_CTLSTAT + (port - 4) * 4, val); 70 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
37} 71}
38 72
39static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port) 73static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
74 u32 off2, u32 port)
40{ 75{
41 void __iomem *regs = mvi->regs + off; 76 void __iomem *regs = mvi->regs + off;
42 void __iomem *regs2 = mvi->regs + off2; 77 void __iomem *regs2 = mvi->regs + off2;
43 return (port < 4)?readl(regs + port * 8): 78 return (port < 4) ? readl(regs + port * 8) :
44 readl(regs2 + (port - 4) * 8); 79 readl(regs2 + (port - 4) * 8);
45} 80}
46 81
@@ -61,16 +96,19 @@ static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
61 MVS_P4_CFG_DATA, port); 96 MVS_P4_CFG_DATA, port);
62} 97}
63 98
64static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val) 99static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
100 u32 port, u32 val)
65{ 101{
66 mvs_write_port(mvi, MVS_P0_CFG_DATA, 102 mvs_write_port(mvi, MVS_P0_CFG_DATA,
67 MVS_P4_CFG_DATA, port, val); 103 MVS_P4_CFG_DATA, port, val);
68} 104}
69 105
70static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr) 106static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
107 u32 port, u32 addr)
71{ 108{
72 mvs_write_port(mvi, MVS_P0_CFG_ADDR, 109 mvs_write_port(mvi, MVS_P0_CFG_ADDR,
73 MVS_P4_CFG_ADDR, port, addr); 110 MVS_P4_CFG_ADDR, port, addr);
111 mdelay(10);
74} 112}
75 113
76static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port) 114static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
@@ -79,16 +117,19 @@ static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
79 MVS_P4_VSR_DATA, port); 117 MVS_P4_VSR_DATA, port);
80} 118}
81 119
82static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val) 120static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
121 u32 port, u32 val)
83{ 122{
84 mvs_write_port(mvi, MVS_P0_VSR_DATA, 123 mvs_write_port(mvi, MVS_P0_VSR_DATA,
85 MVS_P4_VSR_DATA, port, val); 124 MVS_P4_VSR_DATA, port, val);
86} 125}
87 126
88static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr) 127static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
128 u32 port, u32 addr)
89{ 129{
90 mvs_write_port(mvi, MVS_P0_VSR_ADDR, 130 mvs_write_port(mvi, MVS_P0_VSR_ADDR,
91 MVS_P4_VSR_ADDR, port, addr); 131 MVS_P4_VSR_ADDR, port, addr);
132 mdelay(10);
92} 133}
93 134
94static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port) 135static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
@@ -97,7 +138,8 @@ static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
97 MVS_P4_INT_STAT, port); 138 MVS_P4_INT_STAT, port);
98} 139}
99 140
100static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val) 141static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
142 u32 port, u32 val)
101{ 143{
102 mvs_write_port(mvi, MVS_P0_INT_STAT, 144 mvs_write_port(mvi, MVS_P0_INT_STAT,
103 MVS_P4_INT_STAT, port, val); 145 MVS_P4_INT_STAT, port, val);
@@ -107,12 +149,132 @@ static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
107{ 149{
108 return mvs_read_port(mvi, MVS_P0_INT_MASK, 150 return mvs_read_port(mvi, MVS_P0_INT_MASK,
109 MVS_P4_INT_MASK, port); 151 MVS_P4_INT_MASK, port);
152
110} 153}
111 154
112static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val) 155static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
156 u32 port, u32 val)
113{ 157{
114 mvs_write_port(mvi, MVS_P0_INT_MASK, 158 mvs_write_port(mvi, MVS_P0_INT_MASK,
115 MVS_P4_INT_MASK, port, val); 159 MVS_P4_INT_MASK, port, val);
116} 160}
117 161
118#endif 162static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi)
163{
164 u32 tmp;
165
166 /* workaround for SATA R-ERR, to ignore phy glitch */
167 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
168 tmp &= ~(1 << 9);
169 tmp |= (1 << 10);
170 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
171
172 /* enable retry 127 times */
173 mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
174
175 /* extend open frame timeout to max */
176 tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
177 tmp &= ~0xffff;
178 tmp |= 0x3fff;
179 mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
180
181 /* workaround for WDTIMEOUT , set to 550 ms */
182 mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
183
184 /* not to halt for different port op during wideport link change */
185 mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
186
187 /* workaround for Seagate disk not-found OOB sequence, recv
188 * COMINIT before sending out COMWAKE */
189 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
190 tmp &= 0x0000ffff;
191 tmp |= 0x00fa0000;
192 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
193
194 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
195 tmp &= 0x1fffffff;
196 tmp |= (2U << 29); /* 8 ms retry */
197 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
198}
199
200static inline void mvs_int_sata(struct mvs_info *mvi)
201{
202 u32 tmp;
203 void __iomem *regs = mvi->regs;
204 tmp = mr32(MVS_INT_STAT_SRS_0);
205 if (tmp)
206 mw32(MVS_INT_STAT_SRS_0, tmp);
207 MVS_CHIP_DISP->clear_active_cmds(mvi);
208}
209
210static inline void mvs_int_full(struct mvs_info *mvi)
211{
212 void __iomem *regs = mvi->regs;
213 u32 tmp, stat;
214 int i;
215
216 stat = mr32(MVS_INT_STAT);
217 mvs_int_rx(mvi, false);
218
219 for (i = 0; i < mvi->chip->n_phy; i++) {
220 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
221 if (tmp)
222 mvs_int_port(mvi, i, tmp);
223 }
224
225 if (stat & CINT_SRS)
226 mvs_int_sata(mvi);
227
228 mw32(MVS_INT_STAT, stat);
229}
230
231static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
232{
233 void __iomem *regs = mvi->regs;
234 mw32(MVS_TX_PROD_IDX, tx);
235}
236
237static inline u32 mvs_rx_update(struct mvs_info *mvi)
238{
239 void __iomem *regs = mvi->regs;
240 return mr32(MVS_RX_CONS_IDX);
241}
242
243static inline u32 mvs_get_prd_size(void)
244{
245 return sizeof(struct mvs_prd);
246}
247
248static inline u32 mvs_get_prd_count(void)
249{
250 return MAX_SG_ENTRY;
251}
252
253static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
254{
255 u16 link_stat, link_spd;
256 const char *spd[] = {
257 "UnKnown",
258 "2.5",
259 "5.0",
260 };
261 if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
262 return;
263
264 pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
265 link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
266 if (link_spd >= 3)
267 link_spd = 0;
268 dev_printk(KERN_INFO, mvi->dev,
269 "mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
270 (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
271 spd[link_spd]);
272}
273
274static inline u32 mvs_hw_max_link_rate(void)
275{
276 return MAX_LINK_RATE;
277}
278
279#endif /* _MV_CHIPS_H_ */
280