diff options
author | Jeff Garzik <jeff@garzik.org> | 2009-05-08 17:44:01 -0400 |
---|---|---|
committer | James Bottomley <James.Bottomley@HansenPartnership.com> | 2009-05-20 18:21:12 -0400 |
commit | dd4969a892ea522ecf9d7d826ba1531ce044d46f (patch) | |
tree | 262978c450f749b3df5cb575feeb39bc982289ae /drivers/scsi/mvsas/mv_64xx.h | |
parent | 2ad52f473bbc1aa5b33c4a329b8a359f125e19d1 (diff) |
[SCSI] mvsas: split driver into multiple files
Split mvsas driver into multiple source codes, based on the split
and function distribution found in Marvell's mvsas update.
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers/scsi/mvsas/mv_64xx.h')
-rw-r--r-- | drivers/scsi/mvsas/mv_64xx.h | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/drivers/scsi/mvsas/mv_64xx.h b/drivers/scsi/mvsas/mv_64xx.h new file mode 100644 index 000000000000..c9f399ebc926 --- /dev/null +++ b/drivers/scsi/mvsas/mv_64xx.h | |||
@@ -0,0 +1,92 @@ | |||
1 | #ifndef _MVS64XX_REG_H_ | ||
2 | #define _MVS64XX_REG_H_ | ||
3 | |||
4 | /* enhanced mode registers (BAR4) */ | ||
5 | enum hw_registers { | ||
6 | MVS_GBL_CTL = 0x04, /* global control */ | ||
7 | MVS_GBL_INT_STAT = 0x08, /* global irq status */ | ||
8 | MVS_GBL_PI = 0x0C, /* ports implemented bitmask */ | ||
9 | MVS_GBL_PORT_TYPE = 0xa0, /* port type */ | ||
10 | |||
11 | MVS_CTL = 0x100, /* SAS/SATA port configuration */ | ||
12 | MVS_PCS = 0x104, /* SAS/SATA port control/status */ | ||
13 | MVS_CMD_LIST_LO = 0x108, /* cmd list addr */ | ||
14 | MVS_CMD_LIST_HI = 0x10C, | ||
15 | MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */ | ||
16 | MVS_RX_FIS_HI = 0x114, | ||
17 | |||
18 | MVS_TX_CFG = 0x120, /* TX configuration */ | ||
19 | MVS_TX_LO = 0x124, /* TX (delivery) ring addr */ | ||
20 | MVS_TX_HI = 0x128, | ||
21 | |||
22 | MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */ | ||
23 | MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */ | ||
24 | MVS_RX_CFG = 0x134, /* RX configuration */ | ||
25 | MVS_RX_LO = 0x138, /* RX (completion) ring addr */ | ||
26 | MVS_RX_HI = 0x13C, | ||
27 | MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */ | ||
28 | |||
29 | MVS_INT_COAL = 0x148, /* Int coalescing config */ | ||
30 | MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */ | ||
31 | MVS_INT_STAT = 0x150, /* Central int status */ | ||
32 | MVS_INT_MASK = 0x154, /* Central int enable */ | ||
33 | MVS_INT_STAT_SRS = 0x158, /* SATA register set status */ | ||
34 | MVS_INT_MASK_SRS = 0x15C, | ||
35 | |||
36 | /* ports 1-3 follow after this */ | ||
37 | MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */ | ||
38 | MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */ | ||
39 | MVS_P4_INT_STAT = 0x200, /* Port 4 interrupt status */ | ||
40 | MVS_P4_INT_MASK = 0x204, /* Port 4 interrupt enable mask */ | ||
41 | |||
42 | /* ports 1-3 follow after this */ | ||
43 | MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */ | ||
44 | MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */ | ||
45 | |||
46 | MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */ | ||
47 | MVS_CMD_DATA = 0x1BC, /* Command register port (data) */ | ||
48 | |||
49 | /* ports 1-3 follow after this */ | ||
50 | MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */ | ||
51 | MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */ | ||
52 | MVS_P4_CFG_ADDR = 0x230, /* Port 4 config address */ | ||
53 | MVS_P4_CFG_DATA = 0x234, /* Port 4 config data */ | ||
54 | |||
55 | /* ports 1-3 follow after this */ | ||
56 | MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */ | ||
57 | MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */ | ||
58 | MVS_P4_VSR_ADDR = 0x250, /* port 4 VSR addr */ | ||
59 | MVS_P4_VSR_DATA = 0x254, /* port 4 VSR data */ | ||
60 | }; | ||
61 | |||
62 | enum pci_cfg_registers { | ||
63 | PCR_PHY_CTL = 0x40, | ||
64 | PCR_PHY_CTL2 = 0x90, | ||
65 | PCR_DEV_CTRL = 0xE8, | ||
66 | }; | ||
67 | |||
68 | /* SAS/SATA Vendor Specific Port Registers */ | ||
69 | enum sas_sata_vsp_regs { | ||
70 | VSR_PHY_STAT = 0x00, /* Phy Status */ | ||
71 | VSR_PHY_MODE1 = 0x01, /* phy tx */ | ||
72 | VSR_PHY_MODE2 = 0x02, /* tx scc */ | ||
73 | VSR_PHY_MODE3 = 0x03, /* pll */ | ||
74 | VSR_PHY_MODE4 = 0x04, /* VCO */ | ||
75 | VSR_PHY_MODE5 = 0x05, /* Rx */ | ||
76 | VSR_PHY_MODE6 = 0x06, /* CDR */ | ||
77 | VSR_PHY_MODE7 = 0x07, /* Impedance */ | ||
78 | VSR_PHY_MODE8 = 0x08, /* Voltage */ | ||
79 | VSR_PHY_MODE9 = 0x09, /* Test */ | ||
80 | VSR_PHY_MODE10 = 0x0A, /* Power */ | ||
81 | VSR_PHY_MODE11 = 0x0B, /* Phy Mode */ | ||
82 | VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */ | ||
83 | VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */ | ||
84 | }; | ||
85 | |||
86 | struct mvs_prd { | ||
87 | __le64 addr; /* 64-bit buffer address */ | ||
88 | __le32 reserved; | ||
89 | __le32 len; /* 16-bit length */ | ||
90 | }; | ||
91 | |||
92 | #endif | ||