diff options
author | Sreekanth Reddy <Sreekanth.Reddy@lsi.com> | 2013-02-01 11:25:43 -0500 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2013-06-24 15:43:15 -0400 |
commit | ca6832e91b5d851fca4ea8579915cd2b6c958117 (patch) | |
tree | 5838be0f88921db796462f0c460f9c52f510f79a /drivers/scsi/mpt2sas/mpt2sas_base.c | |
parent | 10ec24e4ce0356f61a12d79f84996cea3686b926 (diff) |
[SCSI] mpt2sas: Update the timing requirements for issuing a Hard Reset
Updated the mpt2sas driver code that issues hard reset to comply with the
timing requirements mentioned in MPI specifications rev V.
[jejb: checpatch fixes]
Signed-off-by: Sreekanth Reddy <Sreekanth.Reddy@lsi.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/mpt2sas/mpt2sas_base.c')
-rw-r--r-- | drivers/scsi/mpt2sas/mpt2sas_base.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/scsi/mpt2sas/mpt2sas_base.c b/drivers/scsi/mpt2sas/mpt2sas_base.c index c76b18bbacb8..8bb1fe96f21e 100644 --- a/drivers/scsi/mpt2sas/mpt2sas_base.c +++ b/drivers/scsi/mpt2sas/mpt2sas_base.c | |||
@@ -3936,11 +3936,15 @@ _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag) | |||
3936 | writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, | 3936 | writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, |
3937 | &ioc->chip->HostDiagnostic); | 3937 | &ioc->chip->HostDiagnostic); |
3938 | 3938 | ||
3939 | /* don't access any registers for 50 milliseconds */ | 3939 | /* This delay allows the chip PCIe hardware time to finish reset tasks*/ |
3940 | msleep(50); | 3940 | if (sleep_flag == CAN_SLEEP) |
3941 | msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); | ||
3942 | else | ||
3943 | mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); | ||
3941 | 3944 | ||
3942 | /* 300 second max wait */ | 3945 | /* Approximately 300 second max wait */ |
3943 | for (count = 0; count < 3000000 ; count++) { | 3946 | for (count = 0; count < (300000000 / |
3947 | MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { | ||
3944 | 3948 | ||
3945 | host_diagnostic = readl(&ioc->chip->HostDiagnostic); | 3949 | host_diagnostic = readl(&ioc->chip->HostDiagnostic); |
3946 | 3950 | ||
@@ -3949,11 +3953,13 @@ _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag) | |||
3949 | if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) | 3953 | if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) |
3950 | break; | 3954 | break; |
3951 | 3955 | ||
3952 | /* wait 100 msec */ | 3956 | /* Wait to pass the second read delay window */ |
3953 | if (sleep_flag == CAN_SLEEP) | 3957 | if (sleep_flag == CAN_SLEEP) |
3954 | msleep(1); | 3958 | msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC |
3959 | /1000); | ||
3955 | else | 3960 | else |
3956 | mdelay(1); | 3961 | mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC |
3962 | /1000); | ||
3957 | } | 3963 | } |
3958 | 3964 | ||
3959 | if (host_diagnostic & MPI2_DIAG_HCB_MODE) { | 3965 | if (host_diagnostic & MPI2_DIAG_HCB_MODE) { |