diff options
author | James Smart <james.smart@emulex.com> | 2013-01-03 15:44:00 -0500 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2013-01-29 19:32:41 -0500 |
commit | 962bc51b04b2725639c47c49404943516ac32b11 (patch) | |
tree | db534ab9510f851ac34f9e26b0d813c8a7db9b42 /drivers/scsi/lpfc/lpfc_init.c | |
parent | 8b455cf351bba1b9e46d6a1350888be9f6a289d2 (diff) |
[SCSI] lpfc 8.3.37: Provide support for FCoE protocol dual-chute (ULP) operation
Signed-off-by: James Smart <james.smart@emulex.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/lpfc/lpfc_init.c')
-rw-r--r-- | drivers/scsi/lpfc/lpfc_init.c | 72 |
1 files changed, 68 insertions, 4 deletions
diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index 5262049651ee..26ca2efa976e 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c | |||
@@ -6233,9 +6233,11 @@ lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type) | |||
6233 | phba->sli4_hba.conf_regs_memmap_p + | 6233 | phba->sli4_hba.conf_regs_memmap_p + |
6234 | LPFC_CTL_PORT_SEM_OFFSET; | 6234 | LPFC_CTL_PORT_SEM_OFFSET; |
6235 | phba->sli4_hba.RQDBregaddr = | 6235 | phba->sli4_hba.RQDBregaddr = |
6236 | phba->sli4_hba.conf_regs_memmap_p + LPFC_RQ_DOORBELL; | 6236 | phba->sli4_hba.conf_regs_memmap_p + |
6237 | LPFC_ULP0_RQ_DOORBELL; | ||
6237 | phba->sli4_hba.WQDBregaddr = | 6238 | phba->sli4_hba.WQDBregaddr = |
6238 | phba->sli4_hba.conf_regs_memmap_p + LPFC_WQ_DOORBELL; | 6239 | phba->sli4_hba.conf_regs_memmap_p + |
6240 | LPFC_ULP0_WQ_DOORBELL; | ||
6239 | phba->sli4_hba.EQCQDBregaddr = | 6241 | phba->sli4_hba.EQCQDBregaddr = |
6240 | phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL; | 6242 | phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL; |
6241 | phba->sli4_hba.MQDBregaddr = | 6243 | phba->sli4_hba.MQDBregaddr = |
@@ -6289,9 +6291,11 @@ lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf) | |||
6289 | return -ENODEV; | 6291 | return -ENODEV; |
6290 | 6292 | ||
6291 | phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + | 6293 | phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + |
6292 | vf * LPFC_VFR_PAGE_SIZE + LPFC_RQ_DOORBELL); | 6294 | vf * LPFC_VFR_PAGE_SIZE + |
6295 | LPFC_ULP0_RQ_DOORBELL); | ||
6293 | phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + | 6296 | phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + |
6294 | vf * LPFC_VFR_PAGE_SIZE + LPFC_WQ_DOORBELL); | 6297 | vf * LPFC_VFR_PAGE_SIZE + |
6298 | LPFC_ULP0_WQ_DOORBELL); | ||
6295 | phba->sli4_hba.EQCQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + | 6299 | phba->sli4_hba.EQCQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + |
6296 | vf * LPFC_VFR_PAGE_SIZE + LPFC_EQCQ_DOORBELL); | 6300 | vf * LPFC_VFR_PAGE_SIZE + LPFC_EQCQ_DOORBELL); |
6297 | phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + | 6301 | phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p + |
@@ -6987,6 +6991,19 @@ lpfc_sli4_queue_destroy(struct lpfc_hba *phba) | |||
6987 | phba->sli4_hba.fcp_wq = NULL; | 6991 | phba->sli4_hba.fcp_wq = NULL; |
6988 | } | 6992 | } |
6989 | 6993 | ||
6994 | if (phba->pci_bar0_memmap_p) { | ||
6995 | iounmap(phba->pci_bar0_memmap_p); | ||
6996 | phba->pci_bar0_memmap_p = NULL; | ||
6997 | } | ||
6998 | if (phba->pci_bar2_memmap_p) { | ||
6999 | iounmap(phba->pci_bar2_memmap_p); | ||
7000 | phba->pci_bar2_memmap_p = NULL; | ||
7001 | } | ||
7002 | if (phba->pci_bar4_memmap_p) { | ||
7003 | iounmap(phba->pci_bar4_memmap_p); | ||
7004 | phba->pci_bar4_memmap_p = NULL; | ||
7005 | } | ||
7006 | |||
6990 | /* Release FCP CQ mapping array */ | 7007 | /* Release FCP CQ mapping array */ |
6991 | if (phba->sli4_hba.fcp_cq_map != NULL) { | 7008 | if (phba->sli4_hba.fcp_cq_map != NULL) { |
6992 | kfree(phba->sli4_hba.fcp_cq_map); | 7009 | kfree(phba->sli4_hba.fcp_cq_map); |
@@ -7050,6 +7067,53 @@ lpfc_sli4_queue_setup(struct lpfc_hba *phba) | |||
7050 | int rc = -ENOMEM; | 7067 | int rc = -ENOMEM; |
7051 | int fcp_eqidx, fcp_cqidx, fcp_wqidx; | 7068 | int fcp_eqidx, fcp_cqidx, fcp_wqidx; |
7052 | int fcp_cq_index = 0; | 7069 | int fcp_cq_index = 0; |
7070 | uint32_t shdr_status, shdr_add_status; | ||
7071 | union lpfc_sli4_cfg_shdr *shdr; | ||
7072 | LPFC_MBOXQ_t *mboxq; | ||
7073 | uint32_t length; | ||
7074 | |||
7075 | /* Check for dual-ULP support */ | ||
7076 | mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); | ||
7077 | if (!mboxq) { | ||
7078 | lpfc_printf_log(phba, KERN_ERR, LOG_INIT, | ||
7079 | "3249 Unable to allocate memory for " | ||
7080 | "QUERY_FW_CFG mailbox command\n"); | ||
7081 | return -ENOMEM; | ||
7082 | } | ||
7083 | length = (sizeof(struct lpfc_mbx_query_fw_config) - | ||
7084 | sizeof(struct lpfc_sli4_cfg_mhdr)); | ||
7085 | lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON, | ||
7086 | LPFC_MBOX_OPCODE_QUERY_FW_CFG, | ||
7087 | length, LPFC_SLI4_MBX_EMBED); | ||
7088 | |||
7089 | rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL); | ||
7090 | |||
7091 | shdr = (union lpfc_sli4_cfg_shdr *) | ||
7092 | &mboxq->u.mqe.un.sli4_config.header.cfg_shdr; | ||
7093 | shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response); | ||
7094 | shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response); | ||
7095 | if (shdr_status || shdr_add_status || rc) { | ||
7096 | lpfc_printf_log(phba, KERN_ERR, LOG_INIT, | ||
7097 | "3250 QUERY_FW_CFG mailbox failed with status " | ||
7098 | "x%x add_status x%x, mbx status x%x\n", | ||
7099 | shdr_status, shdr_add_status, rc); | ||
7100 | if (rc != MBX_TIMEOUT) | ||
7101 | mempool_free(mboxq, phba->mbox_mem_pool); | ||
7102 | rc = -ENXIO; | ||
7103 | goto out_error; | ||
7104 | } | ||
7105 | |||
7106 | phba->sli4_hba.fw_func_mode = | ||
7107 | mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode; | ||
7108 | phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode; | ||
7109 | phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode; | ||
7110 | lpfc_printf_log(phba, KERN_INFO, LOG_INIT, | ||
7111 | "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, " | ||
7112 | "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode, | ||
7113 | phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode); | ||
7114 | |||
7115 | if (rc != MBX_TIMEOUT) | ||
7116 | mempool_free(mboxq, phba->mbox_mem_pool); | ||
7053 | 7117 | ||
7054 | /* | 7118 | /* |
7055 | * Set up HBA Event Queues (EQs) | 7119 | * Set up HBA Event Queues (EQs) |