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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-07 15:47:02 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-07 15:47:02 -0500
commitda40d036fd716f0efb2917076220814b1e927ae1 (patch)
tree567893573a48e2954d82421e77606034d3b32f84 /drivers/scsi/lpfc/lpfc_hw4.h
parentaa58abc20fa85328a9f048e2626c0893691ff284 (diff)
parentc32e061fa19893ce4acf95d97d5613a161f0f1b7 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6: (147 commits) [SCSI] arcmsr: fix write to device check [SCSI] lpfc: lower stack use in lpfc_fc_frame_check [SCSI] eliminate an unnecessary local variable from scsi_remove_target() [SCSI] libiscsi: use bh locking instead of irq with session lock [SCSI] libiscsi: do not take host lock in queuecommand [SCSI] be2iscsi: fix null ptr when accessing task hdr [SCSI] be2iscsi: fix gfp use in alloc_pdu [SCSI] libiscsi: add more informative failure message during iscsi scsi eh [SCSI] gdth: Add missing call to gdth_ioctl_free [SCSI] bfa: remove unused defintions and misc cleanups [SCSI] bfa: remove inactive functions [SCSI] bfa: replace bfa_assert with WARN_ON [SCSI] qla2xxx: Use sg_next to fetch next sg element while walking sg list. [SCSI] qla2xxx: Fix to avoid recursive lock failure during BSG timeout. [SCSI] qla2xxx: Remove code to not reset ISP82xx on failure. [SCSI] qla2xxx: Display mailbox register 4 during 8012 AEN for ISP82XX parts. [SCSI] qla2xxx: Don't perform a BIG_HAMMER if Get-ID (0x20) mailbox command fails on CNAs. [SCSI] qla2xxx: Remove redundant module parameter permission bits [SCSI] qla2xxx: Add sysfs node for displaying board temperature. [SCSI] qla2xxx: Code cleanup to remove unwanted comments and code. ...
Diffstat (limited to 'drivers/scsi/lpfc/lpfc_hw4.h')
-rw-r--r--drivers/scsi/lpfc/lpfc_hw4.h292
1 files changed, 218 insertions, 74 deletions
diff --git a/drivers/scsi/lpfc/lpfc_hw4.h b/drivers/scsi/lpfc/lpfc_hw4.h
index 6e4bc34e1d0d..94c1aa1136de 100644
--- a/drivers/scsi/lpfc/lpfc_hw4.h
+++ b/drivers/scsi/lpfc/lpfc_hw4.h
@@ -64,29 +64,39 @@ struct lpfc_sli_intf {
64#define lpfc_sli_intf_valid_MASK 0x00000007 64#define lpfc_sli_intf_valid_MASK 0x00000007
65#define lpfc_sli_intf_valid_WORD word0 65#define lpfc_sli_intf_valid_WORD word0
66#define LPFC_SLI_INTF_VALID 6 66#define LPFC_SLI_INTF_VALID 6
67#define lpfc_sli_intf_featurelevel2_SHIFT 24 67#define lpfc_sli_intf_sli_hint2_SHIFT 24
68#define lpfc_sli_intf_featurelevel2_MASK 0x0000001F 68#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
69#define lpfc_sli_intf_featurelevel2_WORD word0 69#define lpfc_sli_intf_sli_hint2_WORD word0
70#define lpfc_sli_intf_featurelevel1_SHIFT 16 70#define LPFC_SLI_INTF_SLI_HINT2_NONE 0
71#define lpfc_sli_intf_featurelevel1_MASK 0x000000FF 71#define lpfc_sli_intf_sli_hint1_SHIFT 16
72#define lpfc_sli_intf_featurelevel1_WORD word0 72#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
73#define LPFC_SLI_INTF_FEATURELEVEL1_1 1 73#define lpfc_sli_intf_sli_hint1_WORD word0
74#define LPFC_SLI_INTF_FEATURELEVEL1_2 2 74#define LPFC_SLI_INTF_SLI_HINT1_NONE 0
75#define LPFC_SLI_INTF_SLI_HINT1_1 1
76#define LPFC_SLI_INTF_SLI_HINT1_2 2
77#define lpfc_sli_intf_if_type_SHIFT 12
78#define lpfc_sli_intf_if_type_MASK 0x0000000F
79#define lpfc_sli_intf_if_type_WORD word0
80#define LPFC_SLI_INTF_IF_TYPE_0 0
81#define LPFC_SLI_INTF_IF_TYPE_1 1
82#define LPFC_SLI_INTF_IF_TYPE_2 2
75#define lpfc_sli_intf_sli_family_SHIFT 8 83#define lpfc_sli_intf_sli_family_SHIFT 8
76#define lpfc_sli_intf_sli_family_MASK 0x000000FF 84#define lpfc_sli_intf_sli_family_MASK 0x0000000F
77#define lpfc_sli_intf_sli_family_WORD word0 85#define lpfc_sli_intf_sli_family_WORD word0
78#define LPFC_SLI_INTF_FAMILY_BE2 0 86#define LPFC_SLI_INTF_FAMILY_BE2 0x0
79#define LPFC_SLI_INTF_FAMILY_BE3 1 87#define LPFC_SLI_INTF_FAMILY_BE3 0x1
88#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
89#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
80#define lpfc_sli_intf_slirev_SHIFT 4 90#define lpfc_sli_intf_slirev_SHIFT 4
81#define lpfc_sli_intf_slirev_MASK 0x0000000F 91#define lpfc_sli_intf_slirev_MASK 0x0000000F
82#define lpfc_sli_intf_slirev_WORD word0 92#define lpfc_sli_intf_slirev_WORD word0
83#define LPFC_SLI_INTF_REV_SLI3 3 93#define LPFC_SLI_INTF_REV_SLI3 3
84#define LPFC_SLI_INTF_REV_SLI4 4 94#define LPFC_SLI_INTF_REV_SLI4 4
85#define lpfc_sli_intf_if_type_SHIFT 0 95#define lpfc_sli_intf_func_type_SHIFT 0
86#define lpfc_sli_intf_if_type_MASK 0x00000007 96#define lpfc_sli_intf_func_type_MASK 0x00000001
87#define lpfc_sli_intf_if_type_WORD word0 97#define lpfc_sli_intf_func_type_WORD word0
88#define LPFC_SLI_INTF_IF_TYPE_0 0 98#define LPFC_SLI_INTF_IF_TYPE_PHYS 0
89#define LPFC_SLI_INTF_IF_TYPE_1 1 99#define LPFC_SLI_INTF_IF_TYPE_VIRT 1
90}; 100};
91 101
92#define LPFC_SLI4_MBX_EMBED true 102#define LPFC_SLI4_MBX_EMBED true
@@ -450,35 +460,40 @@ struct lpfc_register {
450 uint32_t word0; 460 uint32_t word0;
451}; 461};
452 462
463/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
453#define LPFC_UERR_STATUS_HI 0x00A4 464#define LPFC_UERR_STATUS_HI 0x00A4
454#define LPFC_UERR_STATUS_LO 0x00A0 465#define LPFC_UERR_STATUS_LO 0x00A0
455#define LPFC_UE_MASK_HI 0x00AC 466#define LPFC_UE_MASK_HI 0x00AC
456#define LPFC_UE_MASK_LO 0x00A8 467#define LPFC_UE_MASK_LO 0x00A8
468
469/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
457#define LPFC_SLI_INTF 0x0058 470#define LPFC_SLI_INTF 0x0058
458 471
459/* BAR0 Registers */ 472#define LPFC_SLIPORT_IF2_SMPHR 0x0400
460#define LPFC_HST_STATE 0x00AC 473#define lpfc_port_smphr_perr_SHIFT 31
461#define lpfc_hst_state_perr_SHIFT 31 474#define lpfc_port_smphr_perr_MASK 0x1
462#define lpfc_hst_state_perr_MASK 0x1 475#define lpfc_port_smphr_perr_WORD word0
463#define lpfc_hst_state_perr_WORD word0 476#define lpfc_port_smphr_sfi_SHIFT 30
464#define lpfc_hst_state_sfi_SHIFT 30 477#define lpfc_port_smphr_sfi_MASK 0x1
465#define lpfc_hst_state_sfi_MASK 0x1 478#define lpfc_port_smphr_sfi_WORD word0
466#define lpfc_hst_state_sfi_WORD word0 479#define lpfc_port_smphr_nip_SHIFT 29
467#define lpfc_hst_state_nip_SHIFT 29 480#define lpfc_port_smphr_nip_MASK 0x1
468#define lpfc_hst_state_nip_MASK 0x1 481#define lpfc_port_smphr_nip_WORD word0
469#define lpfc_hst_state_nip_WORD word0 482#define lpfc_port_smphr_ipc_SHIFT 28
470#define lpfc_hst_state_ipc_SHIFT 28 483#define lpfc_port_smphr_ipc_MASK 0x1
471#define lpfc_hst_state_ipc_MASK 0x1 484#define lpfc_port_smphr_ipc_WORD word0
472#define lpfc_hst_state_ipc_WORD word0 485#define lpfc_port_smphr_scr1_SHIFT 27
473#define lpfc_hst_state_xrom_SHIFT 27 486#define lpfc_port_smphr_scr1_MASK 0x1
474#define lpfc_hst_state_xrom_MASK 0x1 487#define lpfc_port_smphr_scr1_WORD word0
475#define lpfc_hst_state_xrom_WORD word0 488#define lpfc_port_smphr_scr2_SHIFT 26
476#define lpfc_hst_state_dl_SHIFT 26 489#define lpfc_port_smphr_scr2_MASK 0x1
477#define lpfc_hst_state_dl_MASK 0x1 490#define lpfc_port_smphr_scr2_WORD word0
478#define lpfc_hst_state_dl_WORD word0 491#define lpfc_port_smphr_host_scratch_SHIFT 16
479#define lpfc_hst_state_port_status_SHIFT 0 492#define lpfc_port_smphr_host_scratch_MASK 0xFF
480#define lpfc_hst_state_port_status_MASK 0xFFFF 493#define lpfc_port_smphr_host_scratch_WORD word0
481#define lpfc_hst_state_port_status_WORD word0 494#define lpfc_port_smphr_port_status_SHIFT 0
495#define lpfc_port_smphr_port_status_MASK 0xFFFF
496#define lpfc_port_smphr_port_status_WORD word0
482 497
483#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 498#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
484#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 499#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
@@ -511,10 +526,46 @@ struct lpfc_register {
511#define LPFC_POST_STAGE_RC_DONE 0x0B07 526#define LPFC_POST_STAGE_RC_DONE 0x0B07
512#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 527#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
513#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 528#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
514#define LPFC_POST_STAGE_ARMFW_READY 0xC000 529#define LPFC_POST_STAGE_PORT_READY 0xC000
515#define LPFC_POST_STAGE_ARMFW_UE 0xF000 530#define LPFC_POST_STAGE_PORT_UE 0xF000
531
532#define LPFC_SLIPORT_STATUS 0x0404
533#define lpfc_sliport_status_err_SHIFT 31
534#define lpfc_sliport_status_err_MASK 0x1
535#define lpfc_sliport_status_err_WORD word0
536#define lpfc_sliport_status_end_SHIFT 30
537#define lpfc_sliport_status_end_MASK 0x1
538#define lpfc_sliport_status_end_WORD word0
539#define lpfc_sliport_status_oti_SHIFT 29
540#define lpfc_sliport_status_oti_MASK 0x1
541#define lpfc_sliport_status_oti_WORD word0
542#define lpfc_sliport_status_rn_SHIFT 24
543#define lpfc_sliport_status_rn_MASK 0x1
544#define lpfc_sliport_status_rn_WORD word0
545#define lpfc_sliport_status_rdy_SHIFT 23
546#define lpfc_sliport_status_rdy_MASK 0x1
547#define lpfc_sliport_status_rdy_WORD word0
548#define MAX_IF_TYPE_2_RESETS 1000
549
550#define LPFC_SLIPORT_CNTRL 0x0408
551#define lpfc_sliport_ctrl_end_SHIFT 30
552#define lpfc_sliport_ctrl_end_MASK 0x1
553#define lpfc_sliport_ctrl_end_WORD word0
554#define LPFC_SLIPORT_LITTLE_ENDIAN 0
555#define LPFC_SLIPORT_BIG_ENDIAN 1
556#define lpfc_sliport_ctrl_ip_SHIFT 27
557#define lpfc_sliport_ctrl_ip_MASK 0x1
558#define lpfc_sliport_ctrl_ip_WORD word0
559#define LPFC_SLIPORT_INIT_PORT 1
560
561#define LPFC_SLIPORT_ERR_1 0x040C
562#define LPFC_SLIPORT_ERR_2 0x0410
563
564/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
565 * reside in BAR 2.
566 */
567#define LPFC_SLIPORT_IF0_SMPHR 0x00AC
516 568
517/* BAR1 Registers */
518#define LPFC_IMR_MASK_ALL 0xFFFFFFFF 569#define LPFC_IMR_MASK_ALL 0xFFFFFFFF
519#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 570#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
520 571
@@ -569,14 +620,21 @@ struct lpfc_register {
569#define LPFC_SLI4_INTR30 BIT30 620#define LPFC_SLI4_INTR30 BIT30
570#define LPFC_SLI4_INTR31 BIT31 621#define LPFC_SLI4_INTR31 BIT31
571 622
572/* BAR2 Registers */ 623/*
624 * The Doorbell registers defined here exist in different BAR
625 * register sets depending on the UCNA Port's reported if_type
626 * value. For UCNA ports running SLI4 and if_type 0, they reside in
627 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
628 * BAR0. The offsets are the same so the driver must account for
629 * any base address difference.
630 */
573#define LPFC_RQ_DOORBELL 0x00A0 631#define LPFC_RQ_DOORBELL 0x00A0
574#define lpfc_rq_doorbell_num_posted_SHIFT 16 632#define lpfc_rq_doorbell_num_posted_SHIFT 16
575#define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 633#define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
576#define lpfc_rq_doorbell_num_posted_WORD word0 634#define lpfc_rq_doorbell_num_posted_WORD word0
577#define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */ 635#define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */
578#define lpfc_rq_doorbell_id_SHIFT 0 636#define lpfc_rq_doorbell_id_SHIFT 0
579#define lpfc_rq_doorbell_id_MASK 0x03FF 637#define lpfc_rq_doorbell_id_MASK 0xFFFF
580#define lpfc_rq_doorbell_id_WORD word0 638#define lpfc_rq_doorbell_id_WORD word0
581 639
582#define LPFC_WQ_DOORBELL 0x0040 640#define LPFC_WQ_DOORBELL 0x0040
@@ -591,6 +649,11 @@ struct lpfc_register {
591#define lpfc_wq_doorbell_id_WORD word0 649#define lpfc_wq_doorbell_id_WORD word0
592 650
593#define LPFC_EQCQ_DOORBELL 0x0120 651#define LPFC_EQCQ_DOORBELL 0x0120
652#define lpfc_eqcq_doorbell_se_SHIFT 31
653#define lpfc_eqcq_doorbell_se_MASK 0x0001
654#define lpfc_eqcq_doorbell_se_WORD word0
655#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
656#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
594#define lpfc_eqcq_doorbell_arm_SHIFT 29 657#define lpfc_eqcq_doorbell_arm_SHIFT 29
595#define lpfc_eqcq_doorbell_arm_MASK 0x0001 658#define lpfc_eqcq_doorbell_arm_MASK 0x0001
596#define lpfc_eqcq_doorbell_arm_WORD word0 659#define lpfc_eqcq_doorbell_arm_WORD word0
@@ -628,7 +691,7 @@ struct lpfc_register {
628#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 691#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
629#define lpfc_mq_doorbell_num_posted_WORD word0 692#define lpfc_mq_doorbell_num_posted_WORD word0
630#define lpfc_mq_doorbell_id_SHIFT 0 693#define lpfc_mq_doorbell_id_SHIFT 0
631#define lpfc_mq_doorbell_id_MASK 0x03FF 694#define lpfc_mq_doorbell_id_MASK 0xFFFF
632#define lpfc_mq_doorbell_id_WORD word0 695#define lpfc_mq_doorbell_id_WORD word0
633 696
634struct lpfc_sli4_cfg_mhdr { 697struct lpfc_sli4_cfg_mhdr {
@@ -1048,12 +1111,18 @@ struct lpfc_mbx_mq_create_ext {
1048#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1111#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1049#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1112#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1050#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1113#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1051#define lpfc_mbx_mq_create_ext_async_evt_fcfste_SHIFT LPFC_TRAILER_CODE_FCOE 1114#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1052#define lpfc_mbx_mq_create_ext_async_evt_fcfste_MASK 0x00000001 1115#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1053#define lpfc_mbx_mq_create_ext_async_evt_fcfste_WORD async_evt_bmap 1116#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1054#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1117#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1055#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1118#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1056#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1119#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1120#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1121#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1122#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1123#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1124#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1125#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1057 struct mq_context context; 1126 struct mq_context context;
1058 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1127 struct dma_address page[LPFC_MAX_MQ_PAGE];
1059 } request; 1128 } request;
@@ -1307,7 +1376,7 @@ struct lpfc_mbx_query_fw_cfg {
1307#define lpfc_function_mode_dal_WORD function_mode 1376#define lpfc_function_mode_dal_WORD function_mode
1308#define lpfc_function_mode_lro_SHIFT 9 1377#define lpfc_function_mode_lro_SHIFT 9
1309#define lpfc_function_mode_lro_MASK 0x00000001 1378#define lpfc_function_mode_lro_MASK 0x00000001
1310#define lpfc_function_mode_lro_WORD function_mode9 1379#define lpfc_function_mode_lro_WORD function_mode
1311#define lpfc_function_mode_flex10_SHIFT 10 1380#define lpfc_function_mode_flex10_SHIFT 10
1312#define lpfc_function_mode_flex10_MASK 0x00000001 1381#define lpfc_function_mode_flex10_MASK 0x00000001
1313#define lpfc_function_mode_flex10_WORD function_mode 1382#define lpfc_function_mode_flex10_WORD function_mode
@@ -1358,10 +1427,16 @@ struct lpfc_mbx_init_vfi {
1358#define lpfc_init_vfi_vf_SHIFT 29 1427#define lpfc_init_vfi_vf_SHIFT 29
1359#define lpfc_init_vfi_vf_MASK 0x00000001 1428#define lpfc_init_vfi_vf_MASK 0x00000001
1360#define lpfc_init_vfi_vf_WORD word1 1429#define lpfc_init_vfi_vf_WORD word1
1430#define lpfc_init_vfi_vp_SHIFT 28
1431#define lpfc_init_vfi_vp_MASK 0x00000001
1432#define lpfc_init_vfi_vp_WORD word1
1361#define lpfc_init_vfi_vfi_SHIFT 0 1433#define lpfc_init_vfi_vfi_SHIFT 0
1362#define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1434#define lpfc_init_vfi_vfi_MASK 0x0000FFFF
1363#define lpfc_init_vfi_vfi_WORD word1 1435#define lpfc_init_vfi_vfi_WORD word1
1364 uint32_t word2; 1436 uint32_t word2;
1437#define lpfc_init_vfi_vpi_SHIFT 16
1438#define lpfc_init_vfi_vpi_MASK 0x0000FFFF
1439#define lpfc_init_vfi_vpi_WORD word2
1365#define lpfc_init_vfi_fcfi_SHIFT 0 1440#define lpfc_init_vfi_fcfi_SHIFT 0
1366#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1441#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
1367#define lpfc_init_vfi_fcfi_WORD word2 1442#define lpfc_init_vfi_fcfi_WORD word2
@@ -2069,6 +2144,8 @@ struct lpfc_mcqe {
2069#define LPFC_TRAILER_CODE_FCOE 0x2 2144#define LPFC_TRAILER_CODE_FCOE 0x2
2070#define LPFC_TRAILER_CODE_DCBX 0x3 2145#define LPFC_TRAILER_CODE_DCBX 0x3
2071#define LPFC_TRAILER_CODE_GRP5 0x5 2146#define LPFC_TRAILER_CODE_GRP5 0x5
2147#define LPFC_TRAILER_CODE_FC 0x10
2148#define LPFC_TRAILER_CODE_SLI 0x11
2072}; 2149};
2073 2150
2074struct lpfc_acqe_link { 2151struct lpfc_acqe_link {
@@ -2094,11 +2171,12 @@ struct lpfc_acqe_link {
2094#define LPFC_ASYNC_LINK_STATUS_UP 0x1 2171#define LPFC_ASYNC_LINK_STATUS_UP 0x1
2095#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 2172#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
2096#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 2173#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
2097#define lpfc_acqe_link_physical_SHIFT 0 2174#define lpfc_acqe_link_type_SHIFT 6
2098#define lpfc_acqe_link_physical_MASK 0x000000FF 2175#define lpfc_acqe_link_type_MASK 0x00000003
2099#define lpfc_acqe_link_physical_WORD word0 2176#define lpfc_acqe_link_type_WORD word0
2100#define LPFC_ASYNC_LINK_PORT_A 0x0 2177#define lpfc_acqe_link_number_SHIFT 0
2101#define LPFC_ASYNC_LINK_PORT_B 0x1 2178#define lpfc_acqe_link_number_MASK 0x0000003F
2179#define lpfc_acqe_link_number_WORD word0
2102 uint32_t word1; 2180 uint32_t word1;
2103#define lpfc_acqe_link_fault_SHIFT 0 2181#define lpfc_acqe_link_fault_SHIFT 0
2104#define lpfc_acqe_link_fault_MASK 0x000000FF 2182#define lpfc_acqe_link_fault_MASK 0x000000FF
@@ -2106,29 +2184,31 @@ struct lpfc_acqe_link {
2106#define LPFC_ASYNC_LINK_FAULT_NONE 0x0 2184#define LPFC_ASYNC_LINK_FAULT_NONE 0x0
2107#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 2185#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
2108#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 2186#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
2109#define lpfc_acqe_qos_link_speed_SHIFT 16 2187#define lpfc_acqe_logical_link_speed_SHIFT 16
2110#define lpfc_acqe_qos_link_speed_MASK 0x0000FFFF 2188#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
2111#define lpfc_acqe_qos_link_speed_WORD word1 2189#define lpfc_acqe_logical_link_speed_WORD word1
2112 uint32_t event_tag; 2190 uint32_t event_tag;
2113 uint32_t trailer; 2191 uint32_t trailer;
2192#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
2193#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
2114}; 2194};
2115 2195
2116struct lpfc_acqe_fcoe { 2196struct lpfc_acqe_fip {
2117 uint32_t index; 2197 uint32_t index;
2118 uint32_t word1; 2198 uint32_t word1;
2119#define lpfc_acqe_fcoe_fcf_count_SHIFT 0 2199#define lpfc_acqe_fip_fcf_count_SHIFT 0
2120#define lpfc_acqe_fcoe_fcf_count_MASK 0x0000FFFF 2200#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
2121#define lpfc_acqe_fcoe_fcf_count_WORD word1 2201#define lpfc_acqe_fip_fcf_count_WORD word1
2122#define lpfc_acqe_fcoe_event_type_SHIFT 16 2202#define lpfc_acqe_fip_event_type_SHIFT 16
2123#define lpfc_acqe_fcoe_event_type_MASK 0x0000FFFF 2203#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
2124#define lpfc_acqe_fcoe_event_type_WORD word1 2204#define lpfc_acqe_fip_event_type_WORD word1
2125#define LPFC_FCOE_EVENT_TYPE_NEW_FCF 0x1
2126#define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL 0x2
2127#define LPFC_FCOE_EVENT_TYPE_FCF_DEAD 0x3
2128#define LPFC_FCOE_EVENT_TYPE_CVL 0x4
2129#define LPFC_FCOE_EVENT_TYPE_FCF_PARAM_MOD 0x5
2130 uint32_t event_tag; 2205 uint32_t event_tag;
2131 uint32_t trailer; 2206 uint32_t trailer;
2207#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
2208#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
2209#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
2210#define LPFC_FIP_EVENT_TYPE_CVL 0x4
2211#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
2132}; 2212};
2133 2213
2134struct lpfc_acqe_dcbx { 2214struct lpfc_acqe_dcbx {
@@ -2140,9 +2220,12 @@ struct lpfc_acqe_dcbx {
2140 2220
2141struct lpfc_acqe_grp5 { 2221struct lpfc_acqe_grp5 {
2142 uint32_t word0; 2222 uint32_t word0;
2143#define lpfc_acqe_grp5_pport_SHIFT 0 2223#define lpfc_acqe_grp5_type_SHIFT 6
2144#define lpfc_acqe_grp5_pport_MASK 0x000000FF 2224#define lpfc_acqe_grp5_type_MASK 0x00000003
2145#define lpfc_acqe_grp5_pport_WORD word0 2225#define lpfc_acqe_grp5_type_WORD word0
2226#define lpfc_acqe_grp5_number_SHIFT 0
2227#define lpfc_acqe_grp5_number_MASK 0x0000003F
2228#define lpfc_acqe_grp5_number_WORD word0
2146 uint32_t word1; 2229 uint32_t word1;
2147#define lpfc_acqe_grp5_llink_spd_SHIFT 16 2230#define lpfc_acqe_grp5_llink_spd_SHIFT 16
2148#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 2231#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
@@ -2151,6 +2234,68 @@ struct lpfc_acqe_grp5 {
2151 uint32_t trailer; 2234 uint32_t trailer;
2152}; 2235};
2153 2236
2237struct lpfc_acqe_fc_la {
2238 uint32_t word0;
2239#define lpfc_acqe_fc_la_speed_SHIFT 24
2240#define lpfc_acqe_fc_la_speed_MASK 0x000000FF
2241#define lpfc_acqe_fc_la_speed_WORD word0
2242#define LPFC_FC_LA_SPEED_UNKOWN 0x0
2243#define LPFC_FC_LA_SPEED_1G 0x1
2244#define LPFC_FC_LA_SPEED_2G 0x2
2245#define LPFC_FC_LA_SPEED_4G 0x4
2246#define LPFC_FC_LA_SPEED_8G 0x8
2247#define LPFC_FC_LA_SPEED_10G 0xA
2248#define LPFC_FC_LA_SPEED_16G 0x10
2249#define lpfc_acqe_fc_la_topology_SHIFT 16
2250#define lpfc_acqe_fc_la_topology_MASK 0x000000FF
2251#define lpfc_acqe_fc_la_topology_WORD word0
2252#define LPFC_FC_LA_TOP_UNKOWN 0x0
2253#define LPFC_FC_LA_TOP_P2P 0x1
2254#define LPFC_FC_LA_TOP_FCAL 0x2
2255#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
2256#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
2257#define lpfc_acqe_fc_la_att_type_SHIFT 8
2258#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
2259#define lpfc_acqe_fc_la_att_type_WORD word0
2260#define LPFC_FC_LA_TYPE_LINK_UP 0x1
2261#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
2262#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
2263#define lpfc_acqe_fc_la_port_type_SHIFT 6
2264#define lpfc_acqe_fc_la_port_type_MASK 0x00000003
2265#define lpfc_acqe_fc_la_port_type_WORD word0
2266#define LPFC_LINK_TYPE_ETHERNET 0x0
2267#define LPFC_LINK_TYPE_FC 0x1
2268#define lpfc_acqe_fc_la_port_number_SHIFT 0
2269#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
2270#define lpfc_acqe_fc_la_port_number_WORD word0
2271 uint32_t word1;
2272#define lpfc_acqe_fc_la_llink_spd_SHIFT 16
2273#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
2274#define lpfc_acqe_fc_la_llink_spd_WORD word1
2275#define lpfc_acqe_fc_la_fault_SHIFT 0
2276#define lpfc_acqe_fc_la_fault_MASK 0x000000FF
2277#define lpfc_acqe_fc_la_fault_WORD word1
2278#define LPFC_FC_LA_FAULT_NONE 0x0
2279#define LPFC_FC_LA_FAULT_LOCAL 0x1
2280#define LPFC_FC_LA_FAULT_REMOTE 0x2
2281 uint32_t event_tag;
2282 uint32_t trailer;
2283#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
2284#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
2285};
2286
2287struct lpfc_acqe_sli {
2288 uint32_t event_data1;
2289 uint32_t event_data2;
2290 uint32_t reserved;
2291 uint32_t trailer;
2292#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
2293#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
2294#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
2295#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
2296#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
2297};
2298
2154/* 2299/*
2155 * Define the bootstrap mailbox (bmbx) region used to communicate 2300 * Define the bootstrap mailbox (bmbx) region used to communicate
2156 * mailbox command between the host and port. The mailbox consists 2301 * mailbox command between the host and port. The mailbox consists
@@ -2210,7 +2355,7 @@ struct wqe_common {
2210#define wqe_rcvoxid_WORD word9 2355#define wqe_rcvoxid_WORD word9
2211 uint32_t word10; 2356 uint32_t word10;
2212#define wqe_ebde_cnt_SHIFT 0 2357#define wqe_ebde_cnt_SHIFT 0
2213#define wqe_ebde_cnt_MASK 0x00000007 2358#define wqe_ebde_cnt_MASK 0x0000000f
2214#define wqe_ebde_cnt_WORD word10 2359#define wqe_ebde_cnt_WORD word10
2215#define wqe_lenloc_SHIFT 7 2360#define wqe_lenloc_SHIFT 7
2216#define wqe_lenloc_MASK 0x00000003 2361#define wqe_lenloc_MASK 0x00000003
@@ -2402,7 +2547,6 @@ struct xmit_seq64_wqe {
2402 uint32_t relative_offset; 2547 uint32_t relative_offset;
2403 struct wqe_rctl_dfctl wge_ctl; 2548 struct wqe_rctl_dfctl wge_ctl;
2404 struct wqe_common wqe_com; /* words 6-11 */ 2549 struct wqe_common wqe_com; /* words 6-11 */
2405 /* Note: word10 different REVISIT */
2406 uint32_t xmit_len; 2550 uint32_t xmit_len;
2407 uint32_t rsvd_12_15[3]; 2551 uint32_t rsvd_12_15[3];
2408}; 2552};