[SCSI] lpfc: NPIV: add SLI-3 interface

NPIV support is only available via new adapter interface extensions,
termed SLI-3. This interface changes some of the basic behaviors such
as command and response ring element sizes and data structures, as
well as a change in buffer posting.  Note: the new firmware extensions
are found only on our mid-range and enterprise 4Gig adapters - so NPIV
support is available only on these newer adapters. The latest firmware
can be downloaded from the Emulex support page.

Signed-off-by: James Smart <James.Smart@emulex.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>

1 files changed, 368 insertions, 29 deletions

diff --git a/drivers/scsi/lpfc/lpfc_hw.h b/drivers/scsi/lpfc/lpfc_hw.h
index c4be6dc00c4c..430416805e85 100644
--- a/drivers/scsi/lpfc/lpfc_hw.h
+++ b/drivers/scsi/lpfc/lpfc_hw.h
@@ -59,6 +59,11 @@
 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
 
+#define SLI2_IOCB_CMD_SIZE      32
+#define SLI2_IOCB_RSP_SIZE      32
+#define SLI3_IOCB_CMD_SIZE      128
+#define SLI3_IOCB_RSP_SIZE      64
+
 /* Common Transport structures and definitions */
 
 union CtRevisionId {
@@ -1255,6 +1260,7 @@ typedef struct {		/* FireFly BIU registers */
 #define MBX_CONFIG_FARP     0x25
 #define MBX_BEACON          0x2A
 
+#define MBX_CONFIG_HBQ      0x7C
 #define MBX_LOAD_AREA       0x81
 #define MBX_RUN_BIU_DIAG64  0x84
 #define MBX_CONFIG_PORT     0x88
@@ -1334,6 +1340,10 @@ typedef struct {		/* FireFly BIU registers */
 #define CMD_FCP_TRECEIVE64_CX   0xA1
 #define CMD_FCP_TRSP64_CX       0xA3
 
+#define CMD_IOCB_RCV_SEQ64_CX   0xB5
+#define CMD_IOCB_RCV_ELS64_CX   0xB7
+#define CMD_IOCB_RCV_CONT64_CX  0xBB
+
 #define CMD_GEN_REQUEST64_CR    0xC2
 #define CMD_GEN_REQUEST64_CX    0xC3
 
@@ -1560,6 +1570,7 @@ typedef struct {
 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
+#define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
 
 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
@@ -1817,6 +1828,13 @@ typedef struct {
                                       structure */
                 struct ulp_bde64 sp64;
         } un;
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint16_t rsvd3;
+        uint16_t vpi;
+#else   /*  __LITTLE_ENDIAN_BITFIELD */
+        uint16_t vpi;
+        uint16_t rsvd3;
+#endif
 } READ_SPARM_VAR;
 
 /* Structure for MB Command READ_STATUS (14) */
@@ -1917,11 +1935,17 @@ typedef struct {
 #ifdef __BIG_ENDIAN_BITFIELD
         uint32_t cv:1;
         uint32_t rr:1;
-        uint32_t rsvd1:29;
+        uint32_t rsvd2:2;
+        uint32_t v3req:1;
+        uint32_t v3rsp:1;
+        uint32_t rsvd1:25;
         uint32_t rv:1;
 #else   /*  __LITTLE_ENDIAN_BITFIELD */
         uint32_t rv:1;
-        uint32_t rsvd1:29;
+        uint32_t rsvd1:25;
+        uint32_t v3rsp:1;
+        uint32_t v3req:1;
+        uint32_t rsvd2:2;
         uint32_t rr:1;
         uint32_t cv:1;
 #endif
@@ -1971,8 +1995,8 @@ typedef struct {
         uint8_t sli1FwName[16];
         uint32_t sli2FwRev;
         uint8_t sli2FwName[16];
-        uint32_t rsvd2;
-        uint32_t RandomData[7];
+        uint32_t sli3Feat;
+        uint32_t RandomData[6];
 } READ_REV_VAR;
 
 /* Structure for MB Command READ_LINK_STAT (18) */
@@ -2012,6 +2036,14 @@ typedef struct {
                 struct ulp_bde64 sp64;
         } un;
 
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint16_t rsvd6;
+        uint16_t vpi;
+#else /* __LITTLE_ENDIAN_BITFIELD */
+        uint16_t vpi;
+        uint16_t rsvd6;
+#endif
+
 } REG_LOGIN_VAR;
 
 /* Word 30 contents for REG_LOGIN */
@@ -2036,9 +2068,21 @@ typedef struct {
 #ifdef __BIG_ENDIAN_BITFIELD
         uint16_t rsvd1;
         uint16_t rpi;
+        uint32_t rsvd2;
+        uint32_t rsvd3;
+        uint32_t rsvd4;
+        uint32_t rsvd5;
+        uint16_t rsvd6;
+        uint16_t vpi;
 #else   /*  __LITTLE_ENDIAN_BITFIELD */
         uint16_t rpi;
         uint16_t rsvd1;
+        uint32_t rsvd2;
+        uint32_t rsvd3;
+        uint32_t rsvd4;
+        uint32_t rsvd5;
+        uint16_t vpi;
+        uint16_t rsvd6;
 #endif
 } UNREG_LOGIN_VAR;
 
@@ -2046,6 +2090,17 @@ typedef struct {
 
 typedef struct {
         uint32_t did;
+        uint32_t rsvd2;
+        uint32_t rsvd3;
+        uint32_t rsvd4;
+        uint32_t rsvd5;
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint16_t rsvd6;
+        uint16_t vpi;
+#else
+        uint16_t vpi;
+        uint16_t rsvd6;
+#endif
 } UNREG_D_ID_VAR;
 
 /* Structure for MB Command READ_LA (21) */
@@ -2177,13 +2232,240 @@ typedef struct {
 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
 
+struct hbq_mask {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint8_t tmatch;
+        uint8_t tmask;
+        uint8_t rctlmatch;
+        uint8_t rctlmask;
+#else   /*  __LITTLE_ENDIAN */
+        uint8_t rctlmask;
+        uint8_t rctlmatch;
+        uint8_t tmask;
+        uint8_t tmatch;
+#endif
+};
+
+
+/* Structure for MB Command CONFIG_HBQ (7c) */
+
+struct config_hbq_var {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t rsvd1      :7;
+        uint32_t recvNotify :1;     /* Receive Notification */
+        uint32_t numMask    :8;     /* # Mask Entries       */
+        uint32_t profile    :8;     /* Selection Profile    */
+        uint32_t rsvd2      :8;
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t rsvd2      :8;
+        uint32_t profile    :8;     /* Selection Profile    */
+        uint32_t numMask    :8;     /* # Mask Entries       */
+        uint32_t recvNotify :1;     /* Receive Notification */
+        uint32_t rsvd1      :7;
+#endif
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t hbqId      :16;
+        uint32_t rsvd3      :12;
+        uint32_t ringMask   :4;
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t ringMask   :4;
+        uint32_t rsvd3      :12;
+        uint32_t hbqId      :16;
+#endif
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t entry_count :16;
+        uint32_t rsvd4        :8;
+        uint32_t headerLen    :8;
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t headerLen    :8;
+        uint32_t rsvd4        :8;
+        uint32_t entry_count :16;
+#endif
+
+        uint32_t hbqaddrLow;
+        uint32_t hbqaddrHigh;
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t rsvd5      :31;
+        uint32_t logEntry   :1;
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t logEntry   :1;
+        uint32_t rsvd5      :31;
+#endif
+
+        uint32_t rsvd6;    /* w7 */
+        uint32_t rsvd7;    /* w8 */
+        uint32_t rsvd8;    /* w9 */
+
+        struct hbq_mask hbqMasks[6];
+
+
+        union {
+                uint32_t allprofiles[12];
+
+                struct {
+                        #ifdef __BIG_ENDIAN_BITFIELD
+                                uint32_t        seqlenoff       :16;
+                                uint32_t        maxlen          :16;
+                        #else   /*  __LITTLE_ENDIAN */
+                                uint32_t        maxlen          :16;
+                                uint32_t        seqlenoff       :16;
+                        #endif
+                        #ifdef __BIG_ENDIAN_BITFIELD
+                                uint32_t        rsvd1           :28;
+                                uint32_t        seqlenbcnt      :4;
+                        #else   /*  __LITTLE_ENDIAN */
+                                uint32_t        seqlenbcnt      :4;
+                                uint32_t        rsvd1           :28;
+                        #endif
+                        uint32_t rsvd[10];
+                } profile2;
+
+                struct {
+                        #ifdef __BIG_ENDIAN_BITFIELD
+                                uint32_t        seqlenoff       :16;
+                                uint32_t        maxlen          :16;
+                        #else   /*  __LITTLE_ENDIAN */
+                                uint32_t        maxlen          :16;
+                                uint32_t        seqlenoff       :16;
+                        #endif
+                        #ifdef __BIG_ENDIAN_BITFIELD
+                                uint32_t        cmdcodeoff      :28;
+                                uint32_t        rsvd1           :12;
+                                uint32_t        seqlenbcnt      :4;
+                        #else   /*  __LITTLE_ENDIAN */
+                                uint32_t        seqlenbcnt      :4;
+                                uint32_t        rsvd1           :12;
+                                uint32_t        cmdcodeoff      :28;
+                        #endif
+                        uint32_t cmdmatch[8];
+
+                        uint32_t rsvd[2];
+                } profile3;
+
+                struct {
+                        #ifdef __BIG_ENDIAN_BITFIELD
+                                uint32_t        seqlenoff       :16;
+                                uint32_t        maxlen          :16;
+                        #else   /*  __LITTLE_ENDIAN */
+                                uint32_t        maxlen          :16;
+                                uint32_t        seqlenoff       :16;
+                        #endif
+                        #ifdef __BIG_ENDIAN_BITFIELD
+                                uint32_t        cmdcodeoff      :28;
+                                uint32_t        rsvd1           :12;
+                                uint32_t        seqlenbcnt      :4;
+                        #else   /*  __LITTLE_ENDIAN */
+                                uint32_t        seqlenbcnt      :4;
+                                uint32_t        rsvd1           :12;
+                                uint32_t        cmdcodeoff      :28;
+                        #endif
+                        uint32_t cmdmatch[8];
+
+                        uint32_t rsvd[2];
+                } profile5;
+
+        } profiles;
+
+};
+
+
 
 /* Structure for MB Command CONFIG_PORT (0x88) */
 typedef struct {
-        uint32_t pcbLen;
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t cBE       :  1;
+        uint32_t cET       :  1;
+        uint32_t cHpcb     :  1;
+        uint32_t cMA       :  1;
+        uint32_t sli_mode  :  4;
+        uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
+                                        * config block */
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
+                                        * config block */
+        uint32_t sli_mode  :  4;
+        uint32_t cMA       :  1;
+        uint32_t cHpcb     :  1;
+        uint32_t cET       :  1;
+        uint32_t cBE       :  1;
+#endif
+
         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
-        uint32_t hbainit[5];
+        uint32_t hbainit[6];
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t rsvd      : 24;  /* Reserved                             */
+        uint32_t cmv       :  1;  /* Configure Max VPIs                   */
+        uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
+        uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
+        uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
+        uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
+        uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
+        uint32_t cmx       :  1;  /* Configure Max XRIs                   */
+        uint32_t cmr       :  1;  /* Configure Max RPIs                   */
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t cmr       :  1;  /* Configure Max RPIs                   */
+        uint32_t cmx       :  1;  /* Configure Max XRIs                   */
+        uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
+        uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
+        uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
+        uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
+        uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
+        uint32_t cmv       :  1;  /* Configure Max VPIs                   */
+        uint32_t rsvd      : 24;  /* Reserved                             */
+#endif
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t rsvd2     : 24;  /* Reserved                             */
+        uint32_t gmv       :  1;  /* Grant Max VPIs                       */
+        uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
+        uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
+        uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
+        uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
+        uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
+        uint32_t gmx       :  1;  /* Grant Max XRIs                       */
+        uint32_t gmr       :  1;  /* Grant Max RPIs                       */
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t gmr       :  1;  /* Grant Max RPIs                       */
+        uint32_t gmx       :  1;  /* Grant Max XRIs                       */
+        uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
+        uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
+        uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
+        uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
+        uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
+        uint32_t gmv       :  1;  /* Grant Max VPIs                       */
+        uint32_t rsvd2     : 24;  /* Reserved                             */
+#endif
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
+        uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
+        uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
+#endif
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
+        uint32_t rsvd3     : 16;  /* Max HBQs Host expect to configure    */
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t rsvd3     : 16;  /* Max HBQs Host expect to configure    */
+        uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
+#endif
+
+        uint32_t rsvd4;           /* Reserved                             */
+
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t rsvd5      : 16;  /* Reserved                             */
+        uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
+#else   /*  __LITTLE_ENDIAN */
+        uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
+        uint32_t rsvd5      : 16;  /* Reserved                             */
+#endif
+
 } CONFIG_PORT_VAR;
 
 /* SLI-2 Port Control Block */
@@ -2261,33 +2543,38 @@ typedef struct {
 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
 
 typedef union {
-        uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
-        LOAD_SM_VAR varLdSM;    /* cmd =  1 (LOAD_SM)        */
-        READ_NV_VAR varRDnvp;   /* cmd =  2 (READ_NVPARMS)   */
-        WRITE_NV_VAR varWTnvp;  /* cmd =  3 (WRITE_NVPARMS)  */
+        uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
+                                                    * feature/max ring number
+                                                    */
+        LOAD_SM_VAR varLdSM;            /* cmd =  1 (LOAD_SM)        */
+        READ_NV_VAR varRDnvp;           /* cmd =  2 (READ_NVPARMS)   */
+        WRITE_NV_VAR varWTnvp;          /* cmd =  3 (WRITE_NVPARMS)  */
         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
-        CONFIG_LINK varCfgLnk;  /* cmd =  7 (CONFIG_LINK)    */
-        PART_SLIM_VAR varSlim;  /* cmd =  8 (PART_SLIM)      */
+        CONFIG_LINK varCfgLnk;          /* cmd =  7 (CONFIG_LINK)    */
+        PART_SLIM_VAR varSlim;          /* cmd =  8 (PART_SLIM)      */
         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
-        READ_RPI_VAR varRdRPI;  /* cmd = 15 (READ_RPI(64))   */
-        READ_XRI_VAR varRdXRI;  /* cmd = 16 (READ_XRI)       */
-        READ_REV_VAR varRdRev;  /* cmd = 17 (READ_REV)       */
-        READ_LNK_VAR varRdLnk;  /* cmd = 18 (READ_LNK_STAT)  */
+        READ_RPI_VAR varRdRPI;          /* cmd = 15 (READ_RPI(64))   */
+        READ_XRI_VAR varRdXRI;          /* cmd = 16 (READ_XRI)       */
+        READ_REV_VAR varRdRev;          /* cmd = 17 (READ_REV)       */
+        READ_LNK_VAR varRdLnk;          /* cmd = 18 (READ_LNK_STAT)  */
         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
-        READ_LA_VAR varReadLA;  /* cmd = 21 (READ_LA(64))    */
+        READ_LA_VAR varReadLA;          /* cmd = 21 (READ_LA(64))    */
         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
-        DUMP_VAR varDmp;        /* Warm Start DUMP mbx cmd   */
-        UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID)   */
-        CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)  NEW_FEATURE */
-        CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT)  */
+        DUMP_VAR varDmp;                /* Warm Start DUMP mbx cmd   */
+        UNREG_D_ID_VAR varUnregDID;     /* cmd = 0x23 (UNREG_D_ID)   */
+        CONFIG_FARP_VAR varCfgFarp;     /* cmd = 0x25 (CONFIG_FARP)
+                                         * NEW_FEATURE
+                                         */
+        struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
+        CONFIG_PORT_VAR varCfgPort;     /* cmd = 0x88 (CONFIG_PORT)  */
 } MAILVARIANTS;
 
 /*
@@ -2304,16 +2591,30 @@ struct lpfc_pgp {
         __le32 rspPutInx;
 };
 
-typedef struct _SLI2_DESC {
-        struct lpfc_hgp host[MAX_RINGS];
+struct sli2_desc {
         uint32_t unused1[16];
+        struct lpfc_hgp host[MAX_RINGS];
+        struct lpfc_pgp port[MAX_RINGS];
+};
+
+struct sli3_desc {
+        struct lpfc_hgp host[MAX_RINGS];
+        uint32_t reserved[8];
+        uint32_t hbq_put[16];
+};
+
+struct sli3_pgp {
         struct lpfc_pgp port[MAX_RINGS];
-} SLI2_DESC;
+        uint32_t hbq_get[16];
+};
 
 typedef union {
-        SLI2_DESC s2;
+        struct sli2_desc s2;
+        struct sli3_desc s3;
+        struct sli3_pgp  s3_pgp;
 } SLI_VAR;
 
+
 typedef struct {
 #ifdef __BIG_ENDIAN_BITFIELD
         uint16_t mbxStatus;
@@ -2617,6 +2918,23 @@ typedef struct {
         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
 } FCPT_FIELDS64;
 
+/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
+   or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
+
+struct rcv_sli3 {
+        uint32_t word8Rsvd;
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint16_t vpi;
+        uint16_t word9Rsvd;
+#else  /*  __LITTLE_ENDIAN */
+        uint16_t word9Rsvd;
+        uint16_t vpi;
+#endif
+        uint32_t word10Rsvd;
+        uint32_t acc_len;      /* accumulated length */
+        struct ulp_bde64 bde2;
+};
+
 typedef struct _IOCB {  /* IOCB structure */
         union {
                 GENERIC_RSP grsp;       /* Generic response */
@@ -2631,8 +2949,8 @@ typedef struct _IOCB {	/* IOCB structure */
 
                 /* SLI-2 structures */
 
-                struct ulp_bde64 cont64[2];     /* up to 2 64 bit continuation
-                                           bde_64s */
+                struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
+                                              * bde_64s */
                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
@@ -2693,7 +3011,16 @@ typedef struct _IOCB {	/* IOCB structure */
         uint32_t ulpXS:1;
         uint32_t ulpTimeout:8;
 #endif
+        union {
+                struct rcv_sli3 rcvsli3; /* words 8 - 15 */
+                uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
+        } unsli3;
+
+#define ulpCt_h ulpXS
+#define ulpCt_l ulpFCP2Rcvy
 
+#define IOCB_FCP           1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
+#define IOCB_IP            2    /* IOCB is used for IP ELS cmds */
 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
@@ -2724,21 +3051,33 @@ typedef struct _IOCB {	/* IOCB structure */
 
 } IOCB_t;
 
+/* Structure used for a single HBQ entry */
+struct lpfc_hbq_entry {
+        struct ulp_bde64 bde;
+        uint32_t buffer_tag;
+};
+
 
 #define SLI1_SLIM_SIZE   (4 * 1024)
 
 /* Up to 498 IOCBs will fit into 16k
  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
  */
-#define SLI2_SLIM_SIZE   (16 * 1024)
+#define SLI2_SLIM_SIZE   (64 * 1024)
 
 /* Maximum IOCBs that will fit in SLI2 slim */
 #define MAX_SLI2_IOCB    498
+#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
+                            (sizeof(MAILBOX_t) + sizeof(PCB_t)))
+
+/* HBQ entries are 4 words each = 4k */
+#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
+                             lpfc_sli_hbq_count())
 
 struct lpfc_sli2_slim {
         MAILBOX_t mbx;
         PCB_t pcb;
-        IOCB_t IOCBs[MAX_SLI2_IOCB];
+        IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
 };
 
 /*