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authorAlan Cox <alan@lxorguk.ukuu.org.uk>2007-05-21 10:06:43 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2007-05-22 12:08:56 -0400
commit72d39fea9017bbb1407620bf89dfe8d1fb658e35 (patch)
treed7c87e09fd0d59bc50c8d31df07666213fa1eeab /drivers/scsi/initio.c
parent9d399cc7feac3faf66768566e04e16c750aad25f (diff)
[SCSI] initio: Convert into a real Linux driver and update to modern style
This is a mix of a grand clean up I did and a reworking of the hotplug support by Christoph. In testing it works as well as the previous code did (that is -quite badly-) but we can now read it and as it settles in actually debug the long standing problems it shares with the old driver. Signed-off-by: Alan Cox <alan@redhat.com> From Christoph: removal of the BSD license is also fine with me, but should really get a mention in the changelog aswell. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/initio.c')
-rw-r--r--drivers/scsi/initio.c3823
1 files changed, 1833 insertions, 1990 deletions
diff --git a/drivers/scsi/initio.c b/drivers/scsi/initio.c
index 7e7635ca78f1..65ca1424954e 100644
--- a/drivers/scsi/initio.c
+++ b/drivers/scsi/initio.c
@@ -3,7 +3,8 @@
3 * 3 *
4 * Copyright (c) 1994-1998 Initio Corporation 4 * Copyright (c) 1994-1998 Initio Corporation
5 * Copyright (c) 1998 Bas Vermeulen <bvermeul@blackstar.xs4all.nl> 5 * Copyright (c) 1998 Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
6 * All rights reserved. 6 * Copyright (c) 2004 Christoph Hellwig <hch@lst.de>
7 * Copyright (c) 2007 Red Hat <alan@redhat.com>
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -19,38 +20,6 @@
19 * along with this program; see the file COPYING. If not, write to 20 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 * 22 *
22 * --------------------------------------------------------------------------
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions, and the following disclaimer,
29 * without modification, immediately at the beginning of the file.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution.
33 * 3. The name of the author may not be used to endorse or promote products
34 * derived from this software without specific prior written permission.
35 *
36 * Where this Software is combined with software released under the terms of
37 * the GNU General Public License ("GPL") and the terms of the GPL would require the
38 * combined work to also be released under the terms of the GPL, the terms
39 * and conditions of this License will apply in addition to those of the
40 * GPL with the exception of any terms or conditions of this License that
41 * conflict with, or are expressly prohibited by, the GPL.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
44 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
47 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
49 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 * SUCH DAMAGE.
54 * 23 *
55 ************************************************************************* 24 *************************************************************************
56 * 25 *
@@ -70,14 +39,14 @@
70 * - Fix memory allocation problem 39 * - Fix memory allocation problem
71 * 03/04/98 hc - v1.01l 40 * 03/04/98 hc - v1.01l
72 * - Fix tape rewind which will hang the system problem 41 * - Fix tape rewind which will hang the system problem
73 * - Set can_queue to tul_num_scb 42 * - Set can_queue to initio_num_scb
74 * 06/25/98 hc - v1.01m 43 * 06/25/98 hc - v1.01m
75 * - Get it work for kernel version >= 2.1.75 44 * - Get it work for kernel version >= 2.1.75
76 * - Dynamic assign SCSI bus reset holding time in init_tulip() 45 * - Dynamic assign SCSI bus reset holding time in initio_init()
77 * 07/02/98 hc - v1.01n 46 * 07/02/98 hc - v1.01n
78 * - Support 0002134A 47 * - Support 0002134A
79 * 08/07/98 hc - v1.01o 48 * 08/07/98 hc - v1.01o
80 * - Change the tul_abort_srb routine to use scsi_done. <01> 49 * - Change the initio_abort_srb routine to use scsi_done. <01>
81 * 09/07/98 hl - v1.02 50 * 09/07/98 hl - v1.02
82 * - Change the INI9100U define and proc_dir_entry to 51 * - Change the INI9100U define and proc_dir_entry to
83 * reflect the newer Kernel 2.1.118, but the v1.o1o 52 * reflect the newer Kernel 2.1.118, but the v1.o1o
@@ -150,23 +119,13 @@
150static unsigned int i91u_debug = DEBUG_DEFAULT; 119static unsigned int i91u_debug = DEBUG_DEFAULT;
151#endif 120#endif
152 121
153#define TUL_RDWORD(x,y) (short)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) )) 122static int initio_tag_enable = 1;
154
155typedef struct PCI_ID_Struc {
156 unsigned short vendor_id;
157 unsigned short device_id;
158} PCI_ID;
159
160static int tul_num_ch = 4; /* Maximum 4 adapters */
161static int tul_num_scb;
162static int tul_tag_enable = 1;
163static SCB *tul_scb;
164 123
165#ifdef DEBUG_i91u 124#ifdef DEBUG_i91u
166static int setup_debug = 0; 125static int setup_debug = 0;
167#endif 126#endif
168 127
169static void i91uSCBPost(BYTE * pHcb, BYTE * pScb); 128static void i91uSCBPost(u8 * pHcb, u8 * pScb);
170 129
171/* PCI Devices supported by this driver */ 130/* PCI Devices supported by this driver */
172static struct pci_device_id i91u_pci_devices[] = { 131static struct pci_device_id i91u_pci_devices[] = {
@@ -184,74 +143,66 @@ MODULE_DEVICE_TABLE(pci, i91u_pci_devices);
184#define DEBUG_STATE 0 143#define DEBUG_STATE 0
185#define INT_DISC 0 144#define INT_DISC 0
186 145
187/*--- external functions --*/ 146/*--- forward references ---*/
188static void tul_se2_wait(void); 147static struct scsi_ctrl_blk *initio_find_busy_scb(struct initio_host * host, u16 tarlun);
189 148static struct scsi_ctrl_blk *initio_find_done_scb(struct initio_host * host);
190/*--- forward refrence ---*/ 149
191static SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun); 150static int tulip_main(struct initio_host * host);
192static SCB *tul_find_done_scb(HCS * pCurHcb); 151
193 152static int initio_next_state(struct initio_host * host);
194static int tulip_main(HCS * pCurHcb); 153static int initio_state_1(struct initio_host * host);
195 154static int initio_state_2(struct initio_host * host);
196static int tul_next_state(HCS * pCurHcb); 155static int initio_state_3(struct initio_host * host);
197static int tul_state_1(HCS * pCurHcb); 156static int initio_state_4(struct initio_host * host);
198static int tul_state_2(HCS * pCurHcb); 157static int initio_state_5(struct initio_host * host);
199static int tul_state_3(HCS * pCurHcb); 158static int initio_state_6(struct initio_host * host);
200static int tul_state_4(HCS * pCurHcb); 159static int initio_state_7(struct initio_host * host);
201static int tul_state_5(HCS * pCurHcb); 160static int initio_xfer_data_in(struct initio_host * host);
202static int tul_state_6(HCS * pCurHcb); 161static int initio_xfer_data_out(struct initio_host * host);
203static int tul_state_7(HCS * pCurHcb); 162static int initio_xpad_in(struct initio_host * host);
204static int tul_xfer_data_in(HCS * pCurHcb); 163static int initio_xpad_out(struct initio_host * host);
205static int tul_xfer_data_out(HCS * pCurHcb); 164static int initio_status_msg(struct initio_host * host);
206static int tul_xpad_in(HCS * pCurHcb); 165
207static int tul_xpad_out(HCS * pCurHcb); 166static int initio_msgin(struct initio_host * host);
208static int tul_status_msg(HCS * pCurHcb); 167static int initio_msgin_sync(struct initio_host * host);
209 168static int initio_msgin_accept(struct initio_host * host);
210static int tul_msgin(HCS * pCurHcb); 169static int initio_msgout_reject(struct initio_host * host);
211static int tul_msgin_sync(HCS * pCurHcb); 170static int initio_msgin_extend(struct initio_host * host);
212static int tul_msgin_accept(HCS * pCurHcb); 171
213static int tul_msgout_reject(HCS * pCurHcb); 172static int initio_msgout_ide(struct initio_host * host);
214static int tul_msgin_extend(HCS * pCurHcb); 173static int initio_msgout_abort_targ(struct initio_host * host);
215 174static int initio_msgout_abort_tag(struct initio_host * host);
216static int tul_msgout_ide(HCS * pCurHcb); 175
217static int tul_msgout_abort_targ(HCS * pCurHcb); 176static int initio_bus_device_reset(struct initio_host * host);
218static int tul_msgout_abort_tag(HCS * pCurHcb); 177static void initio_select_atn(struct initio_host * host, struct scsi_ctrl_blk * scb);
219 178static void initio_select_atn3(struct initio_host * host, struct scsi_ctrl_blk * scb);
220static int tul_bus_device_reset(HCS * pCurHcb); 179static void initio_select_atn_stop(struct initio_host * host, struct scsi_ctrl_blk * scb);
221static void tul_select_atn(HCS * pCurHcb, SCB * pCurScb); 180static int int_initio_busfree(struct initio_host * host);
222static void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb); 181static int int_initio_scsi_rst(struct initio_host * host);
223static void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb); 182static int int_initio_bad_seq(struct initio_host * host);
224static int int_tul_busfree(HCS * pCurHcb); 183static int int_initio_resel(struct initio_host * host);
225static int int_tul_scsi_rst(HCS * pCurHcb); 184static int initio_sync_done(struct initio_host * host);
226static int int_tul_bad_seq(HCS * pCurHcb); 185static int wdtr_done(struct initio_host * host);
227static int int_tul_resel(HCS * pCurHcb); 186static int wait_tulip(struct initio_host * host);
228static int tul_sync_done(HCS * pCurHcb); 187static int initio_wait_done_disc(struct initio_host * host);
229static int wdtr_done(HCS * pCurHcb); 188static int initio_wait_disc(struct initio_host * host);
230static int wait_tulip(HCS * pCurHcb); 189static void tulip_scsi(struct initio_host * host);
231static int tul_wait_done_disc(HCS * pCurHcb); 190static int initio_post_scsi_rst(struct initio_host * host);
232static int tul_wait_disc(HCS * pCurHcb); 191
233static void tulip_scsi(HCS * pCurHcb); 192static void initio_se2_ew_en(unsigned long base);
234static int tul_post_scsi_rst(HCS * pCurHcb); 193static void initio_se2_ew_ds(unsigned long base);
235 194static int initio_se2_rd_all(unsigned long base);
236static void tul_se2_ew_en(WORD CurBase); 195static void initio_se2_update_all(unsigned long base); /* setup default pattern */
237static void tul_se2_ew_ds(WORD CurBase); 196static void initio_read_eeprom(unsigned long base);
238static int tul_se2_rd_all(WORD CurBase); 197
239static void tul_se2_update_all(WORD CurBase); /* setup default pattern */ 198/* ---- INTERNAL VARIABLES ---- */
240static void tul_read_eeprom(WORD CurBase); 199
241
242 /* ---- INTERNAL VARIABLES ---- */
243static HCS tul_hcs[MAX_SUPPORTED_ADAPTERS];
244static INI_ADPT_STRUCT i91u_adpt[MAX_SUPPORTED_ADAPTERS];
245
246/*NVRAM nvram, *nvramp = &nvram; */
247static NVRAM i91unvram; 200static NVRAM i91unvram;
248static NVRAM *i91unvramp; 201static NVRAM *i91unvramp;
249 202
250 203static u8 i91udftNvRam[64] =
251
252static UCHAR i91udftNvRam[64] =
253{ 204{
254/*----------- header -----------*/ 205 /*----------- header -----------*/
255 0x25, 0xc9, /* Signature */ 206 0x25, 0xc9, /* Signature */
256 0x40, /* Size */ 207 0x40, /* Size */
257 0x01, /* Revision */ 208 0x01, /* Revision */
@@ -289,7 +240,7 @@ static UCHAR i91udftNvRam[64] =
289 0, 0}; /* - CheckSum - */ 240 0, 0}; /* - CheckSum - */
290 241
291 242
292static UCHAR tul_rate_tbl[8] = /* fast 20 */ 243static u8 initio_rate_tbl[8] = /* fast 20 */
293{ 244{
294 /* nanosecond devide by 4 */ 245 /* nanosecond devide by 4 */
295 12, /* 50ns, 20M */ 246 12, /* 50ns, 20M */
@@ -302,53 +253,17 @@ static UCHAR tul_rate_tbl[8] = /* fast 20 */
302 62 /* 250ns, 4M */ 253 62 /* 250ns, 4M */
303}; 254};
304 255
305static void tul_do_pause(unsigned amount) 256static void initio_do_pause(unsigned amount)
306{ /* Pause for amount jiffies */ 257{
258 /* Pause for amount jiffies */
307 unsigned long the_time = jiffies + amount; 259 unsigned long the_time = jiffies + amount;
308 260
309 while (time_before_eq(jiffies, the_time)); 261 while (time_before_eq(jiffies, the_time))
262 cpu_relax();
310} 263}
311 264
312/*-- forward reference --*/ 265/*-- forward reference --*/
313 266
314/*******************************************************************
315 Use memeory refresh time ~ 15us * 2
316********************************************************************/
317void tul_se2_wait(void)
318{
319#if 1
320 udelay(30);
321#else
322 UCHAR readByte;
323
324 readByte = TUL_RD(0, 0x61);
325 if ((readByte & 0x10) == 0x10) {
326 for (;;) {
327 readByte = TUL_RD(0, 0x61);
328 if ((readByte & 0x10) == 0x10)
329 break;
330 }
331 for (;;) {
332 readByte = TUL_RD(0, 0x61);
333 if ((readByte & 0x10) != 0x10)
334 break;
335 }
336 } else {
337 for (;;) {
338 readByte = TUL_RD(0, 0x61);
339 if ((readByte & 0x10) == 0x10)
340 break;
341 }
342 for (;;) {
343 readByte = TUL_RD(0, 0x61);
344 if ((readByte & 0x10) != 0x10)
345 break;
346 }
347 }
348#endif
349}
350
351
352/****************************************************************** 267/******************************************************************
353 Input: instruction for Serial E2PROM 268 Input: instruction for Serial E2PROM
354 269
@@ -379,1174 +294,1019 @@ void tul_se2_wait(void)
379 294
380 295
381******************************************************************/ 296******************************************************************/
382static void tul_se2_instr(WORD CurBase, UCHAR instr) 297
298/**
299 * initio_se2_instr - bitbang an instruction
300 * @base: Base of InitIO controller
301 * @instr: Instruction for serial E2PROM
302 *
303 * Bitbang an instruction out to the serial E2Prom
304 */
305
306static void initio_se2_instr(unsigned long base, u8 instr)
383{ 307{
384 int i; 308 int i;
385 UCHAR b; 309 u8 b;
386 310
387 TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* cs+start bit */ 311 outb(SE2CS | SE2DO, base + TUL_NVRAM); /* cs+start bit */
388 tul_se2_wait(); 312 udelay(30);
389 TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK | SE2DO); /* +CLK */ 313 outb(SE2CS | SE2CLK | SE2DO, base + TUL_NVRAM); /* +CLK */
390 tul_se2_wait(); 314 udelay(30);
391 315
392 for (i = 0; i < 8; i++) { 316 for (i = 0; i < 8; i++) {
393 if (instr & 0x80) 317 if (instr & 0x80)
394 b = SE2CS | SE2DO; /* -CLK+dataBit */ 318 b = SE2CS | SE2DO; /* -CLK+dataBit */
395 else 319 else
396 b = SE2CS; /* -CLK */ 320 b = SE2CS; /* -CLK */
397 TUL_WR(CurBase + TUL_NVRAM, b); 321 outb(b, base + TUL_NVRAM);
398 tul_se2_wait(); 322 udelay(30);
399 TUL_WR(CurBase + TUL_NVRAM, b | SE2CLK); /* +CLK */ 323 outb(b | SE2CLK, base + TUL_NVRAM); /* +CLK */
400 tul_se2_wait(); 324 udelay(30);
401 instr <<= 1; 325 instr <<= 1;
402 } 326 }
403 TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */ 327 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
404 tul_se2_wait(); 328 udelay(30);
405 return;
406} 329}
407 330
408 331
409/****************************************************************** 332/**
410 Function name : tul_se2_ew_en 333 * initio_se2_ew_en - Enable erase/write
411 Description : Enable erase/write state of serial EEPROM 334 * @base: Base address of InitIO controller
412******************************************************************/ 335 *
413void tul_se2_ew_en(WORD CurBase) 336 * Enable erase/write state of serial EEPROM
337 */
338void initio_se2_ew_en(unsigned long base)
414{ 339{
415 tul_se2_instr(CurBase, 0x30); /* EWEN */ 340 initio_se2_instr(base, 0x30); /* EWEN */
416 TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */ 341 outb(0, base + TUL_NVRAM); /* -CS */
417 tul_se2_wait(); 342 udelay(30);
418 return;
419} 343}
420 344
421 345
422/************************************************************************ 346/**
423 Disable erase/write state of serial EEPROM 347 * initio_se2_ew_ds - Disable erase/write
424*************************************************************************/ 348 * @base: Base address of InitIO controller
425void tul_se2_ew_ds(WORD CurBase) 349 *
350 * Disable erase/write state of serial EEPROM
351 */
352void initio_se2_ew_ds(unsigned long base)
426{ 353{
427 tul_se2_instr(CurBase, 0); /* EWDS */ 354 initio_se2_instr(base, 0); /* EWDS */
428 TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */ 355 outb(0, base + TUL_NVRAM); /* -CS */
429 tul_se2_wait(); 356 udelay(30);
430 return;
431} 357}
432 358
433 359
434/****************************************************************** 360/**
435 Input :address of Serial E2PROM 361 * initio_se2_rd - read E2PROM word
436 Output :value stored in Serial E2PROM 362 * @base: Base of InitIO controller
437*******************************************************************/ 363 * @addr: Address of word in E2PROM
438static USHORT tul_se2_rd(WORD CurBase, ULONG adr) 364 *
365 * Read a word from the NV E2PROM device
366 */
367static u16 initio_se2_rd(unsigned long base, u8 addr)
439{ 368{
440 UCHAR instr, readByte; 369 u8 instr, rb;
441 USHORT readWord; 370 u16 val = 0;
442 int i; 371 int i;
443 372
444 instr = (UCHAR) (adr | 0x80); 373 instr = (u8) (addr | 0x80);
445 tul_se2_instr(CurBase, instr); /* READ INSTR */ 374 initio_se2_instr(base, instr); /* READ INSTR */
446 readWord = 0;
447 375
448 for (i = 15; i >= 0; i--) { 376 for (i = 15; i >= 0; i--) {
449 TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */ 377 outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */
450 tul_se2_wait(); 378 udelay(30);
451 TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */ 379 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
452 380
453 /* sample data after the following edge of clock */ 381 /* sample data after the following edge of clock */
454 readByte = TUL_RD(CurBase, TUL_NVRAM); 382 rb = inb(base + TUL_NVRAM);
455 readByte &= SE2DI; 383 rb &= SE2DI;
456 readWord += (readByte << i); 384 val += (rb << i);
457 tul_se2_wait(); /* 6/20/95 */ 385 udelay(30); /* 6/20/95 */
458 } 386 }
459 387
460 TUL_WR(CurBase + TUL_NVRAM, 0); /* no chip select */ 388 outb(0, base + TUL_NVRAM); /* no chip select */
461 tul_se2_wait(); 389 udelay(30);
462 return readWord; 390 return val;
463} 391}
464 392
465 393/**
466/****************************************************************** 394 * initio_se2_wr - read E2PROM word
467 Input: new value in Serial E2PROM, address of Serial E2PROM 395 * @base: Base of InitIO controller
468*******************************************************************/ 396 * @addr: Address of word in E2PROM
469static void tul_se2_wr(WORD CurBase, UCHAR adr, USHORT writeWord) 397 * @val: Value to write
398 *
399 * Write a word to the NV E2PROM device. Used when recovering from
400 * a problem with the NV.
401 */
402static void initio_se2_wr(unsigned long base, u8 addr, u16 val)
470{ 403{
471 UCHAR readByte; 404 u8 rb;
472 UCHAR instr; 405 u8 instr;
473 int i; 406 int i;
474 407
475 instr = (UCHAR) (adr | 0x40); 408 instr = (u8) (addr | 0x40);
476 tul_se2_instr(CurBase, instr); /* WRITE INSTR */ 409 initio_se2_instr(base, instr); /* WRITE INSTR */
477 for (i = 15; i >= 0; i--) { 410 for (i = 15; i >= 0; i--) {
478 if (writeWord & 0x8000) 411 if (val & 0x8000)
479 TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* -CLK+dataBit 1 */ 412 outb(SE2CS | SE2DO, base + TUL_NVRAM); /* -CLK+dataBit 1 */
480 else 413 else
481 TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK+dataBit 0 */ 414 outb(SE2CS, base + TUL_NVRAM); /* -CLK+dataBit 0 */
482 tul_se2_wait(); 415 udelay(30);
483 TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */ 416 outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */
484 tul_se2_wait(); 417 udelay(30);
485 writeWord <<= 1; 418 val <<= 1;
486 } 419 }
487 TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */ 420 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
488 tul_se2_wait(); 421 udelay(30);
489 TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */ 422 outb(0, base + TUL_NVRAM); /* -CS */
490 tul_se2_wait(); 423 udelay(30);
491 424
492 TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* +CS */ 425 outb(SE2CS, base + TUL_NVRAM); /* +CS */
493 tul_se2_wait(); 426 udelay(30);
494 427
495 for (;;) { 428 for (;;) {
496 TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */ 429 outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */
497 tul_se2_wait(); 430 udelay(30);
498 TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */ 431 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
499 tul_se2_wait(); 432 udelay(30);
500 if ((readByte = TUL_RD(CurBase, TUL_NVRAM)) & SE2DI) 433 if ((rb = inb(base + TUL_NVRAM)) & SE2DI)
501 break; /* write complete */ 434 break; /* write complete */
502 } 435 }
503 TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */ 436 outb(0, base + TUL_NVRAM); /* -CS */
504 return;
505} 437}
506 438
439/**
440 * initio_se2_rd_all - read hostadapter NV configuration
441 * @base: Base address of InitIO controller
442 *
443 * Reads the E2PROM data into main memory. Ensures that the checksum
444 * and header marker are valid. Returns 1 on success -1 on error.
445 */
507 446
508/*********************************************************************** 447static int initio_se2_rd_all(unsigned long base)
509 Read SCSI H/A configuration parameters from serial EEPROM
510************************************************************************/
511int tul_se2_rd_all(WORD CurBase)
512{ 448{
513 int i; 449 int i;
514 ULONG chksum = 0; 450 u16 chksum = 0;
515 USHORT *np; 451 u16 *np;
516 452
517 i91unvramp = &i91unvram; 453 i91unvramp = &i91unvram;
518 np = (USHORT *) i91unvramp; 454 np = (u16 *) i91unvramp;
519 for (i = 0; i < 32; i++) { 455 for (i = 0; i < 32; i++)
520 *np++ = tul_se2_rd(CurBase, i); 456 *np++ = initio_se2_rd(base, i);
521 }
522 457
523/*--------------------Is signature "ini" ok ? ----------------*/ 458 /* Is signature "ini" ok ? */
524 if (i91unvramp->NVM_Signature != INI_SIGNATURE) 459 if (i91unvramp->NVM_Signature != INI_SIGNATURE)
525 return -1; 460 return -1;
526/*---------------------- Is ckecksum ok ? ----------------------*/ 461 /* Is ckecksum ok ? */
527 np = (USHORT *) i91unvramp; 462 np = (u16 *) i91unvramp;
528 for (i = 0; i < 31; i++) 463 for (i = 0; i < 31; i++)
529 chksum += *np++; 464 chksum += *np++;
530 if (i91unvramp->NVM_CheckSum != (USHORT) chksum) 465 if (i91unvramp->NVM_CheckSum != chksum)
531 return -1; 466 return -1;
532 return 1; 467 return 1;
533} 468}
534 469
535 470/**
536/*********************************************************************** 471 * initio_se2_update_all - Update E2PROM
537 Update SCSI H/A configuration parameters from serial EEPROM 472 * @base: Base of InitIO controller
538************************************************************************/ 473 *
539void tul_se2_update_all(WORD CurBase) 474 * Update the E2PROM by wrting any changes into the E2PROM
475 * chip, rewriting the checksum.
476 */
477static void initio_se2_update_all(unsigned long base)
540{ /* setup default pattern */ 478{ /* setup default pattern */
541 int i; 479 int i;
542 ULONG chksum = 0; 480 u16 chksum = 0;
543 USHORT *np, *np1; 481 u16 *np, *np1;
544 482
545 i91unvramp = &i91unvram; 483 i91unvramp = &i91unvram;
546 /* Calculate checksum first */ 484 /* Calculate checksum first */
547 np = (USHORT *) i91udftNvRam; 485 np = (u16 *) i91udftNvRam;
548 for (i = 0; i < 31; i++) 486 for (i = 0; i < 31; i++)
549 chksum += *np++; 487 chksum += *np++;
550 *np = (USHORT) chksum; 488 *np = chksum;
551 tul_se2_ew_en(CurBase); /* Enable write */ 489 initio_se2_ew_en(base); /* Enable write */
552 490
553 np = (USHORT *) i91udftNvRam; 491 np = (u16 *) i91udftNvRam;
554 np1 = (USHORT *) i91unvramp; 492 np1 = (u16 *) i91unvramp;
555 for (i = 0; i < 32; i++, np++, np1++) { 493 for (i = 0; i < 32; i++, np++, np1++) {
556 if (*np != *np1) { 494 if (*np != *np1)
557 tul_se2_wr(CurBase, i, *np); 495 initio_se2_wr(base, i, *np);
558 }
559 } 496 }
560 497 initio_se2_ew_ds(base); /* Disable write */
561 tul_se2_ew_ds(CurBase); /* Disable write */
562 return;
563} 498}
564 499
565/************************************************************************* 500/**
566 Function name : read_eeprom 501 * initio_read_eeprom - Retrieve configuration
567**************************************************************************/ 502 * @base: Base of InitIO Host Adapter
568void tul_read_eeprom(WORD CurBase) 503 *
569{ 504 * Retrieve the host adapter configuration data from E2Prom. If the
570 UCHAR gctrl; 505 * data is invalid then the defaults are used and are also restored
571 506 * into the E2PROM. This forms the access point for the SCSI driver
572 i91unvramp = &i91unvram; 507 * into the E2PROM layer, the other functions for the E2PROM are all
573/*------Enable EEProm programming ---*/ 508 * internal use.
574 gctrl = TUL_RD(CurBase, TUL_GCTRL); 509 *
575 TUL_WR(CurBase + TUL_GCTRL, gctrl | TUL_GCTRL_EEPROM_BIT); 510 * Must be called single threaded, uses a shared global area.
576 if (tul_se2_rd_all(CurBase) != 1) { 511 */
577 tul_se2_update_all(CurBase); /* setup default pattern */
578 tul_se2_rd_all(CurBase); /* load again */
579 }
580/*------ Disable EEProm programming ---*/
581 gctrl = TUL_RD(CurBase, TUL_GCTRL);
582 TUL_WR(CurBase + TUL_GCTRL, gctrl & ~TUL_GCTRL_EEPROM_BIT);
583} /* read_eeprom */
584 512
585static int Addi91u_into_Adapter_table(WORD wBIOS, WORD wBASE, BYTE bInterrupt, 513static void initio_read_eeprom(unsigned long base)
586 BYTE bBus, BYTE bDevice)
587{ 514{
588 int i, j; 515 u8 gctrl;
589 516
590 for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) { 517 i91unvramp = &i91unvram;
591 if (i91u_adpt[i].ADPT_BIOS < wBIOS) 518 /* Enable EEProm programming */
592 continue; 519 gctrl = inb(base + TUL_GCTRL);
593 if (i91u_adpt[i].ADPT_BIOS == wBIOS) { 520 outb(gctrl | TUL_GCTRL_EEPROM_BIT, base + TUL_GCTRL);
594 if (i91u_adpt[i].ADPT_BASE == wBASE) { 521 if (initio_se2_rd_all(base) != 1) {
595 if (i91u_adpt[i].ADPT_Bus != 0xFF) 522 initio_se2_update_all(base); /* setup default pattern */
596 return 1; 523 initio_se2_rd_all(base); /* load again */
597 } else if (i91u_adpt[i].ADPT_BASE < wBASE)
598 continue;
599 }
600 for (j = MAX_SUPPORTED_ADAPTERS - 1; j > i; j--) {
601 i91u_adpt[j].ADPT_BASE = i91u_adpt[j - 1].ADPT_BASE;
602 i91u_adpt[j].ADPT_INTR = i91u_adpt[j - 1].ADPT_INTR;
603 i91u_adpt[j].ADPT_BIOS = i91u_adpt[j - 1].ADPT_BIOS;
604 i91u_adpt[j].ADPT_Bus = i91u_adpt[j - 1].ADPT_Bus;
605 i91u_adpt[j].ADPT_Device = i91u_adpt[j - 1].ADPT_Device;
606 }
607 i91u_adpt[i].ADPT_BASE = wBASE;
608 i91u_adpt[i].ADPT_INTR = bInterrupt;
609 i91u_adpt[i].ADPT_BIOS = wBIOS;
610 i91u_adpt[i].ADPT_Bus = bBus;
611 i91u_adpt[i].ADPT_Device = bDevice;
612 return 0;
613 } 524 }
614 return 1; 525 /* Disable EEProm programming */
526 gctrl = inb(base + TUL_GCTRL);
527 outb(gctrl & ~TUL_GCTRL_EEPROM_BIT, base + TUL_GCTRL);
615} 528}
616 529
617static void init_i91uAdapter_table(void) 530/**
618{ 531 * initio_stop_bm - stop bus master
619 int i; 532 * @host: InitIO we are stopping
620 533 *
621 for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) { /* Initialize adapter structure */ 534 * Stop any pending DMA operation, aborting the DMA if neccessary
622 i91u_adpt[i].ADPT_BIOS = 0xffff; 535 */
623 i91u_adpt[i].ADPT_BASE = 0xffff;
624 i91u_adpt[i].ADPT_INTR = 0xff;
625 i91u_adpt[i].ADPT_Bus = 0xff;
626 i91u_adpt[i].ADPT_Device = 0xff;
627 }
628 return;
629}
630 536
631static void tul_stop_bm(HCS * pCurHcb) 537static void initio_stop_bm(struct initio_host * host)
632{ 538{
633 539
634 if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */ 540 if (inb(host->addr + TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
635 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO); 541 outb(TAX_X_ABT | TAX_X_CLR_FIFO, host->addr + TUL_XCmd);
636 /* wait Abort DMA xfer done */ 542 /* wait Abort DMA xfer done */
637 while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0); 543 while ((inb(host->addr + TUL_Int) & XABT) == 0)
544 cpu_relax();
638 } 545 }
639 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 546 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
640} 547}
641 548
642/***************************************************************************/ 549/**
643static void get_tulipPCIConfig(HCS * pCurHcb, int ch_idx) 550 * initio_reset_scsi - Reset SCSI host controller
644{ 551 * @host: InitIO host to reset
645 pCurHcb->HCS_Base = i91u_adpt[ch_idx].ADPT_BASE; /* Supply base address */ 552 * @seconds: Recovery time
646 pCurHcb->HCS_BIOS = i91u_adpt[ch_idx].ADPT_BIOS; /* Supply BIOS address */ 553 *
647 pCurHcb->HCS_Intr = i91u_adpt[ch_idx].ADPT_INTR; /* Supply interrupt line */ 554 * Perform a full reset of the SCSI subsystem.
648 return; 555 */
649}
650 556
651/***************************************************************************/ 557static int initio_reset_scsi(struct initio_host * host, int seconds)
652static int tul_reset_scsi(HCS * pCurHcb, int seconds)
653{ 558{
654 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_BUS); 559 outb(TSC_RST_BUS, host->addr + TUL_SCtrl0);
655 560
656 while (!((pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt)) & TSS_SCSIRST_INT)); 561 while (!((host->jsint = inb(host->addr + TUL_SInt)) & TSS_SCSIRST_INT))
657 /* reset tulip chip */ 562 cpu_relax();
658 563
659 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, 0); 564 /* reset tulip chip */
565 outb(0, host->addr + TUL_SSignal);
660 566
661 /* Stall for a while, wait for target's firmware ready,make it 2 sec ! */ 567 /* Stall for a while, wait for target's firmware ready,make it 2 sec ! */
662 /* SONY 5200 tape drive won't work if only stall for 1 sec */ 568 /* SONY 5200 tape drive won't work if only stall for 1 sec */
663 tul_do_pause(seconds * HZ); 569 /* FIXME: this is a very long busy wait right now */
664 570 initio_do_pause(seconds * HZ);
665 TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
666 571
667 return (SCSI_RESET_SUCCESS); 572 inb(host->addr + TUL_SInt);
573 return SCSI_RESET_SUCCESS;
668} 574}
669 575
670/***************************************************************************/ 576/**
671static int init_tulip(HCS * pCurHcb, SCB * scbp, int tul_num_scb, 577 * initio_init - set up an InitIO host adapter
672 BYTE * pbBiosAdr, int seconds) 578 * @host: InitIO host adapter
579 * @num_scbs: Number of SCBS
580 * @bios_addr: BIOS address
581 *
582 * Set up the host adapter and devices according to the configuration
583 * retrieved from the E2PROM.
584 *
585 * Locking: Calls E2PROM layer code which is not re-enterable so must
586 * run single threaded for now.
587 */
588
589static void initio_init(struct initio_host * host, u8 *bios_addr)
673{ 590{
674 int i; 591 int i;
675 BYTE *pwFlags; 592 u8 *flags;
676 BYTE *pbHeads; 593 u8 *heads;
677 SCB *pTmpScb, *pPrevScb = NULL; 594
678 595 /* Get E2Prom configuration */
679 pCurHcb->HCS_NumScbs = tul_num_scb; 596 initio_read_eeprom(host->addr);
680 pCurHcb->HCS_Semaph = 1;
681 spin_lock_init(&pCurHcb->HCS_SemaphLock);
682 pCurHcb->HCS_JSStatus0 = 0;
683 pCurHcb->HCS_Scb = scbp;
684 pCurHcb->HCS_NxtPend = scbp;
685 pCurHcb->HCS_NxtAvail = scbp;
686 for (i = 0, pTmpScb = scbp; i < tul_num_scb; i++, pTmpScb++) {
687 pTmpScb->SCB_TagId = i;
688 if (i != 0)
689 pPrevScb->SCB_NxtScb = pTmpScb;
690 pPrevScb = pTmpScb;
691 }
692 pPrevScb->SCB_NxtScb = NULL;
693 pCurHcb->HCS_ScbEnd = pTmpScb;
694 pCurHcb->HCS_FirstAvail = scbp;
695 pCurHcb->HCS_LastAvail = pPrevScb;
696 spin_lock_init(&pCurHcb->HCS_AvailLock);
697 pCurHcb->HCS_FirstPend = NULL;
698 pCurHcb->HCS_LastPend = NULL;
699 pCurHcb->HCS_FirstBusy = NULL;
700 pCurHcb->HCS_LastBusy = NULL;
701 pCurHcb->HCS_FirstDone = NULL;
702 pCurHcb->HCS_LastDone = NULL;
703 pCurHcb->HCS_ActScb = NULL;
704 pCurHcb->HCS_ActTcs = NULL;
705
706 tul_read_eeprom(pCurHcb->HCS_Base);
707/*---------- get H/A configuration -------------*/
708 if (i91unvramp->NVM_SCSIInfo[0].NVM_NumOfTarg == 8) 597 if (i91unvramp->NVM_SCSIInfo[0].NVM_NumOfTarg == 8)
709 pCurHcb->HCS_MaxTar = 8; 598 host->max_tar = 8;
710 else 599 else
711 pCurHcb->HCS_MaxTar = 16; 600 host->max_tar = 16;
712 601
713 pCurHcb->HCS_Config = i91unvramp->NVM_SCSIInfo[0].NVM_ChConfig1; 602 host->config = i91unvramp->NVM_SCSIInfo[0].NVM_ChConfig1;
714 603
715 pCurHcb->HCS_SCSI_ID = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID; 604 host->scsi_id = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID;
716 pCurHcb->HCS_IdMask = ~(1 << pCurHcb->HCS_SCSI_ID); 605 host->idmask = ~(1 << host->scsi_id);
717 606
718#ifdef CHK_PARITY 607#ifdef CHK_PARITY
719 /* Enable parity error response */ 608 /* Enable parity error response */
720 TUL_WR(pCurHcb->HCS_Base + TUL_PCMD, TUL_RD(pCurHcb->HCS_Base, TUL_PCMD) | 0x40); 609 outb(inb(host->addr + TUL_PCMD) | 0x40, host->addr + TUL_PCMD);
721#endif 610#endif
722 611
723 /* Mask all the interrupt */ 612 /* Mask all the interrupt */
724 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F); 613 outb(0x1F, host->addr + TUL_Mask);
725 614
726 tul_stop_bm(pCurHcb); 615 initio_stop_bm(host);
727 /* --- Initialize the tulip --- */ 616 /* --- Initialize the tulip --- */
728 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_CHIP); 617 outb(TSC_RST_CHIP, host->addr + TUL_SCtrl0);
729 618
730 /* program HBA's SCSI ID */ 619 /* program HBA's SCSI ID */
731 TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId, pCurHcb->HCS_SCSI_ID << 4); 620 outb(host->scsi_id << 4, host->addr + TUL_SScsiId);
732 621
733 /* Enable Initiator Mode ,phase latch,alternate sync period mode, 622 /* Enable Initiator Mode ,phase latch,alternate sync period mode,
734 disable SCSI reset */ 623 disable SCSI reset */
735 if (pCurHcb->HCS_Config & HCC_EN_PAR) 624 if (host->config & HCC_EN_PAR)
736 pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT | TSC_EN_SCSI_PAR); 625 host->sconf1 = (TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
737 else 626 else
738 pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT); 627 host->sconf1 = (TSC_INITDEFAULT);
739 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_SConf1); 628 outb(host->sconf1, host->addr + TUL_SConfig);
740 629
741 /* Enable HW reselect */ 630 /* Enable HW reselect */
742 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); 631 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1);
743 632
744 TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, 0); 633 outb(0, host->addr + TUL_SPeriod);
745 634
746 /* selection time out = 250 ms */ 635 /* selection time out = 250 ms */
747 TUL_WR(pCurHcb->HCS_Base + TUL_STimeOut, 153); 636 outb(153, host->addr + TUL_STimeOut);
748 637
749/*--------- Enable SCSI terminator -----*/ 638 /* Enable SCSI terminator */
750 TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, (pCurHcb->HCS_Config & (HCC_ACT_TERM1 | HCC_ACT_TERM2))); 639 outb((host->config & (HCC_ACT_TERM1 | HCC_ACT_TERM2)),
751 TUL_WR(pCurHcb->HCS_Base + TUL_GCTRL1, 640 host->addr + TUL_XCtrl);
752 ((pCurHcb->HCS_Config & HCC_AUTO_TERM) >> 4) | (TUL_RD(pCurHcb->HCS_Base, TUL_GCTRL1) & 0xFE)); 641 outb(((host->config & HCC_AUTO_TERM) >> 4) |
642 (inb(host->addr + TUL_GCTRL1) & 0xFE),
643 host->addr + TUL_GCTRL1);
753 644
754 for (i = 0, 645 for (i = 0,
755 pwFlags = & (i91unvramp->NVM_SCSIInfo[0].NVM_Targ0Config), 646 flags = & (i91unvramp->NVM_SCSIInfo[0].NVM_Targ0Config),
756 pbHeads = pbBiosAdr + 0x180; 647 heads = bios_addr + 0x180;
757 i < pCurHcb->HCS_MaxTar; 648 i < host->max_tar;
758 i++, pwFlags++) { 649 i++, flags++) {
759 pCurHcb->HCS_Tcs[i].TCS_Flags = *pwFlags & ~(TCF_SYNC_DONE | TCF_WDTR_DONE); 650 host->targets[i].flags = *flags & ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
760 if (pCurHcb->HCS_Tcs[i].TCS_Flags & TCF_EN_255) 651 if (host->targets[i].flags & TCF_EN_255)
761 pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63; 652 host->targets[i].drv_flags = TCF_DRV_255_63;
762 else 653 else
763 pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0; 654 host->targets[i].drv_flags = 0;
764 pCurHcb->HCS_Tcs[i].TCS_JS_Period = 0; 655 host->targets[i].js_period = 0;
765 pCurHcb->HCS_Tcs[i].TCS_SConfig0 = pCurHcb->HCS_SConf1; 656 host->targets[i].sconfig0 = host->sconf1;
766 pCurHcb->HCS_Tcs[i].TCS_DrvHead = *pbHeads++; 657 host->targets[i].heads = *heads++;
767 if (pCurHcb->HCS_Tcs[i].TCS_DrvHead == 255) 658 if (host->targets[i].heads == 255)
768 pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63; 659 host->targets[i].drv_flags = TCF_DRV_255_63;
769 else 660 else
770 pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0; 661 host->targets[i].drv_flags = 0;
771 pCurHcb->HCS_Tcs[i].TCS_DrvSector = *pbHeads++; 662 host->targets[i].sectors = *heads++;
772 pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY; 663 host->targets[i].flags &= ~TCF_BUSY;
773 pCurHcb->HCS_ActTags[i] = 0; 664 host->act_tags[i] = 0;
774 pCurHcb->HCS_MaxTags[i] = 0xFF; 665 host->max_tags[i] = 0xFF;
775 } /* for */ 666 } /* for */
776 printk("i91u: PCI Base=0x%04X, IRQ=%d, BIOS=0x%04X0, SCSI ID=%d\n", 667 printk("i91u: PCI Base=0x%04X, IRQ=%d, BIOS=0x%04X0, SCSI ID=%d\n",
777 pCurHcb->HCS_Base, pCurHcb->HCS_Intr, 668 host->addr, host->irq,
778 pCurHcb->HCS_BIOS, pCurHcb->HCS_SCSI_ID); 669 host->bios_addr, host->scsi_id);
779/*------------------- reset SCSI Bus ---------------------------*/ 670 /* Reset SCSI Bus */
780 if (pCurHcb->HCS_Config & HCC_SCSI_RESET) { 671 if (host->config & HCC_SCSI_RESET) {
781 printk("i91u: Reset SCSI Bus ... \n"); 672 printk(KERN_INFO "i91u: Reset SCSI Bus ... \n");
782 tul_reset_scsi(pCurHcb, seconds); 673 initio_reset_scsi(host, 10);
783 } 674 }
784 TUL_WR(pCurHcb->HCS_Base + TUL_SCFG1, 0x17); 675 outb(0x17, host->addr + TUL_SCFG1);
785 TUL_WR(pCurHcb->HCS_Base + TUL_SIntEnable, 0xE9); 676 outb(0xE9, host->addr + TUL_SIntEnable);
786 return (0);
787} 677}
788 678
789/***************************************************************************/ 679/**
790static SCB *tul_alloc_scb(HCS * hcsp) 680 * initio_alloc_scb - Allocate an SCB
681 * @host: InitIO host we are allocating for
682 *
683 * Walk the SCB list for the controller and allocate a free SCB if
684 * one exists.
685 */
686static struct scsi_ctrl_blk *initio_alloc_scb(struct initio_host *host)
791{ 687{
792 SCB *pTmpScb; 688 struct scsi_ctrl_blk *scb;
793 ULONG flags; 689 unsigned long flags;
794 spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags); 690
795 if ((pTmpScb = hcsp->HCS_FirstAvail) != NULL) { 691 spin_lock_irqsave(&host->avail_lock, flags);
692 if ((scb = host->first_avail) != NULL) {
796#if DEBUG_QUEUE 693#if DEBUG_QUEUE
797 printk("find scb at %08lx\n", (ULONG) pTmpScb); 694 printk("find scb at %p\n", scb);
798#endif 695#endif
799 if ((hcsp->HCS_FirstAvail = pTmpScb->SCB_NxtScb) == NULL) 696 if ((host->first_avail = scb->next) == NULL)
800 hcsp->HCS_LastAvail = NULL; 697 host->last_avail = NULL;
801 pTmpScb->SCB_NxtScb = NULL; 698 scb->next = NULL;
802 pTmpScb->SCB_Status = SCB_RENT; 699 scb->status = SCB_RENT;
803 } 700 }
804 spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags); 701 spin_unlock_irqrestore(&host->avail_lock, flags);
805 return (pTmpScb); 702 return scb;
806} 703}
807 704
808/***************************************************************************/ 705/**
809static void tul_release_scb(HCS * hcsp, SCB * scbp) 706 * initio_release_scb - Release an SCB
707 * @host: InitIO host that owns the SCB
708 * @cmnd: SCB command block being returned
709 *
710 * Return an allocated SCB to the host free list
711 */
712
713static void initio_release_scb(struct initio_host * host, struct scsi_ctrl_blk * cmnd)
810{ 714{
811 ULONG flags; 715 unsigned long flags;
812 716
813#if DEBUG_QUEUE 717#if DEBUG_QUEUE
814 printk("Release SCB %lx; ", (ULONG) scbp); 718 printk("Release SCB %p; ", cmnd);
815#endif 719#endif
816 spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags); 720 spin_lock_irqsave(&(host->avail_lock), flags);
817 scbp->SCB_Srb = NULL; 721 cmnd->srb = NULL;
818 scbp->SCB_Status = 0; 722 cmnd->status = 0;
819 scbp->SCB_NxtScb = NULL; 723 cmnd->next = NULL;
820 if (hcsp->HCS_LastAvail != NULL) { 724 if (host->last_avail != NULL) {
821 hcsp->HCS_LastAvail->SCB_NxtScb = scbp; 725 host->last_avail->next = cmnd;
822 hcsp->HCS_LastAvail = scbp; 726 host->last_avail = cmnd;
823 } else { 727 } else {
824 hcsp->HCS_FirstAvail = scbp; 728 host->first_avail = cmnd;
825 hcsp->HCS_LastAvail = scbp; 729 host->last_avail = cmnd;
826 } 730 }
827 spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags); 731 spin_unlock_irqrestore(&(host->avail_lock), flags);
828} 732}
829 733
830/***************************************************************************/ 734/***************************************************************************/
831static void tul_append_pend_scb(HCS * pCurHcb, SCB * scbp) 735static void initio_append_pend_scb(struct initio_host * host, struct scsi_ctrl_blk * scbp)
832{ 736{
833 737
834#if DEBUG_QUEUE 738#if DEBUG_QUEUE
835 printk("Append pend SCB %lx; ", (ULONG) scbp); 739 printk("Append pend SCB %p; ", scbp);
836#endif 740#endif
837 scbp->SCB_Status = SCB_PEND; 741 scbp->status = SCB_PEND;
838 scbp->SCB_NxtScb = NULL; 742 scbp->next = NULL;
839 if (pCurHcb->HCS_LastPend != NULL) { 743 if (host->last_pending != NULL) {
840 pCurHcb->HCS_LastPend->SCB_NxtScb = scbp; 744 host->last_pending->next = scbp;
841 pCurHcb->HCS_LastPend = scbp; 745 host->last_pending = scbp;
842 } else { 746 } else {
843 pCurHcb->HCS_FirstPend = scbp; 747 host->first_pending = scbp;
844 pCurHcb->HCS_LastPend = scbp; 748 host->last_pending = scbp;
845 } 749 }
846} 750}
847 751
848/***************************************************************************/ 752/***************************************************************************/
849static void tul_push_pend_scb(HCS * pCurHcb, SCB * scbp) 753static void initio_push_pend_scb(struct initio_host * host, struct scsi_ctrl_blk * scbp)
850{ 754{
851 755
852#if DEBUG_QUEUE 756#if DEBUG_QUEUE
853 printk("Push pend SCB %lx; ", (ULONG) scbp); 757 printk("Push pend SCB %p; ", scbp);
854#endif 758#endif
855 scbp->SCB_Status = SCB_PEND; 759 scbp->status = SCB_PEND;
856 if ((scbp->SCB_NxtScb = pCurHcb->HCS_FirstPend) != NULL) { 760 if ((scbp->next = host->first_pending) != NULL) {
857 pCurHcb->HCS_FirstPend = scbp; 761 host->first_pending = scbp;
858 } else { 762 } else {
859 pCurHcb->HCS_FirstPend = scbp; 763 host->first_pending = scbp;
860 pCurHcb->HCS_LastPend = scbp; 764 host->last_pending = scbp;
861 } 765 }
862} 766}
863 767
864/***************************************************************************/ 768static struct scsi_ctrl_blk *initio_find_first_pend_scb(struct initio_host * host)
865static SCB *tul_find_first_pend_scb(HCS * pCurHcb)
866{ 769{
867 SCB *pFirstPend; 770 struct scsi_ctrl_blk *first;
868 771
869 772
870 pFirstPend = pCurHcb->HCS_FirstPend; 773 first = host->first_pending;
871 while (pFirstPend != NULL) { 774 while (first != NULL) {
872 if (pFirstPend->SCB_Opcode != ExecSCSI) { 775 if (first->opcode != ExecSCSI)
873 return (pFirstPend); 776 return first;
874 } 777 if (first->tagmsg == 0) {
875 if (pFirstPend->SCB_TagMsg == 0) { 778 if ((host->act_tags[first->target] == 0) &&
876 if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] == 0) && 779 !(host->targets[first->target].flags & TCF_BUSY))
877 !(pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) { 780 return first;
878 return (pFirstPend);
879 }
880 } else { 781 } else {
881 if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] >= 782 if ((host->act_tags[first->target] >=
882 pCurHcb->HCS_MaxTags[pFirstPend->SCB_Target]) | 783 host->max_tags[first->target]) |
883 (pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) { 784 (host->targets[first->target].flags & TCF_BUSY)) {
884 pFirstPend = pFirstPend->SCB_NxtScb; 785 first = first->next;
885 continue; 786 continue;
886 } 787 }
887 return (pFirstPend); 788 return first;
888 } 789 }
889 pFirstPend = pFirstPend->SCB_NxtScb; 790 first = first->next;
890 } 791 }
891 792 return first;
892
893 return (pFirstPend);
894} 793}
895/***************************************************************************/ 794
896static void tul_unlink_pend_scb(HCS * pCurHcb, SCB * pCurScb) 795static void initio_unlink_pend_scb(struct initio_host * host, struct scsi_ctrl_blk * scb)
897{ 796{
898 SCB *pTmpScb, *pPrevScb; 797 struct scsi_ctrl_blk *tmp, *prev;
899 798
900#if DEBUG_QUEUE 799#if DEBUG_QUEUE
901 printk("unlink pend SCB %lx; ", (ULONG) pCurScb); 800 printk("unlink pend SCB %p; ", scb);
902#endif 801#endif
903 802
904 pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend; 803 prev = tmp = host->first_pending;
905 while (pTmpScb != NULL) { 804 while (tmp != NULL) {
906 if (pCurScb == pTmpScb) { /* Unlink this SCB */ 805 if (scb == tmp) { /* Unlink this SCB */
907 if (pTmpScb == pCurHcb->HCS_FirstPend) { 806 if (tmp == host->first_pending) {
908 if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL) 807 if ((host->first_pending = tmp->next) == NULL)
909 pCurHcb->HCS_LastPend = NULL; 808 host->last_pending = NULL;
910 } else { 809 } else {
911 pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb; 810 prev->next = tmp->next;
912 if (pTmpScb == pCurHcb->HCS_LastPend) 811 if (tmp == host->last_pending)
913 pCurHcb->HCS_LastPend = pPrevScb; 812 host->last_pending = prev;
914 } 813 }
915 pTmpScb->SCB_NxtScb = NULL; 814 tmp->next = NULL;
916 break; 815 break;
917 } 816 }
918 pPrevScb = pTmpScb; 817 prev = tmp;
919 pTmpScb = pTmpScb->SCB_NxtScb; 818 tmp = tmp->next;
920 } 819 }
921 return;
922} 820}
923/***************************************************************************/ 821
924static void tul_append_busy_scb(HCS * pCurHcb, SCB * scbp) 822static void initio_append_busy_scb(struct initio_host * host, struct scsi_ctrl_blk * scbp)
925{ 823{
926 824
927#if DEBUG_QUEUE 825#if DEBUG_QUEUE
928 printk("append busy SCB %lx; ", (ULONG) scbp); 826 printk("append busy SCB %o; ", scbp);
929#endif 827#endif
930 if (scbp->SCB_TagMsg) 828 if (scbp->tagmsg)
931 pCurHcb->HCS_ActTags[scbp->SCB_Target]++; 829 host->act_tags[scbp->target]++;
932 else 830 else
933 pCurHcb->HCS_Tcs[scbp->SCB_Target].TCS_Flags |= TCF_BUSY; 831 host->targets[scbp->target].flags |= TCF_BUSY;
934 scbp->SCB_Status = SCB_BUSY; 832 scbp->status = SCB_BUSY;
935 scbp->SCB_NxtScb = NULL; 833 scbp->next = NULL;
936 if (pCurHcb->HCS_LastBusy != NULL) { 834 if (host->last_busy != NULL) {
937 pCurHcb->HCS_LastBusy->SCB_NxtScb = scbp; 835 host->last_busy->next = scbp;
938 pCurHcb->HCS_LastBusy = scbp; 836 host->last_busy = scbp;
939 } else { 837 } else {
940 pCurHcb->HCS_FirstBusy = scbp; 838 host->first_busy = scbp;
941 pCurHcb->HCS_LastBusy = scbp; 839 host->last_busy = scbp;
942 } 840 }
943} 841}
944 842
945/***************************************************************************/ 843/***************************************************************************/
946static SCB *tul_pop_busy_scb(HCS * pCurHcb) 844static struct scsi_ctrl_blk *initio_pop_busy_scb(struct initio_host * host)
947{ 845{
948 SCB *pTmpScb; 846 struct scsi_ctrl_blk *tmp;
949 847
950 848
951 if ((pTmpScb = pCurHcb->HCS_FirstBusy) != NULL) { 849 if ((tmp = host->first_busy) != NULL) {
952 if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL) 850 if ((host->first_busy = tmp->next) == NULL)
953 pCurHcb->HCS_LastBusy = NULL; 851 host->last_busy = NULL;
954 pTmpScb->SCB_NxtScb = NULL; 852 tmp->next = NULL;
955 if (pTmpScb->SCB_TagMsg) 853 if (tmp->tagmsg)
956 pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--; 854 host->act_tags[tmp->target]--;
957 else 855 else
958 pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY; 856 host->targets[tmp->target].flags &= ~TCF_BUSY;
959 } 857 }
960#if DEBUG_QUEUE 858#if DEBUG_QUEUE
961 printk("Pop busy SCB %lx; ", (ULONG) pTmpScb); 859 printk("Pop busy SCB %p; ", tmp);
962#endif 860#endif
963 return (pTmpScb); 861 return tmp;
964} 862}
965 863
966/***************************************************************************/ 864/***************************************************************************/
967static void tul_unlink_busy_scb(HCS * pCurHcb, SCB * pCurScb) 865static void initio_unlink_busy_scb(struct initio_host * host, struct scsi_ctrl_blk * scb)
968{ 866{
969 SCB *pTmpScb, *pPrevScb; 867 struct scsi_ctrl_blk *tmp, *prev;
970 868
971#if DEBUG_QUEUE 869#if DEBUG_QUEUE
972 printk("unlink busy SCB %lx; ", (ULONG) pCurScb); 870 printk("unlink busy SCB %p; ", scb);
973#endif 871#endif
974 872
975 pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; 873 prev = tmp = host->first_busy;
976 while (pTmpScb != NULL) { 874 while (tmp != NULL) {
977 if (pCurScb == pTmpScb) { /* Unlink this SCB */ 875 if (scb == tmp) { /* Unlink this SCB */
978 if (pTmpScb == pCurHcb->HCS_FirstBusy) { 876 if (tmp == host->first_busy) {
979 if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL) 877 if ((host->first_busy = tmp->next) == NULL)
980 pCurHcb->HCS_LastBusy = NULL; 878 host->last_busy = NULL;
981 } else { 879 } else {
982 pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb; 880 prev->next = tmp->next;
983 if (pTmpScb == pCurHcb->HCS_LastBusy) 881 if (tmp == host->last_busy)
984 pCurHcb->HCS_LastBusy = pPrevScb; 882 host->last_busy = prev;
985 } 883 }
986 pTmpScb->SCB_NxtScb = NULL; 884 tmp->next = NULL;
987 if (pTmpScb->SCB_TagMsg) 885 if (tmp->tagmsg)
988 pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--; 886 host->act_tags[tmp->target]--;
989 else 887 else
990 pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY; 888 host->targets[tmp->target].flags &= ~TCF_BUSY;
991 break; 889 break;
992 } 890 }
993 pPrevScb = pTmpScb; 891 prev = tmp;
994 pTmpScb = pTmpScb->SCB_NxtScb; 892 tmp = tmp->next;
995 } 893 }
996 return; 894 return;
997} 895}
998 896
999/***************************************************************************/ 897struct scsi_ctrl_blk *initio_find_busy_scb(struct initio_host * host, u16 tarlun)
1000SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun)
1001{ 898{
1002 SCB *pTmpScb, *pPrevScb; 899 struct scsi_ctrl_blk *tmp, *prev;
1003 WORD scbp_tarlun; 900 u16 scbp_tarlun;
1004 901
1005 902
1006 pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; 903 prev = tmp = host->first_busy;
1007 while (pTmpScb != NULL) { 904 while (tmp != NULL) {
1008 scbp_tarlun = (pTmpScb->SCB_Lun << 8) | (pTmpScb->SCB_Target); 905 scbp_tarlun = (tmp->lun << 8) | (tmp->target);
1009 if (scbp_tarlun == tarlun) { /* Unlink this SCB */ 906 if (scbp_tarlun == tarlun) { /* Unlink this SCB */
1010 break; 907 break;
1011 } 908 }
1012 pPrevScb = pTmpScb; 909 prev = tmp;
1013 pTmpScb = pTmpScb->SCB_NxtScb; 910 tmp = tmp->next;
1014 } 911 }
1015#if DEBUG_QUEUE 912#if DEBUG_QUEUE
1016 printk("find busy SCB %lx; ", (ULONG) pTmpScb); 913 printk("find busy SCB %p; ", tmp);
1017#endif 914#endif
1018 return (pTmpScb); 915 return tmp;
1019} 916}
1020 917
1021/***************************************************************************/ 918static void initio_append_done_scb(struct initio_host * host, struct scsi_ctrl_blk * scbp)
1022static void tul_append_done_scb(HCS * pCurHcb, SCB * scbp)
1023{ 919{
1024
1025#if DEBUG_QUEUE 920#if DEBUG_QUEUE
1026 printk("append done SCB %lx; ", (ULONG) scbp); 921 printk("append done SCB %p; ", scbp);
1027#endif 922#endif
1028 923
1029 scbp->SCB_Status = SCB_DONE; 924 scbp->status = SCB_DONE;
1030 scbp->SCB_NxtScb = NULL; 925 scbp->next = NULL;
1031 if (pCurHcb->HCS_LastDone != NULL) { 926 if (host->last_done != NULL) {
1032 pCurHcb->HCS_LastDone->SCB_NxtScb = scbp; 927 host->last_done->next = scbp;
1033 pCurHcb->HCS_LastDone = scbp; 928 host->last_done = scbp;
1034 } else { 929 } else {
1035 pCurHcb->HCS_FirstDone = scbp; 930 host->first_done = scbp;
1036 pCurHcb->HCS_LastDone = scbp; 931 host->last_done = scbp;
1037 } 932 }
1038} 933}
1039 934
1040/***************************************************************************/ 935struct scsi_ctrl_blk *initio_find_done_scb(struct initio_host * host)
1041SCB *tul_find_done_scb(HCS * pCurHcb)
1042{ 936{
1043 SCB *pTmpScb; 937 struct scsi_ctrl_blk *tmp;
1044 938
1045 939 if ((tmp = host->first_done) != NULL) {
1046 if ((pTmpScb = pCurHcb->HCS_FirstDone) != NULL) { 940 if ((host->first_done = tmp->next) == NULL)
1047 if ((pCurHcb->HCS_FirstDone = pTmpScb->SCB_NxtScb) == NULL) 941 host->last_done = NULL;
1048 pCurHcb->HCS_LastDone = NULL; 942 tmp->next = NULL;
1049 pTmpScb->SCB_NxtScb = NULL;
1050 } 943 }
1051#if DEBUG_QUEUE 944#if DEBUG_QUEUE
1052 printk("find done SCB %lx; ", (ULONG) pTmpScb); 945 printk("find done SCB %p; ",tmp);
1053#endif 946#endif
1054 return (pTmpScb); 947 return tmp;
1055} 948}
1056 949
1057/***************************************************************************/ 950static int initio_abort_srb(struct initio_host * host, struct scsi_cmnd *srbp)
1058static int tul_abort_srb(HCS * pCurHcb, struct scsi_cmnd *srbp)
1059{ 951{
1060 ULONG flags; 952 unsigned long flags;
1061 SCB *pTmpScb, *pPrevScb; 953 struct scsi_ctrl_blk *tmp, *prev;
1062 954
1063 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags); 955 spin_lock_irqsave(&host->semaph_lock, flags);
1064 956
1065 if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) { 957 if ((host->semaph == 0) && (host->active == NULL)) {
1066 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
1067 /* disable Jasmin SCSI Int */ 958 /* disable Jasmin SCSI Int */
1068 959 outb(0x1F, host->addr + TUL_Mask);
1069 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 960 spin_unlock_irqrestore(&host->semaph_lock, flags);
1070 961 /* FIXME: synchronize_irq needed ? */
1071 tulip_main(pCurHcb); 962 tulip_main(host);
1072 963 spin_lock_irqsave(&host->semaph_lock, flags);
1073 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags); 964 host->semaph = 1;
1074 965 outb(0x0F, host->addr + TUL_Mask);
1075 pCurHcb->HCS_Semaph = 1; 966 spin_unlock_irqrestore(&host->semaph_lock, flags);
1076 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
1077
1078 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1079
1080 return SCSI_ABORT_SNOOZE; 967 return SCSI_ABORT_SNOOZE;
1081 } 968 }
1082 pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend; /* Check Pend queue */ 969 prev = tmp = host->first_pending; /* Check Pend queue */
1083 while (pTmpScb != NULL) { 970 while (tmp != NULL) {
1084 /* 07/27/98 */ 971 /* 07/27/98 */
1085 if (pTmpScb->SCB_Srb == srbp) { 972 if (tmp->srb == srbp) {
1086 if (pTmpScb == pCurHcb->HCS_ActScb) { 973 if (tmp == host->active) {
1087 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 974 spin_unlock_irqrestore(&host->semaph_lock, flags);
1088 return SCSI_ABORT_BUSY; 975 return SCSI_ABORT_BUSY;
1089 } else if (pTmpScb == pCurHcb->HCS_FirstPend) { 976 } else if (tmp == host->first_pending) {
1090 if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL) 977 if ((host->first_pending = tmp->next) == NULL)
1091 pCurHcb->HCS_LastPend = NULL; 978 host->last_pending = NULL;
1092 } else { 979 } else {
1093 pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb; 980 prev->next = tmp->next;
1094 if (pTmpScb == pCurHcb->HCS_LastPend) 981 if (tmp == host->last_pending)
1095 pCurHcb->HCS_LastPend = pPrevScb; 982 host->last_pending = prev;
1096 } 983 }
1097 pTmpScb->SCB_HaStat = HOST_ABORTED; 984 tmp->hastat = HOST_ABORTED;
1098 pTmpScb->SCB_Flags |= SCF_DONE; 985 tmp->flags |= SCF_DONE;
1099 if (pTmpScb->SCB_Flags & SCF_POST) 986 if (tmp->flags & SCF_POST)
1100 (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb); 987 (*tmp->post) ((u8 *) host, (u8 *) tmp);
1101 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 988 spin_unlock_irqrestore(&host->semaph_lock, flags);
1102 return SCSI_ABORT_SUCCESS; 989 return SCSI_ABORT_SUCCESS;
1103 } 990 }
1104 pPrevScb = pTmpScb; 991 prev = tmp;
1105 pTmpScb = pTmpScb->SCB_NxtScb; 992 tmp = tmp->next;
1106 } 993 }
1107 994
1108 pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */ 995 prev = tmp = host->first_busy; /* Check Busy queue */
1109 while (pTmpScb != NULL) { 996 while (tmp != NULL) {
1110 997 if (tmp->srb == srbp) {
1111 if (pTmpScb->SCB_Srb == srbp) { 998 if (tmp == host->active) {
1112 999 spin_unlock_irqrestore(&host->semaph_lock, flags);
1113 if (pTmpScb == pCurHcb->HCS_ActScb) {
1114 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1115 return SCSI_ABORT_BUSY; 1000 return SCSI_ABORT_BUSY;
1116 } else if (pTmpScb->SCB_TagMsg == 0) { 1001 } else if (tmp->tagmsg == 0) {
1117 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 1002 spin_unlock_irqrestore(&host->semaph_lock, flags);
1118 return SCSI_ABORT_BUSY; 1003 return SCSI_ABORT_BUSY;
1119 } else { 1004 } else {
1120 pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--; 1005 host->act_tags[tmp->target]--;
1121 if (pTmpScb == pCurHcb->HCS_FirstBusy) { 1006 if (tmp == host->first_busy) {
1122 if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL) 1007 if ((host->first_busy = tmp->next) == NULL)
1123 pCurHcb->HCS_LastBusy = NULL; 1008 host->last_busy = NULL;
1124 } else { 1009 } else {
1125 pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb; 1010 prev->next = tmp->next;
1126 if (pTmpScb == pCurHcb->HCS_LastBusy) 1011 if (tmp == host->last_busy)
1127 pCurHcb->HCS_LastBusy = pPrevScb; 1012 host->last_busy = prev;
1128 } 1013 }
1129 pTmpScb->SCB_NxtScb = NULL; 1014 tmp->next = NULL;
1130 1015
1131 1016
1132 pTmpScb->SCB_HaStat = HOST_ABORTED; 1017 tmp->hastat = HOST_ABORTED;
1133 pTmpScb->SCB_Flags |= SCF_DONE; 1018 tmp->flags |= SCF_DONE;
1134 if (pTmpScb->SCB_Flags & SCF_POST) 1019 if (tmp->flags & SCF_POST)
1135 (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb); 1020 (*tmp->post) ((u8 *) host, (u8 *) tmp);
1136 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 1021 spin_unlock_irqrestore(&host->semaph_lock, flags);
1137 return SCSI_ABORT_SUCCESS; 1022 return SCSI_ABORT_SUCCESS;
1138 } 1023 }
1139 } 1024 }
1140 pPrevScb = pTmpScb; 1025 prev = tmp;
1141 pTmpScb = pTmpScb->SCB_NxtScb; 1026 tmp = tmp->next;
1142 } 1027 }
1143 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 1028 spin_unlock_irqrestore(&host->semaph_lock, flags);
1144 return (SCSI_ABORT_NOT_RUNNING); 1029 return SCSI_ABORT_NOT_RUNNING;
1145} 1030}
1146 1031
1147/***************************************************************************/ 1032/***************************************************************************/
1148static int tul_bad_seq(HCS * pCurHcb) 1033static int initio_bad_seq(struct initio_host * host)
1149{ 1034{
1150 SCB *pCurScb; 1035 struct scsi_ctrl_blk *scb;
1151
1152 printk("tul_bad_seg c=%d\n", pCurHcb->HCS_Index);
1153
1154 if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
1155 tul_unlink_busy_scb(pCurHcb, pCurScb);
1156 pCurScb->SCB_HaStat = HOST_BAD_PHAS;
1157 pCurScb->SCB_TaStat = 0;
1158 tul_append_done_scb(pCurHcb, pCurScb);
1159 }
1160 tul_stop_bm(pCurHcb);
1161
1162 tul_reset_scsi(pCurHcb, 8); /* 7/29/98 */
1163
1164 return (tul_post_scsi_rst(pCurHcb));
1165}
1166
1167#if 0
1168
1169/************************************************************************/
1170static int tul_device_reset(HCS * pCurHcb, struct scsi_cmnd *pSrb,
1171 unsigned int target, unsigned int ResetFlags)
1172{
1173 ULONG flags;
1174 SCB *pScb;
1175 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
1176
1177 if (ResetFlags & SCSI_RESET_ASYNCHRONOUS) {
1178
1179 if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
1180 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
1181 /* disable Jasmin SCSI Int */
1182
1183 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1184
1185 tulip_main(pCurHcb);
1186
1187 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
1188
1189 pCurHcb->HCS_Semaph = 1;
1190 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
1191
1192 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1193
1194 return SCSI_RESET_SNOOZE;
1195 }
1196 pScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
1197 while (pScb != NULL) {
1198 if (pScb->SCB_Srb == pSrb)
1199 break;
1200 pScb = pScb->SCB_NxtScb;
1201 }
1202 if (pScb == NULL) {
1203 printk("Unable to Reset - No SCB Found\n");
1204
1205 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1206 return SCSI_RESET_NOT_RUNNING;
1207 }
1208 }
1209 if ((pScb = tul_alloc_scb(pCurHcb)) == NULL) {
1210 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1211 return SCSI_RESET_NOT_RUNNING;
1212 }
1213 pScb->SCB_Opcode = BusDevRst;
1214 pScb->SCB_Flags = SCF_POST;
1215 pScb->SCB_Target = target;
1216 pScb->SCB_Mode = 0;
1217
1218 pScb->SCB_Srb = NULL;
1219 if (ResetFlags & SCSI_RESET_SYNCHRONOUS) {
1220 pScb->SCB_Srb = pSrb;
1221 }
1222 tul_push_pend_scb(pCurHcb, pScb); /* push this SCB to Pending queue */
1223
1224 if (pCurHcb->HCS_Semaph == 1) {
1225 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
1226 /* disable Jasmin SCSI Int */
1227 pCurHcb->HCS_Semaph = 0;
1228
1229 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1230 1036
1231 tulip_main(pCurHcb); 1037 printk("initio_bad_seg c=%d\n", host->index);
1232 1038
1233 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags); 1039 if ((scb = host->active) != NULL) {
1234 1040 initio_unlink_busy_scb(host, scb);
1235 pCurHcb->HCS_Semaph = 1; 1041 scb->hastat = HOST_BAD_PHAS;
1236 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F); 1042 scb->tastat = 0;
1043 initio_append_done_scb(host, scb);
1237 } 1044 }
1238 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 1045 initio_stop_bm(host);
1239 return SCSI_RESET_PENDING; 1046 initio_reset_scsi(host, 8); /* 7/29/98 */
1047 return initio_post_scsi_rst(host);
1240} 1048}
1241 1049
1242static int tul_reset_scsi_bus(HCS * pCurHcb)
1243{
1244 ULONG flags;
1245
1246 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
1247 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
1248 pCurHcb->HCS_Semaph = 0;
1249
1250 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1251
1252 tul_stop_bm(pCurHcb);
1253
1254 tul_reset_scsi(pCurHcb, 2); /* 7/29/98 */
1255
1256 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
1257 tul_post_scsi_rst(pCurHcb);
1258
1259 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1260
1261 tulip_main(pCurHcb);
1262
1263 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
1264
1265 pCurHcb->HCS_Semaph = 1;
1266 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
1267 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1268 return (SCSI_RESET_SUCCESS | SCSI_RESET_HOST_RESET);
1269}
1270
1271#endif /* 0 */
1272 1050
1273/************************************************************************/ 1051/************************************************************************/
1274static void tul_exec_scb(HCS * pCurHcb, SCB * pCurScb) 1052static void initio_exec_scb(struct initio_host * host, struct scsi_ctrl_blk * scb)
1275{ 1053{
1276 ULONG flags; 1054 unsigned long flags;
1277 1055
1278 pCurScb->SCB_Mode = 0; 1056 scb->mode = 0;
1279 1057
1280 pCurScb->SCB_SGIdx = 0; 1058 scb->sgidx = 0;
1281 pCurScb->SCB_SGMax = pCurScb->SCB_SGLen; 1059 scb->sgmax = scb->sglen;
1282 1060
1283 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags); 1061 spin_lock_irqsave(&host->semaph_lock, flags);
1284 1062
1285 tul_append_pend_scb(pCurHcb, pCurScb); /* Append this SCB to Pending queue */ 1063 initio_append_pend_scb(host, scb); /* Append this SCB to Pending queue */
1286 1064
1287/* VVVVV 07/21/98 */ 1065/* VVVVV 07/21/98 */
1288 if (pCurHcb->HCS_Semaph == 1) { 1066 if (host->semaph == 1) {
1289 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F); 1067 /* Disable Jasmin SCSI Int */
1290 /* disable Jasmin SCSI Int */ 1068 outb(0x1F, host->addr + TUL_Mask);
1291 pCurHcb->HCS_Semaph = 0; 1069 host->semaph = 0;
1292 1070 spin_unlock_irqrestore(&host->semaph_lock, flags);
1293 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
1294 1071
1295 tulip_main(pCurHcb); 1072 tulip_main(host);
1296 1073
1297 spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags); 1074 spin_lock_irqsave(&host->semaph_lock, flags);
1298 1075 host->semaph = 1;
1299 pCurHcb->HCS_Semaph = 1; 1076 outb(0x0F, host->addr + TUL_Mask);
1300 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
1301 } 1077 }
1302 spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags); 1078 spin_unlock_irqrestore(&host->semaph_lock, flags);
1303 return; 1079 return;
1304} 1080}
1305 1081
1306/***************************************************************************/ 1082/***************************************************************************/
1307static int tul_isr(HCS * pCurHcb) 1083static int initio_isr(struct initio_host * host)
1308{ 1084{
1309 /* Enter critical section */ 1085 if (inb(host->addr + TUL_Int) & TSS_INT_PENDING) {
1310 1086 if (host->semaph == 1) {
1311 if (TUL_RD(pCurHcb->HCS_Base, TUL_Int) & TSS_INT_PENDING) { 1087 outb(0x1F, host->addr + TUL_Mask);
1312 if (pCurHcb->HCS_Semaph == 1) {
1313 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
1314 /* Disable Tulip SCSI Int */ 1088 /* Disable Tulip SCSI Int */
1315 pCurHcb->HCS_Semaph = 0; 1089 host->semaph = 0;
1316 1090
1317 tulip_main(pCurHcb); 1091 tulip_main(host);
1318 1092
1319 pCurHcb->HCS_Semaph = 1; 1093 host->semaph = 1;
1320 TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F); 1094 outb(0x0F, host->addr + TUL_Mask);
1321 return (1); 1095 return 1;
1322 } 1096 }
1323 } 1097 }
1324 return (0); 1098 return 0;
1325} 1099}
1326 1100
1327/***************************************************************************/ 1101static int tulip_main(struct initio_host * host)
1328int tulip_main(HCS * pCurHcb)
1329{ 1102{
1330 SCB *pCurScb; 1103 struct scsi_ctrl_blk *scb;
1331 1104
1332 for (;;) { 1105 for (;;) {
1333 1106 tulip_scsi(host); /* Call tulip_scsi */
1334 tulip_scsi(pCurHcb); /* Call tulip_scsi */ 1107
1335 1108 /* Walk the list of completed SCBs */
1336 while ((pCurScb = tul_find_done_scb(pCurHcb)) != NULL) { /* find done entry */ 1109 while ((scb = initio_find_done_scb(host)) != NULL) { /* find done entry */
1337 if (pCurScb->SCB_TaStat == INI_QUEUE_FULL) { 1110 if (scb->tastat == INI_QUEUE_FULL) {
1338 pCurHcb->HCS_MaxTags[pCurScb->SCB_Target] = 1111 host->max_tags[scb->target] =
1339 pCurHcb->HCS_ActTags[pCurScb->SCB_Target] - 1; 1112 host->act_tags[scb->target] - 1;
1340 pCurScb->SCB_TaStat = 0; 1113 scb->tastat = 0;
1341 tul_append_pend_scb(pCurHcb, pCurScb); 1114 initio_append_pend_scb(host, scb);
1342 continue; 1115 continue;
1343 } 1116 }
1344 if (!(pCurScb->SCB_Mode & SCM_RSENS)) { /* not in auto req. sense mode */ 1117 if (!(scb->mode & SCM_RSENS)) { /* not in auto req. sense mode */
1345 if (pCurScb->SCB_TaStat == 2) { 1118 if (scb->tastat == 2) {
1346 1119
1347 /* clr sync. nego flag */ 1120 /* clr sync. nego flag */
1348 1121
1349 if (pCurScb->SCB_Flags & SCF_SENSE) { 1122 if (scb->flags & SCF_SENSE) {
1350 BYTE len; 1123 u8 len;
1351 len = pCurScb->SCB_SenseLen; 1124 len = scb->senselen;
1352 if (len == 0) 1125 if (len == 0)
1353 len = 1; 1126 len = 1;
1354 pCurScb->SCB_BufLen = pCurScb->SCB_SenseLen; 1127 scb->buflen = scb->senselen;
1355 pCurScb->SCB_BufPtr = pCurScb->SCB_SensePtr; 1128 scb->bufptr = scb->senseptr;
1356 pCurScb->SCB_Flags &= ~(SCF_SG | SCF_DIR); /* for xfer_data_in */ 1129 scb->flags &= ~(SCF_SG | SCF_DIR); /* for xfer_data_in */
1357/* pCurScb->SCB_Flags |= SCF_NO_DCHK; */ 1130 /* so, we won't report wrong direction in xfer_data_in,
1358 /* so, we won't report worng direction in xfer_data_in,
1359 and won't report HOST_DO_DU in state_6 */ 1131 and won't report HOST_DO_DU in state_6 */
1360 pCurScb->SCB_Mode = SCM_RSENS; 1132 scb->mode = SCM_RSENS;
1361 pCurScb->SCB_Ident &= 0xBF; /* Disable Disconnect */ 1133 scb->ident &= 0xBF; /* Disable Disconnect */
1362 pCurScb->SCB_TagMsg = 0; 1134 scb->tagmsg = 0;
1363 pCurScb->SCB_TaStat = 0; 1135 scb->tastat = 0;
1364 pCurScb->SCB_CDBLen = 6; 1136 scb->cdblen = 6;
1365 pCurScb->SCB_CDB[0] = SCSICMD_RequestSense; 1137 scb->cdb[0] = SCSICMD_RequestSense;
1366 pCurScb->SCB_CDB[1] = 0; 1138 scb->cdb[1] = 0;
1367 pCurScb->SCB_CDB[2] = 0; 1139 scb->cdb[2] = 0;
1368 pCurScb->SCB_CDB[3] = 0; 1140 scb->cdb[3] = 0;
1369 pCurScb->SCB_CDB[4] = len; 1141 scb->cdb[4] = len;
1370 pCurScb->SCB_CDB[5] = 0; 1142 scb->cdb[5] = 0;
1371 tul_push_pend_scb(pCurHcb, pCurScb); 1143 initio_push_pend_scb(host, scb);
1372 break; 1144 break;
1373 } 1145 }
1374 } 1146 }
1375 } else { /* in request sense mode */ 1147 } else { /* in request sense mode */
1376 1148
1377 if (pCurScb->SCB_TaStat == 2) { /* check contition status again after sending 1149 if (scb->tastat == 2) { /* check contition status again after sending
1378 requset sense cmd 0x3 */ 1150 requset sense cmd 0x3 */
1379 pCurScb->SCB_HaStat = HOST_BAD_PHAS; 1151 scb->hastat = HOST_BAD_PHAS;
1380 } 1152 }
1381 pCurScb->SCB_TaStat = 2; 1153 scb->tastat = 2;
1382 } 1154 }
1383 pCurScb->SCB_Flags |= SCF_DONE; 1155 scb->flags |= SCF_DONE;
1384 if (pCurScb->SCB_Flags & SCF_POST) { 1156 if (scb->flags & SCF_POST) {
1385 (*pCurScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pCurScb); 1157 /* FIXME: only one post method and lose casts */
1158 (*scb->post) ((u8 *) host, (u8 *) scb);
1386 } 1159 }
1387 } /* while */ 1160 } /* while */
1388
1389 /* find_active: */ 1161 /* find_active: */
1390 if (TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0) & TSS_INT_PENDING) 1162 if (inb(host->addr + TUL_SStatus0) & TSS_INT_PENDING)
1391 continue; 1163 continue;
1392 1164 if (host->active) /* return to OS and wait for xfer_done_ISR/Selected_ISR */
1393 if (pCurHcb->HCS_ActScb) { /* return to OS and wait for xfer_done_ISR/Selected_ISR */
1394 return 1; /* return to OS, enable interrupt */ 1165 return 1; /* return to OS, enable interrupt */
1395 }
1396 /* Check pending SCB */ 1166 /* Check pending SCB */
1397 if (tul_find_first_pend_scb(pCurHcb) == NULL) { 1167 if (initio_find_first_pend_scb(host) == NULL)
1398 return 1; /* return to OS, enable interrupt */ 1168 return 1; /* return to OS, enable interrupt */
1399 }
1400 } /* End of for loop */ 1169 } /* End of for loop */
1401 /* statement won't reach here */ 1170 /* statement won't reach here */
1402} 1171}
1403 1172
1404 1173static void tulip_scsi(struct initio_host * host)
1405
1406
1407/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
1408/***************************************************************************/
1409/***************************************************************************/
1410/***************************************************************************/
1411/***************************************************************************/
1412
1413/***************************************************************************/
1414void tulip_scsi(HCS * pCurHcb)
1415{ 1174{
1416 SCB *pCurScb; 1175 struct scsi_ctrl_blk *scb;
1417 TCS *pCurTcb; 1176 struct target_control *active_tc;
1418 1177
1419 /* make sure to service interrupt asap */ 1178 /* make sure to service interrupt asap */
1420 1179 if ((host->jsstatus0 = inb(host->addr + TUL_SStatus0)) & TSS_INT_PENDING) {
1421 if ((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0)) & TSS_INT_PENDING) { 1180 host->phase = host->jsstatus0 & TSS_PH_MASK;
1422 1181 host->jsstatus1 = inb(host->addr + TUL_SStatus1);
1423 pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK; 1182 host->jsint = inb(host->addr + TUL_SInt);
1424 pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1); 1183 if (host->jsint & TSS_SCSIRST_INT) { /* SCSI bus reset detected */
1425 pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt); 1184 int_initio_scsi_rst(host);
1426 if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* SCSI bus reset detected */
1427 int_tul_scsi_rst(pCurHcb);
1428 return; 1185 return;
1429 } 1186 }
1430 if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if selected/reselected interrupt */ 1187 if (host->jsint & TSS_RESEL_INT) { /* if selected/reselected interrupt */
1431 if (int_tul_resel(pCurHcb) == 0) 1188 if (int_initio_resel(host) == 0)
1432 tul_next_state(pCurHcb); 1189 initio_next_state(host);
1433 return; 1190 return;
1434 } 1191 }
1435 if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) { 1192 if (host->jsint & TSS_SEL_TIMEOUT) {
1436 int_tul_busfree(pCurHcb); 1193 int_initio_busfree(host);
1437 return; 1194 return;
1438 } 1195 }
1439 if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */ 1196 if (host->jsint & TSS_DISC_INT) { /* BUS disconnection */
1440 int_tul_busfree(pCurHcb); /* unexpected bus free or sel timeout */ 1197 int_initio_busfree(host); /* unexpected bus free or sel timeout */
1441 return; 1198 return;
1442 } 1199 }
1443 if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) { /* func complete or Bus service */ 1200 if (host->jsint & (TSS_FUNC_COMP | TSS_BUS_SERV)) { /* func complete or Bus service */
1444 if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) 1201 if ((scb = host->active) != NULL)
1445 tul_next_state(pCurHcb); 1202 initio_next_state(host);
1446 return; 1203 return;
1447 } 1204 }
1448 } 1205 }
1449 if (pCurHcb->HCS_ActScb != NULL) 1206 if (host->active != NULL)
1450 return; 1207 return;
1451 1208
1452 if ((pCurScb = tul_find_first_pend_scb(pCurHcb)) == NULL) 1209 if ((scb = initio_find_first_pend_scb(host)) == NULL)
1453 return; 1210 return;
1454 1211
1455 /* program HBA's SCSI ID & target SCSI ID */ 1212 /* program HBA's SCSI ID & target SCSI ID */
1456 TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId, 1213 outb((host->scsi_id << 4) | (scb->target & 0x0F),
1457 (pCurHcb->HCS_SCSI_ID << 4) | (pCurScb->SCB_Target & 0x0F)); 1214 host->addr + TUL_SScsiId);
1458 if (pCurScb->SCB_Opcode == ExecSCSI) { 1215 if (scb->opcode == ExecSCSI) {
1459 pCurTcb = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target]; 1216 active_tc = &host->targets[scb->target];
1460 1217
1461 if (pCurScb->SCB_TagMsg) 1218 if (scb->tagmsg)
1462 pCurTcb->TCS_DrvFlags |= TCF_DRV_EN_TAG; 1219 active_tc->drv_flags |= TCF_DRV_EN_TAG;
1463 else 1220 else
1464 pCurTcb->TCS_DrvFlags &= ~TCF_DRV_EN_TAG; 1221 active_tc->drv_flags &= ~TCF_DRV_EN_TAG;
1465 1222
1466 TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period); 1223 outb(active_tc->js_period, host->addr + TUL_SPeriod);
1467 if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) { /* do wdtr negotiation */ 1224 if ((active_tc->flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) { /* do wdtr negotiation */
1468 tul_select_atn_stop(pCurHcb, pCurScb); 1225 initio_select_atn_stop(host, scb);
1469 } else { 1226 } else {
1470 if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync negotiation */ 1227 if ((active_tc->flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync negotiation */
1471 tul_select_atn_stop(pCurHcb, pCurScb); 1228 initio_select_atn_stop(host, scb);
1472 } else { 1229 } else {
1473 if (pCurScb->SCB_TagMsg) 1230 if (scb->tagmsg)
1474 tul_select_atn3(pCurHcb, pCurScb); 1231 initio_select_atn3(host, scb);
1475 else 1232 else
1476 tul_select_atn(pCurHcb, pCurScb); 1233 initio_select_atn(host, scb);
1477 } 1234 }
1478 } 1235 }
1479 if (pCurScb->SCB_Flags & SCF_POLL) { 1236 if (scb->flags & SCF_POLL) {
1480 while (wait_tulip(pCurHcb) != -1) { 1237 while (wait_tulip(host) != -1) {
1481 if (tul_next_state(pCurHcb) == -1) 1238 if (initio_next_state(host) == -1)
1482 break; 1239 break;
1483 } 1240 }
1484 } 1241 }
1485 } else if (pCurScb->SCB_Opcode == BusDevRst) { 1242 } else if (scb->opcode == BusDevRst) {
1486 tul_select_atn_stop(pCurHcb, pCurScb); 1243 initio_select_atn_stop(host, scb);
1487 pCurScb->SCB_NxtStat = 8; 1244 scb->next_state = 8;
1488 if (pCurScb->SCB_Flags & SCF_POLL) { 1245 if (scb->flags & SCF_POLL) {
1489 while (wait_tulip(pCurHcb) != -1) { 1246 while (wait_tulip(host) != -1) {
1490 if (tul_next_state(pCurHcb) == -1) 1247 if (initio_next_state(host) == -1)
1491 break; 1248 break;
1492 } 1249 }
1493 } 1250 }
1494 } else if (pCurScb->SCB_Opcode == AbortCmd) { 1251 } else if (scb->opcode == AbortCmd) {
1495 if (tul_abort_srb(pCurHcb, pCurScb->SCB_Srb) != 0) { 1252 if (initio_abort_srb(host, scb->srb) != 0) {
1496 1253 initio_unlink_pend_scb(host, scb);
1497 1254 initio_release_scb(host, scb);
1498 tul_unlink_pend_scb(pCurHcb, pCurScb);
1499
1500 tul_release_scb(pCurHcb, pCurScb);
1501 } else { 1255 } else {
1502 pCurScb->SCB_Opcode = BusDevRst; 1256 scb->opcode = BusDevRst;
1503 tul_select_atn_stop(pCurHcb, pCurScb); 1257 initio_select_atn_stop(host, scb);
1504 pCurScb->SCB_NxtStat = 8; 1258 scb->next_state = 8;
1505 } 1259 }
1506
1507/* 08/03/98 */
1508 } else { 1260 } else {
1509 tul_unlink_pend_scb(pCurHcb, pCurScb); 1261 initio_unlink_pend_scb(host, scb);
1510 pCurScb->SCB_HaStat = 0x16; /* bad command */ 1262 scb->hastat = 0x16; /* bad command */
1511 tul_append_done_scb(pCurHcb, pCurScb); 1263 initio_append_done_scb(host, scb);
1512 } 1264 }
1513 return; 1265 return;
1514} 1266}
1515 1267
1268/**
1269 * initio_next_state - Next SCSI state
1270 * @host: InitIO host we are processing
1271 *
1272 * Progress the active command block along the state machine
1273 * until we hit a state which we must wait for activity to occur.
1274 *
1275 * Returns zero or a negative code.
1276 */
1516 1277
1517/***************************************************************************/ 1278static int initio_next_state(struct initio_host * host)
1518int tul_next_state(HCS * pCurHcb)
1519{ 1279{
1520 int next; 1280 int next;
1521 1281
1522 next = pCurHcb->HCS_ActScb->SCB_NxtStat; 1282 next = host->active->next_state;
1523 for (;;) { 1283 for (;;) {
1524 switch (next) { 1284 switch (next) {
1525 case 1: 1285 case 1:
1526 next = tul_state_1(pCurHcb); 1286 next = initio_state_1(host);
1527 break; 1287 break;
1528 case 2: 1288 case 2:
1529 next = tul_state_2(pCurHcb); 1289 next = initio_state_2(host);
1530 break; 1290 break;
1531 case 3: 1291 case 3:
1532 next = tul_state_3(pCurHcb); 1292 next = initio_state_3(host);
1533 break; 1293 break;
1534 case 4: 1294 case 4:
1535 next = tul_state_4(pCurHcb); 1295 next = initio_state_4(host);
1536 break; 1296 break;
1537 case 5: 1297 case 5:
1538 next = tul_state_5(pCurHcb); 1298 next = initio_state_5(host);
1539 break; 1299 break;
1540 case 6: 1300 case 6:
1541 next = tul_state_6(pCurHcb); 1301 next = initio_state_6(host);
1542 break; 1302 break;
1543 case 7: 1303 case 7:
1544 next = tul_state_7(pCurHcb); 1304 next = initio_state_7(host);
1545 break; 1305 break;
1546 case 8: 1306 case 8:
1547 return (tul_bus_device_reset(pCurHcb)); 1307 return initio_bus_device_reset(host);
1548 default: 1308 default:
1549 return (tul_bad_seq(pCurHcb)); 1309 return initio_bad_seq(host);
1550 } 1310 }
1551 if (next <= 0) 1311 if (next <= 0)
1552 return next; 1312 return next;
@@ -1554,338 +1314,363 @@ int tul_next_state(HCS * pCurHcb)
1554} 1314}
1555 1315
1556 1316
1557/***************************************************************************/ 1317/**
1558/* sTate after selection with attention & stop */ 1318 * initio_state_1 - SCSI state machine
1559int tul_state_1(HCS * pCurHcb) 1319 * @host: InitIO host we are controlling
1320 *
1321 * Perform SCSI state processing for Select/Attention/Stop
1322 */
1323
1324static int initio_state_1(struct initio_host * host)
1560{ 1325{
1561 SCB *pCurScb = pCurHcb->HCS_ActScb; 1326 struct scsi_ctrl_blk *scb = host->active;
1562 TCS *pCurTcb = pCurHcb->HCS_ActTcs; 1327 struct target_control *active_tc = host->active_tc;
1563#if DEBUG_STATE 1328#if DEBUG_STATE
1564 printk("-s1-"); 1329 printk("-s1-");
1565#endif 1330#endif
1566 1331
1567 tul_unlink_pend_scb(pCurHcb, pCurScb); 1332 /* Move the SCB from pending to busy */
1568 tul_append_busy_scb(pCurHcb, pCurScb); 1333 initio_unlink_pend_scb(host, scb);
1334 initio_append_busy_scb(host, scb);
1569 1335
1570 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0); 1336 outb(active_tc->sconfig0, host->addr + TUL_SConfig );
1571 /* ATN on */ 1337 /* ATN on */
1572 if (pCurHcb->HCS_Phase == MSG_OUT) { 1338 if (host->phase == MSG_OUT) {
1573 1339 outb(TSC_EN_BUS_IN | TSC_HW_RESELECT, host->addr + TUL_SCtrl1);
1574 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, (TSC_EN_BUS_IN | TSC_HW_RESELECT)); 1340 outb(scb->ident, host->addr + TUL_SFifo);
1575 1341
1576 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident); 1342 if (scb->tagmsg) {
1577 1343 outb(scb->tagmsg, host->addr + TUL_SFifo);
1578 if (pCurScb->SCB_TagMsg) { 1344 outb(scb->tagid, host->addr + TUL_SFifo);
1579 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg); 1345 }
1580 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId); 1346 if ((active_tc->flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) {
1581 } 1347 active_tc->flags |= TCF_WDTR_DONE;
1582 if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) { 1348 outb(MSG_EXTEND, host->addr + TUL_SFifo);
1583 1349 outb(2, host->addr + TUL_SFifo); /* Extended msg length */
1584 pCurTcb->TCS_Flags |= TCF_WDTR_DONE; 1350 outb(3, host->addr + TUL_SFifo); /* Sync request */
1585 1351 outb(1, host->addr + TUL_SFifo); /* Start from 16 bits */
1586 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND); 1352 } else if ((active_tc->flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) {
1587 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2); /* Extended msg length */ 1353 active_tc->flags |= TCF_SYNC_DONE;
1588 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* Sync request */ 1354 outb(MSG_EXTEND, host->addr + TUL_SFifo);
1589 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* Start from 16 bits */ 1355 outb(3, host->addr + TUL_SFifo); /* extended msg length */
1590 } else if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { 1356 outb(1, host->addr + TUL_SFifo); /* sync request */
1591 1357 outb(initio_rate_tbl[active_tc->flags & TCF_SCSI_RATE], host->addr + TUL_SFifo);
1592 pCurTcb->TCS_Flags |= TCF_SYNC_DONE; 1358 outb(MAX_OFFSET, host->addr + TUL_SFifo); /* REQ/ACK offset */
1593 1359 }
1594 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND); 1360 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1595 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* extended msg length */ 1361 if (wait_tulip(host) == -1)
1596 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */ 1362 return -1;
1597 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]); 1363 }
1598 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */ 1364 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
1599 } 1365 outb((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)), host->addr + TUL_SSignal);
1600 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1366 /* Into before CDB xfer */
1601 if (wait_tulip(pCurHcb) == -1) 1367 return 3;
1602 return (-1); 1368}
1603 } 1369
1604 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1370
1605 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7))); 1371/**
1606 return (3); 1372 * initio_state_2 - SCSI state machine
1607} 1373 * @host: InitIO host we are controlling
1608 1374 *
1375 * state after selection with attention
1376 * state after selection with attention3
1377 */
1609 1378
1610/***************************************************************************/ 1379static int initio_state_2(struct initio_host * host)
1611/* state after selection with attention */
1612/* state after selection with attention3 */
1613int tul_state_2(HCS * pCurHcb)
1614{ 1380{
1615 SCB *pCurScb = pCurHcb->HCS_ActScb; 1381 struct scsi_ctrl_blk *scb = host->active;
1616 TCS *pCurTcb = pCurHcb->HCS_ActTcs; 1382 struct target_control *active_tc = host->active_tc;
1617#if DEBUG_STATE 1383#if DEBUG_STATE
1618 printk("-s2-"); 1384 printk("-s2-");
1619#endif 1385#endif
1620 1386
1621 tul_unlink_pend_scb(pCurHcb, pCurScb); 1387 initio_unlink_pend_scb(host, scb);
1622 tul_append_busy_scb(pCurHcb, pCurScb); 1388 initio_append_busy_scb(host, scb);
1623 1389
1624 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0); 1390 outb(active_tc->sconfig0, host->addr + TUL_SConfig);
1625 1391
1626 if (pCurHcb->HCS_JSStatus1 & TSS_CMD_PH_CMP) { 1392 if (host->jsstatus1 & TSS_CMD_PH_CMP)
1627 return (4); 1393 return 4;
1628 } 1394
1629 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1395 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
1630 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7))); 1396 outb((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)), host->addr + TUL_SSignal);
1631 return (3); 1397 /* Into before CDB xfer */
1398 return 3;
1632} 1399}
1633 1400
1634/***************************************************************************/ 1401/**
1635/* state before CDB xfer is done */ 1402 * initio_state_3 - SCSI state machine
1636int tul_state_3(HCS * pCurHcb) 1403 * @host: InitIO host we are controlling
1404 *
1405 * state before CDB xfer is done
1406 */
1407
1408static int initio_state_3(struct initio_host * host)
1637{ 1409{
1638 SCB *pCurScb = pCurHcb->HCS_ActScb; 1410 struct scsi_ctrl_blk *scb = host->active;
1639 TCS *pCurTcb = pCurHcb->HCS_ActTcs; 1411 struct target_control *active_tc = host->active_tc;
1640 int i; 1412 int i;
1641 1413
1642#if DEBUG_STATE 1414#if DEBUG_STATE
1643 printk("-s3-"); 1415 printk("-s3-");
1644#endif 1416#endif
1645 for (;;) { 1417 for (;;) {
1646 switch (pCurHcb->HCS_Phase) { 1418 switch (host->phase) {
1647 case CMD_OUT: /* Command out phase */ 1419 case CMD_OUT: /* Command out phase */
1648 for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++) 1420 for (i = 0; i < (int) scb->cdblen; i++)
1649 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]); 1421 outb(scb->cdb[i], host->addr + TUL_SFifo);
1650 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1422 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1651 if (wait_tulip(pCurHcb) == -1) 1423 if (wait_tulip(host) == -1)
1652 return (-1); 1424 return -1;
1653 if (pCurHcb->HCS_Phase == CMD_OUT) { 1425 if (host->phase == CMD_OUT)
1654 return (tul_bad_seq(pCurHcb)); 1426 return initio_bad_seq(host);
1655 } 1427 return 4;
1656 return (4);
1657 1428
1658 case MSG_IN: /* Message in phase */ 1429 case MSG_IN: /* Message in phase */
1659 pCurScb->SCB_NxtStat = 3; 1430 scb->next_state = 3;
1660 if (tul_msgin(pCurHcb) == -1) 1431 if (initio_msgin(host) == -1)
1661 return (-1); 1432 return -1;
1662 break; 1433 break;
1663 1434
1664 case STATUS_IN: /* Status phase */ 1435 case STATUS_IN: /* Status phase */
1665 if (tul_status_msg(pCurHcb) == -1) 1436 if (initio_status_msg(host) == -1)
1666 return (-1); 1437 return -1;
1667 break; 1438 break;
1668 1439
1669 case MSG_OUT: /* Message out phase */ 1440 case MSG_OUT: /* Message out phase */
1670 if (pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) { 1441 if (active_tc->flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) {
1671 1442 outb(MSG_NOP, host->addr + TUL_SFifo); /* msg nop */
1672 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */ 1443 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1673 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1444 if (wait_tulip(host) == -1)
1674 if (wait_tulip(pCurHcb) == -1) 1445 return -1;
1675 return (-1);
1676
1677 } else { 1446 } else {
1678 pCurTcb->TCS_Flags |= TCF_SYNC_DONE; 1447 active_tc->flags |= TCF_SYNC_DONE;
1679 1448
1680 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND); 1449 outb(MSG_EXTEND, host->addr + TUL_SFifo);
1681 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* ext. msg len */ 1450 outb(3, host->addr + TUL_SFifo); /* ext. msg len */
1682 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */ 1451 outb(1, host->addr + TUL_SFifo); /* sync request */
1683 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]); 1452 outb(initio_rate_tbl[active_tc->flags & TCF_SCSI_RATE], host->addr + TUL_SFifo);
1684 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */ 1453 outb(MAX_OFFSET, host->addr + TUL_SFifo); /* REQ/ACK offset */
1685 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1454 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1686 if (wait_tulip(pCurHcb) == -1) 1455 if (wait_tulip(host) == -1)
1687 return (-1); 1456 return -1;
1688 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1457 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
1689 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)); 1458 outb(inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7), host->addr + TUL_SSignal);
1690 1459
1691 } 1460 }
1692 break; 1461 break;
1693
1694 default: 1462 default:
1695 return (tul_bad_seq(pCurHcb)); 1463 return initio_bad_seq(host);
1696 } 1464 }
1697 } 1465 }
1698} 1466}
1699 1467
1468/**
1469 * initio_state_4 - SCSI state machine
1470 * @host: InitIO host we are controlling
1471 *
1472 * SCSI state machine. State 4
1473 */
1700 1474
1701/***************************************************************************/ 1475static int initio_state_4(struct initio_host * host)
1702int tul_state_4(HCS * pCurHcb)
1703{ 1476{
1704 SCB *pCurScb = pCurHcb->HCS_ActScb; 1477 struct scsi_ctrl_blk *scb = host->active;
1705 1478
1706#if DEBUG_STATE 1479#if DEBUG_STATE
1707 printk("-s4-"); 1480 printk("-s4-");
1708#endif 1481#endif
1709 if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_NO_XF) { 1482 if ((scb->flags & SCF_DIR) == SCF_NO_XF) {
1710 return (6); /* Go to state 6 */ 1483 return 6; /* Go to state 6 (After data) */
1711 } 1484 }
1712 for (;;) { 1485 for (;;) {
1713 if (pCurScb->SCB_BufLen == 0) 1486 if (scb->buflen == 0)
1714 return (6); /* Go to state 6 */ 1487 return 6;
1715 1488
1716 switch (pCurHcb->HCS_Phase) { 1489 switch (host->phase) {
1717 1490
1718 case STATUS_IN: /* Status phase */ 1491 case STATUS_IN: /* Status phase */
1719 if ((pCurScb->SCB_Flags & SCF_DIR) != 0) { /* if direction bit set then report data underrun */ 1492 if ((scb->flags & SCF_DIR) != 0) /* if direction bit set then report data underrun */
1720 pCurScb->SCB_HaStat = HOST_DO_DU; 1493 scb->hastat = HOST_DO_DU;
1721 } 1494 if ((initio_status_msg(host)) == -1)
1722 if ((tul_status_msg(pCurHcb)) == -1) 1495 return -1;
1723 return (-1);
1724 break; 1496 break;
1725 1497
1726 case MSG_IN: /* Message in phase */ 1498 case MSG_IN: /* Message in phase */
1727 pCurScb->SCB_NxtStat = 0x4; 1499 scb->next_state = 0x4;
1728 if (tul_msgin(pCurHcb) == -1) 1500 if (initio_msgin(host) == -1)
1729 return (-1); 1501 return -1;
1730 break; 1502 break;
1731 1503
1732 case MSG_OUT: /* Message out phase */ 1504 case MSG_OUT: /* Message out phase */
1733 if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { 1505 if (host->jsstatus0 & TSS_PAR_ERROR) {
1734 pCurScb->SCB_BufLen = 0; 1506 scb->buflen = 0;
1735 pCurScb->SCB_HaStat = HOST_DO_DU; 1507 scb->hastat = HOST_DO_DU;
1736 if (tul_msgout_ide(pCurHcb) == -1) 1508 if (initio_msgout_ide(host) == -1)
1737 return (-1); 1509 return -1;
1738 return (6); /* Go to state 6 */ 1510 return 6;
1739 } else { 1511 } else {
1740 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */ 1512 outb(MSG_NOP, host->addr + TUL_SFifo); /* msg nop */
1741 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1513 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1742 if (wait_tulip(pCurHcb) == -1) 1514 if (wait_tulip(host) == -1)
1743 return (-1); 1515 return -1;
1744 } 1516 }
1745 break; 1517 break;
1746 1518
1747 case DATA_IN: /* Data in phase */ 1519 case DATA_IN: /* Data in phase */
1748 return (tul_xfer_data_in(pCurHcb)); 1520 return initio_xfer_data_in(host);
1749 1521
1750 case DATA_OUT: /* Data out phase */ 1522 case DATA_OUT: /* Data out phase */
1751 return (tul_xfer_data_out(pCurHcb)); 1523 return initio_xfer_data_out(host);
1752 1524
1753 default: 1525 default:
1754 return (tul_bad_seq(pCurHcb)); 1526 return initio_bad_seq(host);
1755 } 1527 }
1756 } 1528 }
1757} 1529}
1758 1530
1759 1531
1760/***************************************************************************/ 1532/**
1761/* state after dma xfer done or phase change before xfer done */ 1533 * initio_state_5 - SCSI state machine
1762int tul_state_5(HCS * pCurHcb) 1534 * @host: InitIO host we are controlling
1535 *
1536 * State after dma xfer done or phase change before xfer done
1537 */
1538
1539static int initio_state_5(struct initio_host * host)
1763{ 1540{
1764 SCB *pCurScb = pCurHcb->HCS_ActScb; 1541 struct scsi_ctrl_blk *scb = host->active;
1765 long cnt, xcnt; /* cannot use unsigned !! code: if (xcnt < 0) */ 1542 long cnt, xcnt; /* cannot use unsigned !! code: if (xcnt < 0) */
1766 1543
1767#if DEBUG_STATE 1544#if DEBUG_STATE
1768 printk("-s5-"); 1545 printk("-s5-");
1769#endif 1546#endif
1770/*------ get remaining count -------*/ 1547 /*------ get remaining count -------*/
1771 1548 cnt = inl(host->addr + TUL_SCnt0) & 0x0FFFFFF;
1772 cnt = TUL_RDLONG(pCurHcb->HCS_Base, TUL_SCnt0) & 0x0FFFFFF;
1773 1549
1774 if (TUL_RD(pCurHcb->HCS_Base, TUL_XCmd) & 0x20) { 1550 if (inb(host->addr + TUL_XCmd) & 0x20) {
1775 /* ----------------------- DATA_IN ----------------------------- */ 1551 /* ----------------------- DATA_IN ----------------------------- */
1776 /* check scsi parity error */ 1552 /* check scsi parity error */
1777 if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { 1553 if (host->jsstatus0 & TSS_PAR_ERROR)
1778 pCurScb->SCB_HaStat = HOST_DO_DU; 1554 scb->hastat = HOST_DO_DU;
1779 } 1555 if (inb(host->addr + TUL_XStatus) & XPEND) { /* DMA xfer pending, Send STOP */
1780 if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* DMA xfer pending, Send STOP */
1781 /* tell Hardware scsi xfer has been terminated */ 1556 /* tell Hardware scsi xfer has been terminated */
1782 TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, TUL_RD(pCurHcb->HCS_Base, TUL_XCtrl) | 0x80); 1557 outb(inb(host->addr + TUL_XCtrl) | 0x80, host->addr + TUL_XCtrl);
1783 /* wait until DMA xfer not pending */ 1558 /* wait until DMA xfer not pending */
1784 while (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND); 1559 while (inb(host->addr + TUL_XStatus) & XPEND)
1560 cpu_relax();
1785 } 1561 }
1786 } else { 1562 } else {
1787/*-------- DATA OUT -----------*/ 1563 /*-------- DATA OUT -----------*/
1788 if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0) { 1564 if ((inb(host->addr + TUL_SStatus1) & TSS_XFER_CMP) == 0) {
1789 if (pCurHcb->HCS_ActTcs->TCS_JS_Period & TSC_WIDE_SCSI) 1565 if (host->active_tc->js_period & TSC_WIDE_SCSI)
1790 cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F) << 1; 1566 cnt += (inb(host->addr + TUL_SFifoCnt) & 0x1F) << 1;
1791 else 1567 else
1792 cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F); 1568 cnt += (inb(host->addr + TUL_SFifoCnt) & 0x1F);
1793 } 1569 }
1794 if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */ 1570 if (inb(host->addr + TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
1795 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT); 1571 outb(TAX_X_ABT, host->addr + TUL_XCmd);
1796 /* wait Abort DMA xfer done */ 1572 /* wait Abort DMA xfer done */
1797 while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0); 1573 while ((inb(host->addr + TUL_Int) & XABT) == 0)
1574 cpu_relax();
1798 } 1575 }
1799 if ((cnt == 1) && (pCurHcb->HCS_Phase == DATA_OUT)) { 1576 if ((cnt == 1) && (host->phase == DATA_OUT)) {
1800 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1577 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1801 if (wait_tulip(pCurHcb) == -1) { 1578 if (wait_tulip(host) == -1)
1802 return (-1); 1579 return -1;
1803 }
1804 cnt = 0; 1580 cnt = 0;
1805 } else { 1581 } else {
1806 if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0) 1582 if ((inb(host->addr + TUL_SStatus1) & TSS_XFER_CMP) == 0)
1807 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1583 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
1808 } 1584 }
1809 } 1585 }
1810
1811 if (cnt == 0) { 1586 if (cnt == 0) {
1812 pCurScb->SCB_BufLen = 0; 1587 scb->buflen = 0;
1813 return (6); /* Go to state 6 */ 1588 return 6; /* After Data */
1814 } 1589 }
1815 /* Update active data pointer */ 1590 /* Update active data pointer */
1816 xcnt = (long) pCurScb->SCB_BufLen - cnt; /* xcnt== bytes already xferred */ 1591 xcnt = (long) scb->buflen - cnt; /* xcnt== bytes already xferred */
1817 pCurScb->SCB_BufLen = (U32) cnt; /* cnt == bytes left to be xferred */ 1592 scb->buflen = (u32) cnt; /* cnt == bytes left to be xferred */
1818 if (pCurScb->SCB_Flags & SCF_SG) { 1593 if (scb->flags & SCF_SG) {
1819 register SG *sgp; 1594 struct sg_entry *sgp;
1820 ULONG i; 1595 unsigned long i;
1821 1596
1822 sgp = &pCurScb->SCB_SGList[pCurScb->SCB_SGIdx]; 1597 sgp = &scb->sglist[scb->sgidx];
1823 for (i = pCurScb->SCB_SGIdx; i < pCurScb->SCB_SGMax; sgp++, i++) { 1598 for (i = scb->sgidx; i < scb->sgmax; sgp++, i++) {
1824 xcnt -= (long) sgp->SG_Len; 1599 xcnt -= (long) sgp->len;
1825 if (xcnt < 0) { /* this sgp xfer half done */ 1600 if (xcnt < 0) { /* this sgp xfer half done */
1826 xcnt += (long) sgp->SG_Len; /* xcnt == bytes xferred in this sgp */ 1601 xcnt += (long) sgp->len; /* xcnt == bytes xferred in this sgp */
1827 sgp->SG_Ptr += (U32) xcnt; /* new ptr to be xfer */ 1602 sgp->data += (u32) xcnt; /* new ptr to be xfer */
1828 sgp->SG_Len -= (U32) xcnt; /* new len to be xfer */ 1603 sgp->len -= (u32) xcnt; /* new len to be xfer */
1829 pCurScb->SCB_BufPtr += ((U32) (i - pCurScb->SCB_SGIdx) << 3); 1604 scb->bufptr += ((u32) (i - scb->sgidx) << 3);
1830 /* new SG table ptr */ 1605 /* new SG table ptr */
1831 pCurScb->SCB_SGLen = (BYTE) (pCurScb->SCB_SGMax - i); 1606 scb->sglen = (u8) (scb->sgmax - i);
1832 /* new SG table len */ 1607 /* new SG table len */
1833 pCurScb->SCB_SGIdx = (WORD) i; 1608 scb->sgidx = (u16) i;
1834 /* for next disc and come in this loop */ 1609 /* for next disc and come in this loop */
1835 return (4); /* Go to state 4 */ 1610 return 4; /* Go to state 4 */
1836 } 1611 }
1837 /* else (xcnt >= 0 , i.e. this sgp already xferred */ 1612 /* else (xcnt >= 0 , i.e. this sgp already xferred */
1838 } /* for */ 1613 } /* for */
1839 return (6); /* Go to state 6 */ 1614 return 6; /* Go to state 6 */
1840 } else { 1615 } else {
1841 pCurScb->SCB_BufPtr += (U32) xcnt; 1616 scb->bufptr += (u32) xcnt;
1842 } 1617 }
1843 return (4); /* Go to state 4 */ 1618 return 4; /* Go to state 4 */
1844} 1619}
1845 1620
1846/***************************************************************************/ 1621/**
1847/* state after Data phase */ 1622 * initio_state_6 - SCSI state machine
1848int tul_state_6(HCS * pCurHcb) 1623 * @host: InitIO host we are controlling
1624 *
1625 * State after Data phase
1626 */
1627
1628static int initio_state_6(struct initio_host * host)
1849{ 1629{
1850 SCB *pCurScb = pCurHcb->HCS_ActScb; 1630 struct scsi_ctrl_blk *scb = host->active;
1851 1631
1852#if DEBUG_STATE 1632#if DEBUG_STATE
1853 printk("-s6-"); 1633 printk("-s6-");
1854#endif 1634#endif
1855 for (;;) { 1635 for (;;) {
1856 switch (pCurHcb->HCS_Phase) { 1636 switch (host->phase) {
1857 case STATUS_IN: /* Status phase */ 1637 case STATUS_IN: /* Status phase */
1858 if ((tul_status_msg(pCurHcb)) == -1) 1638 if ((initio_status_msg(host)) == -1)
1859 return (-1); 1639 return -1;
1860 break; 1640 break;
1861 1641
1862 case MSG_IN: /* Message in phase */ 1642 case MSG_IN: /* Message in phase */
1863 pCurScb->SCB_NxtStat = 6; 1643 scb->next_state = 6;
1864 if ((tul_msgin(pCurHcb)) == -1) 1644 if ((initio_msgin(host)) == -1)
1865 return (-1); 1645 return -1;
1866 break; 1646 break;
1867 1647
1868 case MSG_OUT: /* Message out phase */ 1648 case MSG_OUT: /* Message out phase */
1869 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */ 1649 outb(MSG_NOP, host->addr + TUL_SFifo); /* msg nop */
1870 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1650 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
1871 if (wait_tulip(pCurHcb) == -1) 1651 if (wait_tulip(host) == -1)
1872 return (-1); 1652 return -1;
1873 break; 1653 break;
1874 1654
1875 case DATA_IN: /* Data in phase */ 1655 case DATA_IN: /* Data in phase */
1876 return (tul_xpad_in(pCurHcb)); 1656 return initio_xpad_in(host);
1877 1657
1878 case DATA_OUT: /* Data out phase */ 1658 case DATA_OUT: /* Data out phase */
1879 return (tul_xpad_out(pCurHcb)); 1659 return initio_xpad_out(host);
1880 1660
1881 default: 1661 default:
1882 return (tul_bad_seq(pCurHcb)); 1662 return initio_bad_seq(host);
1883 } 1663 }
1884 } 1664 }
1885} 1665}
1886 1666
1887/***************************************************************************/ 1667/**
1888int tul_state_7(HCS * pCurHcb) 1668 * initio_state_7 - SCSI state machine
1669 * @host: InitIO host we are controlling
1670 *
1671 */
1672
1673int initio_state_7(struct initio_host * host)
1889{ 1674{
1890 int cnt, i; 1675 int cnt, i;
1891 1676
@@ -1893,1139 +1678,1037 @@ int tul_state_7(HCS * pCurHcb)
1893 printk("-s7-"); 1678 printk("-s7-");
1894#endif 1679#endif
1895 /* flush SCSI FIFO */ 1680 /* flush SCSI FIFO */
1896 cnt = TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F; 1681 cnt = inb(host->addr + TUL_SFifoCnt) & 0x1F;
1897 if (cnt) { 1682 if (cnt) {
1898 for (i = 0; i < cnt; i++) 1683 for (i = 0; i < cnt; i++)
1899 TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); 1684 inb(host->addr + TUL_SFifo);
1900 } 1685 }
1901 switch (pCurHcb->HCS_Phase) { 1686 switch (host->phase) {
1902 case DATA_IN: /* Data in phase */ 1687 case DATA_IN: /* Data in phase */
1903 case DATA_OUT: /* Data out phase */ 1688 case DATA_OUT: /* Data out phase */
1904 return (tul_bad_seq(pCurHcb)); 1689 return initio_bad_seq(host);
1905 default: 1690 default:
1906 return (6); /* Go to state 6 */ 1691 return 6; /* Go to state 6 */
1907 } 1692 }
1908} 1693}
1909 1694
1910/***************************************************************************/ 1695/**
1911int tul_xfer_data_in(HCS * pCurHcb) 1696 * initio_xfer_data_in - Commence data input
1697 * @host: InitIO host in use
1698 *
1699 * Commence a block of data transfer. The transfer itself will
1700 * be managed by the controller and we will get a completion (or
1701 * failure) interrupt.
1702 */
1703static int initio_xfer_data_in(struct initio_host * host)
1912{ 1704{
1913 SCB *pCurScb = pCurHcb->HCS_ActScb; 1705 struct scsi_ctrl_blk *scb = host->active;
1914 1706
1915 if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DOUT) { 1707 if ((scb->flags & SCF_DIR) == SCF_DOUT)
1916 return (6); /* wrong direction */ 1708 return 6; /* wrong direction */
1917 }
1918 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
1919 1709
1920 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_IN); /* 7/25/95 */ 1710 outl(scb->buflen, host->addr + TUL_SCnt0);
1711 outb(TSC_XF_DMA_IN, host->addr + TUL_SCmd); /* 7/25/95 */
1921 1712
1922 if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */ 1713 if (scb->flags & SCF_SG) { /* S/G xfer */
1923 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3); 1714 outl(((u32) scb->sglen) << 3, host->addr + TUL_XCntH);
1924 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr); 1715 outl(scb->bufptr, host->addr + TUL_XAddH);
1925 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_IN); 1716 outb(TAX_SG_IN, host->addr + TUL_XCmd);
1926 } else { 1717 } else {
1927 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen); 1718 outl(scb->buflen, host->addr + TUL_XCntH);
1928 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr); 1719 outl(scb->bufptr, host->addr + TUL_XAddH);
1929 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_IN); 1720 outb(TAX_X_IN, host->addr + TUL_XCmd);
1930 } 1721 }
1931 pCurScb->SCB_NxtStat = 0x5; 1722 scb->next_state = 0x5;
1932 return (0); /* return to OS, wait xfer done , let jas_isr come in */ 1723 return 0; /* return to OS, wait xfer done , let jas_isr come in */
1933} 1724}
1934 1725
1726/**
1727 * initio_xfer_data_out - Commence data output
1728 * @host: InitIO host in use
1729 *
1730 * Commence a block of data transfer. The transfer itself will
1731 * be managed by the controller and we will get a completion (or
1732 * failure) interrupt.
1733 */
1935 1734
1936/***************************************************************************/ 1735static int initio_xfer_data_out(struct initio_host * host)
1937int tul_xfer_data_out(HCS * pCurHcb)
1938{ 1736{
1939 SCB *pCurScb = pCurHcb->HCS_ActScb; 1737 struct scsi_ctrl_blk *scb = host->active;
1940 1738
1941 if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DIN) { 1739 if ((scb->flags & SCF_DIR) == SCF_DIN)
1942 return (6); /* wrong direction */ 1740 return 6; /* wrong direction */
1943 }
1944 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
1945 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_OUT);
1946 1741
1947 if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */ 1742 outl(scb->buflen, host->addr + TUL_SCnt0);
1948 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3); 1743 outb(TSC_XF_DMA_OUT, host->addr + TUL_SCmd);
1949 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr); 1744
1950 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_OUT); 1745 if (scb->flags & SCF_SG) { /* S/G xfer */
1746 outl(((u32) scb->sglen) << 3, host->addr + TUL_XCntH);
1747 outl(scb->bufptr, host->addr + TUL_XAddH);
1748 outb(TAX_SG_OUT, host->addr + TUL_XCmd);
1951 } else { 1749 } else {
1952 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen); 1750 outl(scb->buflen, host->addr + TUL_XCntH);
1953 TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr); 1751 outl(scb->bufptr, host->addr + TUL_XAddH);
1954 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_OUT); 1752 outb(TAX_X_OUT, host->addr + TUL_XCmd);
1955 } 1753 }
1956 1754
1957 pCurScb->SCB_NxtStat = 0x5; 1755 scb->next_state = 0x5;
1958 return (0); /* return to OS, wait xfer done , let jas_isr come in */ 1756 return 0; /* return to OS, wait xfer done , let jas_isr come in */
1959} 1757}
1960 1758
1961 1759int initio_xpad_in(struct initio_host * host)
1962/***************************************************************************/
1963int tul_xpad_in(HCS * pCurHcb)
1964{ 1760{
1965 SCB *pCurScb = pCurHcb->HCS_ActScb; 1761 struct scsi_ctrl_blk *scb = host->active;
1966 TCS *pCurTcb = pCurHcb->HCS_ActTcs; 1762 struct target_control *active_tc = host->active_tc;
1967 1763
1968 if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) { 1764 if ((scb->flags & SCF_DIR) != SCF_NO_DCHK)
1969 pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */ 1765 scb->hastat = HOST_DO_DU; /* over run */
1970 }
1971 for (;;) { 1766 for (;;) {
1972 if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI) 1767 if (active_tc->js_period & TSC_WIDE_SCSI)
1973 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2); 1768 outl(2, host->addr + TUL_SCnt0);
1974 else 1769 else
1975 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 1770 outl(1, host->addr + TUL_SCnt0);
1976 1771
1977 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN); 1772 outb(TSC_XF_FIFO_IN, host->addr + TUL_SCmd);
1978 if ((wait_tulip(pCurHcb)) == -1) { 1773 if (wait_tulip(host) == -1)
1979 return (-1); 1774 return -1;
1775 if (host->phase != DATA_IN) {
1776 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
1777 return 6;
1980 } 1778 }
1981 if (pCurHcb->HCS_Phase != DATA_IN) { 1779 inb(host->addr + TUL_SFifo);
1982 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
1983 return (6);
1984 }
1985 TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
1986 } 1780 }
1987} 1781}
1988 1782
1989int tul_xpad_out(HCS * pCurHcb) 1783int initio_xpad_out(struct initio_host * host)
1990{ 1784{
1991 SCB *pCurScb = pCurHcb->HCS_ActScb; 1785 struct scsi_ctrl_blk *scb = host->active;
1992 TCS *pCurTcb = pCurHcb->HCS_ActTcs; 1786 struct target_control *active_tc = host->active_tc;
1993 1787
1994 if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) { 1788 if ((scb->flags & SCF_DIR) != SCF_NO_DCHK)
1995 pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */ 1789 scb->hastat = HOST_DO_DU; /* over run */
1996 }
1997 for (;;) { 1790 for (;;) {
1998 if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI) 1791 if (active_tc->js_period & TSC_WIDE_SCSI)
1999 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2); 1792 outl(2, host->addr + TUL_SCnt0);
2000 else 1793 else
2001 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 1794 outl(1, host->addr + TUL_SCnt0);
2002 1795
2003 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0); 1796 outb(0, host->addr + TUL_SFifo);
2004 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1797 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2005 if ((wait_tulip(pCurHcb)) == -1) { 1798 if ((wait_tulip(host)) == -1)
2006 return (-1); 1799 return -1;
2007 } 1800 if (host->phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */
2008 if (pCurHcb->HCS_Phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */ 1801 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1);
2009 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); 1802 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
2010 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1803 return 6;
2011 return (6);
2012 } 1804 }
2013 } 1805 }
2014} 1806}
2015 1807
2016 1808int initio_status_msg(struct initio_host * host)
2017/***************************************************************************/
2018int tul_status_msg(HCS * pCurHcb)
2019{ /* status & MSG_IN */ 1809{ /* status & MSG_IN */
2020 SCB *pCurScb = pCurHcb->HCS_ActScb; 1810 struct scsi_ctrl_blk *scb = host->active;
2021 BYTE msg; 1811 u8 msg;
1812
1813 outb(TSC_CMD_COMP, host->addr + TUL_SCmd);
1814 if (wait_tulip(host) == -1)
1815 return -1;
2022 1816
2023 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_CMD_COMP);
2024 if ((wait_tulip(pCurHcb)) == -1) {
2025 return (-1);
2026 }
2027 /* get status */ 1817 /* get status */
2028 pCurScb->SCB_TaStat = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); 1818 scb->tastat = inb(host->addr + TUL_SFifo);
2029 1819
2030 if (pCurHcb->HCS_Phase == MSG_OUT) { 1820 if (host->phase == MSG_OUT) {
2031 if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { 1821 if (host->jsstatus0 & TSS_PAR_ERROR)
2032 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY); 1822 outb(MSG_PARITY, host->addr + TUL_SFifo);
2033 } else { 1823 else
2034 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); 1824 outb(MSG_NOP, host->addr + TUL_SFifo);
2035 } 1825 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2036 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1826 return wait_tulip(host);
2037 return (wait_tulip(pCurHcb)); 1827 }
2038 } 1828 if (host->phase == MSG_IN) {
2039 if (pCurHcb->HCS_Phase == MSG_IN) { 1829 msg = inb(host->addr + TUL_SFifo);
2040 msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); 1830 if (host->jsstatus0 & TSS_PAR_ERROR) { /* Parity error */
2041 if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { /* Parity error */ 1831 if ((initio_msgin_accept(host)) == -1)
2042 if ((tul_msgin_accept(pCurHcb)) == -1) 1832 return -1;
2043 return (-1); 1833 if (host->phase != MSG_OUT)
2044 if (pCurHcb->HCS_Phase != MSG_OUT) 1834 return initio_bad_seq(host);
2045 return (tul_bad_seq(pCurHcb)); 1835 outb(MSG_PARITY, host->addr + TUL_SFifo);
2046 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY); 1836 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2047 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 1837 return wait_tulip(host);
2048 return (wait_tulip(pCurHcb));
2049 } 1838 }
2050 if (msg == 0) { /* Command complete */ 1839 if (msg == 0) { /* Command complete */
2051 1840
2052 if ((pCurScb->SCB_TaStat & 0x18) == 0x10) { /* No link support */ 1841 if ((scb->tastat & 0x18) == 0x10) /* No link support */
2053 return (tul_bad_seq(pCurHcb)); 1842 return initio_bad_seq(host);
2054 } 1843 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
2055 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1844 outb(TSC_MSG_ACCEPT, host->addr + TUL_SCmd);
2056 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT); 1845 return initio_wait_done_disc(host);
2057 return tul_wait_done_disc(pCurHcb);
2058 1846
2059 } 1847 }
2060 if ((msg == MSG_LINK_COMP) || (msg == MSG_LINK_FLAG)) { 1848 if (msg == MSG_LINK_COMP || msg == MSG_LINK_FLAG) {
2061 if ((pCurScb->SCB_TaStat & 0x18) == 0x10) 1849 if ((scb->tastat & 0x18) == 0x10)
2062 return (tul_msgin_accept(pCurHcb)); 1850 return initio_msgin_accept(host);
2063 } 1851 }
2064 } 1852 }
2065 return (tul_bad_seq(pCurHcb)); 1853 return initio_bad_seq(host);
2066} 1854}
2067 1855
2068 1856
2069/***************************************************************************/
2070/* scsi bus free */ 1857/* scsi bus free */
2071int int_tul_busfree(HCS * pCurHcb) 1858int int_initio_busfree(struct initio_host * host)
2072{ 1859{
2073 SCB *pCurScb = pCurHcb->HCS_ActScb; 1860 struct scsi_ctrl_blk *scb = host->active;
2074 1861
2075 if (pCurScb != NULL) { 1862 if (scb != NULL) {
2076 if (pCurScb->SCB_Status & SCB_SELECT) { /* selection timeout */ 1863 if (scb->status & SCB_SELECT) { /* selection timeout */
2077 tul_unlink_pend_scb(pCurHcb, pCurScb); 1864 initio_unlink_pend_scb(host, scb);
2078 pCurScb->SCB_HaStat = HOST_SEL_TOUT; 1865 scb->hastat = HOST_SEL_TOUT;
2079 tul_append_done_scb(pCurHcb, pCurScb); 1866 initio_append_done_scb(host, scb);
2080 } else { /* Unexpected bus free */ 1867 } else { /* Unexpected bus free */
2081 tul_unlink_busy_scb(pCurHcb, pCurScb); 1868 initio_unlink_busy_scb(host, scb);
2082 pCurScb->SCB_HaStat = HOST_BUS_FREE; 1869 scb->hastat = HOST_BUS_FREE;
2083 tul_append_done_scb(pCurHcb, pCurScb); 1870 initio_append_done_scb(host, scb);
2084 } 1871 }
2085 pCurHcb->HCS_ActScb = NULL; 1872 host->active = NULL;
2086 pCurHcb->HCS_ActTcs = NULL; 1873 host->active_tc = NULL;
2087 } 1874 }
2088 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */ 1875 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0); /* Flush SCSI FIFO */
2089 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT); 1876 outb(TSC_INITDEFAULT, host->addr + TUL_SConfig);
2090 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */ 1877 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1); /* Enable HW reselect */
2091 return (-1); 1878 return -1;
2092} 1879}
2093 1880
2094 1881
2095/***************************************************************************/ 1882/**
2096/* scsi bus reset */ 1883 * int_initio_scsi_rst - SCSI reset occurred
2097static int int_tul_scsi_rst(HCS * pCurHcb) 1884 * @host: Host seeing the reset
1885 *
1886 * A SCSI bus reset has occurred. Clean up any pending transfer
1887 * the hardware is doing by DMA and then abort all active and
1888 * disconnected commands. The mid layer should sort the rest out
1889 * for us
1890 */
1891
1892static int int_initio_scsi_rst(struct initio_host * host)
2098{ 1893{
2099 SCB *pCurScb; 1894 struct scsi_ctrl_blk *scb;
2100 int i; 1895 int i;
2101 1896
2102 /* if DMA xfer is pending, abort DMA xfer */ 1897 /* if DMA xfer is pending, abort DMA xfer */
2103 if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & 0x01) { 1898 if (inb(host->addr + TUL_XStatus) & 0x01) {
2104 TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO); 1899 outb(TAX_X_ABT | TAX_X_CLR_FIFO, host->addr + TUL_XCmd);
2105 /* wait Abort DMA xfer done */ 1900 /* wait Abort DMA xfer done */
2106 while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & 0x04) == 0); 1901 while ((inb(host->addr + TUL_Int) & 0x04) == 0)
2107 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 1902 cpu_relax();
1903 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
2108 } 1904 }
2109 /* Abort all active & disconnected scb */ 1905 /* Abort all active & disconnected scb */
2110 while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) { 1906 while ((scb = initio_pop_busy_scb(host)) != NULL) {
2111 pCurScb->SCB_HaStat = HOST_BAD_PHAS; 1907 scb->hastat = HOST_BAD_PHAS;
2112 tul_append_done_scb(pCurHcb, pCurScb); 1908 initio_append_done_scb(host, scb);
2113 } 1909 }
2114 pCurHcb->HCS_ActScb = NULL; 1910 host->active = NULL;
2115 pCurHcb->HCS_ActTcs = NULL; 1911 host->active_tc = NULL;
2116 1912
2117 /* clr sync nego. done flag */ 1913 /* clr sync nego. done flag */
2118 for (i = 0; i < pCurHcb->HCS_MaxTar; i++) { 1914 for (i = 0; i < host->max_tar; i++)
2119 pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE); 1915 host->targets[i].flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
2120 } 1916 return -1;
2121 return (-1);
2122} 1917}
2123 1918
1919/**
1920 * int_initio_scsi_resel - Reselection occured
1921 * @host: InitIO host adapter
1922 *
1923 * A SCSI reselection event has been signalled and the interrupt
1924 * is now being processed. Work out which command block needs attention
1925 * and continue processing that command.
1926 */
2124 1927
2125/***************************************************************************/ 1928int int_initio_resel(struct initio_host * host)
2126/* scsi reselection */
2127int int_tul_resel(HCS * pCurHcb)
2128{ 1929{
2129 SCB *pCurScb; 1930 struct scsi_ctrl_blk *scb;
2130 TCS *pCurTcb; 1931 struct target_control *active_tc;
2131 BYTE tag, msg = 0; 1932 u8 tag, msg = 0;
2132 BYTE tar, lun; 1933 u8 tar, lun;
2133 1934
2134 if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) { 1935 if ((scb = host->active) != NULL) {
2135 if (pCurScb->SCB_Status & SCB_SELECT) { /* if waiting for selection complete */ 1936 /* FIXME: Why check and not just clear ? */
2136 pCurScb->SCB_Status &= ~SCB_SELECT; 1937 if (scb->status & SCB_SELECT) /* if waiting for selection complete */
2137 } 1938 scb->status &= ~SCB_SELECT;
2138 pCurHcb->HCS_ActScb = NULL; 1939 host->active = NULL;
2139 } 1940 }
2140 /* --------- get target id---------------------- */ 1941 /* --------- get target id---------------------- */
2141 tar = TUL_RD(pCurHcb->HCS_Base, TUL_SBusId); 1942 tar = inb(host->addr + TUL_SBusId);
2142 /* ------ get LUN from Identify message----------- */ 1943 /* ------ get LUN from Identify message----------- */
2143 lun = TUL_RD(pCurHcb->HCS_Base, TUL_SIdent) & 0x0F; 1944 lun = inb(host->addr + TUL_SIdent) & 0x0F;
2144 /* 07/22/98 from 0x1F -> 0x0F */ 1945 /* 07/22/98 from 0x1F -> 0x0F */
2145 pCurTcb = &pCurHcb->HCS_Tcs[tar]; 1946 active_tc = &host->targets[tar];
2146 pCurHcb->HCS_ActTcs = pCurTcb; 1947 host->active_tc = active_tc;
2147 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0); 1948 outb(active_tc->sconfig0, host->addr + TUL_SConfig);
2148 TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period); 1949 outb(active_tc->js_period, host->addr + TUL_SPeriod);
2149
2150 1950
2151 /* ------------- tag queueing ? ------------------- */ 1951 /* ------------- tag queueing ? ------------------- */
2152 if (pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG) { 1952 if (active_tc->drv_flags & TCF_DRV_EN_TAG) {
2153 if ((tul_msgin_accept(pCurHcb)) == -1) 1953 if ((initio_msgin_accept(host)) == -1)
2154 return (-1); 1954 return -1;
2155 if (pCurHcb->HCS_Phase != MSG_IN) 1955 if (host->phase != MSG_IN)
2156 goto no_tag; 1956 goto no_tag;
2157 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 1957 outl(1, host->addr + TUL_SCnt0);
2158 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN); 1958 outb(TSC_XF_FIFO_IN, host->addr + TUL_SCmd);
2159 if ((wait_tulip(pCurHcb)) == -1) 1959 if (wait_tulip(host) == -1)
2160 return (-1); 1960 return -1;
2161 msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag Message */ 1961 msg = inb(host->addr + TUL_SFifo); /* Read Tag Message */
2162 1962
2163 if ((msg < MSG_STAG) || (msg > MSG_OTAG)) /* Is simple Tag */ 1963 if (msg < MSG_STAG || msg > MSG_OTAG) /* Is simple Tag */
2164 goto no_tag; 1964 goto no_tag;
2165 1965
2166 if ((tul_msgin_accept(pCurHcb)) == -1) 1966 if (initio_msgin_accept(host) == -1)
2167 return (-1); 1967 return -1;
2168 1968
2169 if (pCurHcb->HCS_Phase != MSG_IN) 1969 if (host->phase != MSG_IN)
2170 goto no_tag; 1970 goto no_tag;
2171 1971
2172 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 1972 outl(1, host->addr + TUL_SCnt0);
2173 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN); 1973 outb(TSC_XF_FIFO_IN, host->addr + TUL_SCmd);
2174 if ((wait_tulip(pCurHcb)) == -1) 1974 if (wait_tulip(host) == -1)
2175 return (-1); 1975 return -1;
2176 tag = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag ID */ 1976 tag = inb(host->addr + TUL_SFifo); /* Read Tag ID */
2177 pCurScb = pCurHcb->HCS_Scb + tag; 1977 scb = host->scb + tag;
2178 if ((pCurScb->SCB_Target != tar) || (pCurScb->SCB_Lun != lun)) { 1978 if (scb->target != tar || scb->lun != lun) {
2179 return tul_msgout_abort_tag(pCurHcb); 1979 return initio_msgout_abort_tag(host);
2180 } 1980 }
2181 if (pCurScb->SCB_Status != SCB_BUSY) { /* 03/24/95 */ 1981 if (scb->status != SCB_BUSY) { /* 03/24/95 */
2182 return tul_msgout_abort_tag(pCurHcb); 1982 return initio_msgout_abort_tag(host);
2183 } 1983 }
2184 pCurHcb->HCS_ActScb = pCurScb; 1984 host->active = scb;
2185 if ((tul_msgin_accept(pCurHcb)) == -1) 1985 if ((initio_msgin_accept(host)) == -1)
2186 return (-1); 1986 return -1;
2187 } else { /* No tag */ 1987 } else { /* No tag */
2188 no_tag: 1988 no_tag:
2189 if ((pCurScb = tul_find_busy_scb(pCurHcb, tar | (lun << 8))) == NULL) { 1989 if ((scb = initio_find_busy_scb(host, tar | (lun << 8))) == NULL) {
2190 return tul_msgout_abort_targ(pCurHcb); 1990 return initio_msgout_abort_targ(host);
2191 } 1991 }
2192 pCurHcb->HCS_ActScb = pCurScb; 1992 host->active = scb;
2193 if (!(pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG)) { 1993 if (!(active_tc->drv_flags & TCF_DRV_EN_TAG)) {
2194 if ((tul_msgin_accept(pCurHcb)) == -1) 1994 if ((initio_msgin_accept(host)) == -1)
2195 return (-1); 1995 return -1;
2196 } 1996 }
2197 } 1997 }
2198 return 0; 1998 return 0;
2199} 1999}
2200 2000
2001/**
2002 * int_initio_bad_seq - out of phase
2003 * @host: InitIO host flagging event
2004 *
2005 * We have ended up out of phase somehow. Reset the host controller
2006 * and throw all our toys out of the pram. Let the midlayer clean up
2007 */
2201 2008
2202/***************************************************************************/ 2009static int int_initio_bad_seq(struct initio_host * host)
2203static int int_tul_bad_seq(HCS * pCurHcb)
2204{ /* target wrong phase */ 2010{ /* target wrong phase */
2205 SCB *pCurScb; 2011 struct scsi_ctrl_blk *scb;
2206 int i; 2012 int i;
2207 2013
2208 tul_reset_scsi(pCurHcb, 10); 2014 initio_reset_scsi(host, 10);
2209 2015
2210 while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) { 2016 while ((scb = initio_pop_busy_scb(host)) != NULL) {
2211 pCurScb->SCB_HaStat = HOST_BAD_PHAS; 2017 scb->hastat = HOST_BAD_PHAS;
2212 tul_append_done_scb(pCurHcb, pCurScb); 2018 initio_append_done_scb(host, scb);
2213 }
2214 for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
2215 pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
2216 } 2019 }
2217 return (-1); 2020 for (i = 0; i < host->max_tar; i++)
2021 host->targets[i].flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
2022 return -1;
2218} 2023}
2219 2024
2220 2025
2221/***************************************************************************/ 2026/**
2222int tul_msgout_abort_targ(HCS * pCurHcb) 2027 * initio_msgout_abort_targ - abort a tag
2028 * @host: InitIO host
2029 *
2030 * Abort when the target/lun does not match or when our SCB is not
2031 * busy. Used by untagged commands.
2032 */
2033
2034static int initio_msgout_abort_targ(struct initio_host * host)
2223{ 2035{
2224 2036
2225 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2037 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal);
2226 if (tul_msgin_accept(pCurHcb) == -1) 2038 if (initio_msgin_accept(host) == -1)
2227 return (-1); 2039 return -1;
2228 if (pCurHcb->HCS_Phase != MSG_OUT) 2040 if (host->phase != MSG_OUT)
2229 return (tul_bad_seq(pCurHcb)); 2041 return initio_bad_seq(host);
2230 2042
2231 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT); 2043 outb(MSG_ABORT, host->addr + TUL_SFifo);
2232 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2044 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2233 2045
2234 return tul_wait_disc(pCurHcb); 2046 return initio_wait_disc(host);
2235} 2047}
2236 2048
2237/***************************************************************************/ 2049/**
2238int tul_msgout_abort_tag(HCS * pCurHcb) 2050 * initio_msgout_abort_tag - abort a tag
2051 * @host: InitIO host
2052 *
2053 * Abort when the target/lun does not match or when our SCB is not
2054 * busy. Used for tagged commands.
2055 */
2056
2057static int initio_msgout_abort_tag(struct initio_host * host)
2239{ 2058{
2240 2059
2241 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2060 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal);
2242 if (tul_msgin_accept(pCurHcb) == -1) 2061 if (initio_msgin_accept(host) == -1)
2243 return (-1); 2062 return -1;
2244 if (pCurHcb->HCS_Phase != MSG_OUT) 2063 if (host->phase != MSG_OUT)
2245 return (tul_bad_seq(pCurHcb)); 2064 return initio_bad_seq(host);
2246 2065
2247 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT_TAG); 2066 outb(MSG_ABORT_TAG, host->addr + TUL_SFifo);
2248 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2067 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2249 2068
2250 return tul_wait_disc(pCurHcb); 2069 return initio_wait_disc(host);
2251 2070
2252} 2071}
2253 2072
2254/***************************************************************************/ 2073/**
2255int tul_msgin(HCS * pCurHcb) 2074 * initio_msgin - Message in
2075 * @host: InitIO Host
2076 *
2077 * Process incoming message
2078 */
2079static int initio_msgin(struct initio_host * host)
2256{ 2080{
2257 TCS *pCurTcb; 2081 struct target_control *active_tc;
2258 2082
2259 for (;;) { 2083 for (;;) {
2084 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
2260 2085
2261 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 2086 outl(1, host->addr + TUL_SCnt0);
2262 2087 outb(TSC_XF_FIFO_IN, host->addr + TUL_SCmd);
2263 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 2088 if (wait_tulip(host) == -1)
2264 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN); 2089 return -1;
2265 if ((wait_tulip(pCurHcb)) == -1)
2266 return (-1);
2267 2090
2268 switch (TUL_RD(pCurHcb->HCS_Base, TUL_SFifo)) { 2091 switch (inb(host->addr + TUL_SFifo)) {
2269 case MSG_DISC: /* Disconnect msg */ 2092 case MSG_DISC: /* Disconnect msg */
2270 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT); 2093 outb(TSC_MSG_ACCEPT, host->addr + TUL_SCmd);
2271 2094 return initio_wait_disc(host);
2272 return tul_wait_disc(pCurHcb);
2273
2274 case MSG_SDP: 2095 case MSG_SDP:
2275 case MSG_RESTORE: 2096 case MSG_RESTORE:
2276 case MSG_NOP: 2097 case MSG_NOP:
2277 tul_msgin_accept(pCurHcb); 2098 initio_msgin_accept(host);
2278 break; 2099 break;
2279
2280 case MSG_REJ: /* Clear ATN first */ 2100 case MSG_REJ: /* Clear ATN first */
2281 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, 2101 outb((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)),
2282 (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7))); 2102 host->addr + TUL_SSignal);
2283 pCurTcb = pCurHcb->HCS_ActTcs; 2103 active_tc = host->active_tc;
2284 if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync nego */ 2104 if ((active_tc->flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) /* do sync nego */
2285 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2105 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN),
2286 } 2106 host->addr + TUL_SSignal);
2287 tul_msgin_accept(pCurHcb); 2107 initio_msgin_accept(host);
2288 break; 2108 break;
2289
2290 case MSG_EXTEND: /* extended msg */ 2109 case MSG_EXTEND: /* extended msg */
2291 tul_msgin_extend(pCurHcb); 2110 initio_msgin_extend(host);
2292 break; 2111 break;
2293
2294 case MSG_IGNOREWIDE: 2112 case MSG_IGNOREWIDE:
2295 tul_msgin_accept(pCurHcb); 2113 initio_msgin_accept(host);
2296 break; 2114 break;
2297
2298 /* get */
2299 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
2300 if (wait_tulip(pCurHcb) == -1)
2301 return -1;
2302
2303 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0); /* put pad */
2304 TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get IGNORE field */
2305 TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get pad */
2306
2307 tul_msgin_accept(pCurHcb);
2308 break;
2309
2310 case MSG_COMP: 2115 case MSG_COMP:
2311 { 2116 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
2312 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 2117 outb(TSC_MSG_ACCEPT, host->addr + TUL_SCmd);
2313 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT); 2118 return initio_wait_done_disc(host);
2314 return tul_wait_done_disc(pCurHcb);
2315 }
2316 default: 2119 default:
2317 tul_msgout_reject(pCurHcb); 2120 initio_msgout_reject(host);
2318 break; 2121 break;
2319 } 2122 }
2320 if (pCurHcb->HCS_Phase != MSG_IN) 2123 if (host->phase != MSG_IN)
2321 return (pCurHcb->HCS_Phase); 2124 return host->phase;
2322 } 2125 }
2323 /* statement won't reach here */ 2126 /* statement won't reach here */
2324} 2127}
2325 2128
2326 2129static int initio_msgout_reject(struct initio_host * host)
2327
2328
2329/***************************************************************************/
2330int tul_msgout_reject(HCS * pCurHcb)
2331{ 2130{
2131 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal);
2332 2132
2333 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2133 if (initio_msgin_accept(host) == -1)
2334 2134 return -1;
2335 if ((tul_msgin_accept(pCurHcb)) == -1)
2336 return (-1);
2337 2135
2338 if (pCurHcb->HCS_Phase == MSG_OUT) { 2136 if (host->phase == MSG_OUT) {
2339 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_REJ); /* Msg reject */ 2137 outb(MSG_REJ, host->addr + TUL_SFifo); /* Msg reject */
2340 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2138 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2341 return (wait_tulip(pCurHcb)); 2139 return wait_tulip(host);
2342 } 2140 }
2343 return (pCurHcb->HCS_Phase); 2141 return host->phase;
2344} 2142}
2345 2143
2346 2144static int initio_msgout_ide(struct initio_host * host)
2347
2348/***************************************************************************/
2349int tul_msgout_ide(HCS * pCurHcb)
2350{ 2145{
2351 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_IDE); /* Initiator Detected Error */ 2146 outb(MSG_IDE, host->addr + TUL_SFifo); /* Initiator Detected Error */
2352 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2147 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2353 return (wait_tulip(pCurHcb)); 2148 return wait_tulip(host);
2354} 2149}
2355 2150
2356 2151static int initio_msgin_extend(struct initio_host * host)
2357/***************************************************************************/
2358int tul_msgin_extend(HCS * pCurHcb)
2359{ 2152{
2360 BYTE len, idx; 2153 u8 len, idx;
2361 2154
2362 if (tul_msgin_accept(pCurHcb) != MSG_IN) 2155 if (initio_msgin_accept(host) != MSG_IN)
2363 return (pCurHcb->HCS_Phase); 2156 return host->phase;
2364 2157
2365 /* Get extended msg length */ 2158 /* Get extended msg length */
2366 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 2159 outl(1, host->addr + TUL_SCnt0);
2367 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN); 2160 outb(TSC_XF_FIFO_IN, host->addr + TUL_SCmd);
2368 if (wait_tulip(pCurHcb) == -1) 2161 if (wait_tulip(host) == -1)
2369 return (-1); 2162 return -1;
2370 2163
2371 len = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); 2164 len = inb(host->addr + TUL_SFifo);
2372 pCurHcb->HCS_Msg[0] = len; 2165 host->msg[0] = len;
2373 for (idx = 1; len != 0; len--) { 2166 for (idx = 1; len != 0; len--) {
2374 2167
2375 if ((tul_msgin_accept(pCurHcb)) != MSG_IN) 2168 if ((initio_msgin_accept(host)) != MSG_IN)
2376 return (pCurHcb->HCS_Phase); 2169 return host->phase;
2377 TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1); 2170 outl(1, host->addr + TUL_SCnt0);
2378 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN); 2171 outb(TSC_XF_FIFO_IN, host->addr + TUL_SCmd);
2379 if (wait_tulip(pCurHcb) == -1) 2172 if (wait_tulip(host) == -1)
2380 return (-1); 2173 return -1;
2381 pCurHcb->HCS_Msg[idx++] = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); 2174 host->msg[idx++] = inb(host->addr + TUL_SFifo);
2382 } 2175 }
2383 if (pCurHcb->HCS_Msg[1] == 1) { /* if it's synchronous data transfer request */ 2176 if (host->msg[1] == 1) { /* if it's synchronous data transfer request */
2384 if (pCurHcb->HCS_Msg[0] != 3) /* if length is not right */ 2177 u8 r;
2385 return (tul_msgout_reject(pCurHcb)); 2178 if (host->msg[0] != 3) /* if length is not right */
2386 if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_SYNC_NEGO) { /* Set OFFSET=0 to do async, nego back */ 2179 return initio_msgout_reject(host);
2387 pCurHcb->HCS_Msg[3] = 0; 2180 if (host->active_tc->flags & TCF_NO_SYNC_NEGO) { /* Set OFFSET=0 to do async, nego back */
2181 host->msg[3] = 0;
2388 } else { 2182 } else {
2389 if ((tul_msgin_sync(pCurHcb) == 0) && 2183 if (initio_msgin_sync(host) == 0 &&
2390 (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SYNC_DONE)) { 2184 (host->active_tc->flags & TCF_SYNC_DONE)) {
2391 tul_sync_done(pCurHcb); 2185 initio_sync_done(host);
2392 return (tul_msgin_accept(pCurHcb)); 2186 return initio_msgin_accept(host);
2393 } 2187 }
2394 } 2188 }
2395 2189
2396 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2190 r = inb(host->addr + TUL_SSignal);
2397 if ((tul_msgin_accept(pCurHcb)) != MSG_OUT) 2191 outb((r & (TSC_SET_ACK | 7)) | TSC_SET_ATN,
2398 return (pCurHcb->HCS_Phase); 2192 host->addr + TUL_SSignal);
2193 if (initio_msgin_accept(host) != MSG_OUT)
2194 return host->phase;
2399 /* sync msg out */ 2195 /* sync msg out */
2400 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); 2196 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0);
2401 2197
2402 tul_sync_done(pCurHcb); 2198 initio_sync_done(host);
2403 2199
2404 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND); 2200 outb(MSG_EXTEND, host->addr + TUL_SFifo);
2405 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); 2201 outb(3, host->addr + TUL_SFifo);
2406 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); 2202 outb(1, host->addr + TUL_SFifo);
2407 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]); 2203 outb(host->msg[2], host->addr + TUL_SFifo);
2408 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[3]); 2204 outb(host->msg[3], host->addr + TUL_SFifo);
2409 2205 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2410 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2206 return wait_tulip(host);
2411 return (wait_tulip(pCurHcb));
2412 } 2207 }
2413 if ((pCurHcb->HCS_Msg[0] != 2) || (pCurHcb->HCS_Msg[1] != 3)) 2208 if (host->msg[0] != 2 || host->msg[1] != 3)
2414 return (tul_msgout_reject(pCurHcb)); 2209 return initio_msgout_reject(host);
2415 /* if it's WIDE DATA XFER REQ */ 2210 /* if it's WIDE DATA XFER REQ */
2416 if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) { 2211 if (host->active_tc->flags & TCF_NO_WDTR) {
2417 pCurHcb->HCS_Msg[2] = 0; 2212 host->msg[2] = 0;
2418 } else { 2213 } else {
2419 if (pCurHcb->HCS_Msg[2] > 2) /* > 32 bits */ 2214 if (host->msg[2] > 2) /* > 32 bits */
2420 return (tul_msgout_reject(pCurHcb)); 2215 return initio_msgout_reject(host);
2421 if (pCurHcb->HCS_Msg[2] == 2) { /* == 32 */ 2216 if (host->msg[2] == 2) { /* == 32 */
2422 pCurHcb->HCS_Msg[2] = 1; 2217 host->msg[2] = 1;
2423 } else { 2218 } else {
2424 if ((pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) == 0) { 2219 if ((host->active_tc->flags & TCF_NO_WDTR) == 0) {
2425 wdtr_done(pCurHcb); 2220 wdtr_done(host);
2426 if ((pCurHcb->HCS_ActTcs->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) 2221 if ((host->active_tc->flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0)
2427 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2222 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal);
2428 return (tul_msgin_accept(pCurHcb)); 2223 return initio_msgin_accept(host);
2429 } 2224 }
2430 } 2225 }
2431 } 2226 }
2432 TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN)); 2227 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal);
2433 2228
2434 if (tul_msgin_accept(pCurHcb) != MSG_OUT) 2229 if (initio_msgin_accept(host) != MSG_OUT)
2435 return (pCurHcb->HCS_Phase); 2230 return host->phase;
2436 /* WDTR msg out */ 2231 /* WDTR msg out */
2437 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND); 2232 outb(MSG_EXTEND, host->addr + TUL_SFifo);
2438 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2); 2233 outb(2, host->addr + TUL_SFifo);
2439 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); 2234 outb(3, host->addr + TUL_SFifo);
2440 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]); 2235 outb(host->msg[2], host->addr + TUL_SFifo);
2441 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2236 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2442 return (wait_tulip(pCurHcb)); 2237 return wait_tulip(host);
2443} 2238}
2444 2239
2445/***************************************************************************/ 2240static int initio_msgin_sync(struct initio_host * host)
2446int tul_msgin_sync(HCS * pCurHcb)
2447{ 2241{
2448 char default_period; 2242 char default_period;
2449 2243
2450 default_period = tul_rate_tbl[pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SCSI_RATE]; 2244 default_period = initio_rate_tbl[host->active_tc->flags & TCF_SCSI_RATE];
2451 if (pCurHcb->HCS_Msg[3] > MAX_OFFSET) { 2245 if (host->msg[3] > MAX_OFFSET) {
2452 pCurHcb->HCS_Msg[3] = MAX_OFFSET; 2246 host->msg[3] = MAX_OFFSET;
2453 if (pCurHcb->HCS_Msg[2] < default_period) { 2247 if (host->msg[2] < default_period) {
2454 pCurHcb->HCS_Msg[2] = default_period; 2248 host->msg[2] = default_period;
2455 return 1; 2249 return 1;
2456 } 2250 }
2457 if (pCurHcb->HCS_Msg[2] >= 59) { /* Change to async */ 2251 if (host->msg[2] >= 59) /* Change to async */
2458 pCurHcb->HCS_Msg[3] = 0; 2252 host->msg[3] = 0;
2459 }
2460 return 1; 2253 return 1;
2461 } 2254 }
2462 /* offset requests asynchronous transfers ? */ 2255 /* offset requests asynchronous transfers ? */
2463 if (pCurHcb->HCS_Msg[3] == 0) { 2256 if (host->msg[3] == 0) {
2464 return 0; 2257 return 0;
2465 } 2258 }
2466 if (pCurHcb->HCS_Msg[2] < default_period) { 2259 if (host->msg[2] < default_period) {
2467 pCurHcb->HCS_Msg[2] = default_period; 2260 host->msg[2] = default_period;
2468 return 1; 2261 return 1;
2469 } 2262 }
2470 if (pCurHcb->HCS_Msg[2] >= 59) { 2263 if (host->msg[2] >= 59) {
2471 pCurHcb->HCS_Msg[3] = 0; 2264 host->msg[3] = 0;
2472 return 1; 2265 return 1;
2473 } 2266 }
2474 return 0; 2267 return 0;
2475} 2268}
2476 2269
2477 2270static int wdtr_done(struct initio_host * host)
2478/***************************************************************************/
2479int wdtr_done(HCS * pCurHcb)
2480{ 2271{
2481 pCurHcb->HCS_ActTcs->TCS_Flags &= ~TCF_SYNC_DONE; 2272 host->active_tc->flags &= ~TCF_SYNC_DONE;
2482 pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_WDTR_DONE; 2273 host->active_tc->flags |= TCF_WDTR_DONE;
2483 2274
2484 pCurHcb->HCS_ActTcs->TCS_JS_Period = 0; 2275 host->active_tc->js_period = 0;
2485 if (pCurHcb->HCS_Msg[2]) { /* if 16 bit */ 2276 if (host->msg[2]) /* if 16 bit */
2486 pCurHcb->HCS_ActTcs->TCS_JS_Period |= TSC_WIDE_SCSI; 2277 host->active_tc->js_period |= TSC_WIDE_SCSI;
2487 } 2278 host->active_tc->sconfig0 &= ~TSC_ALT_PERIOD;
2488 pCurHcb->HCS_ActTcs->TCS_SConfig0 &= ~TSC_ALT_PERIOD; 2279 outb(host->active_tc->sconfig0, host->addr + TUL_SConfig);
2489 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0); 2280 outb(host->active_tc->js_period, host->addr + TUL_SPeriod);
2490 TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
2491 2281
2492 return 1; 2282 return 1;
2493} 2283}
2494 2284
2495/***************************************************************************/ 2285static int initio_sync_done(struct initio_host * host)
2496int tul_sync_done(HCS * pCurHcb)
2497{ 2286{
2498 int i; 2287 int i;
2499 2288
2500 pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_SYNC_DONE; 2289 host->active_tc->flags |= TCF_SYNC_DONE;
2501 2290
2502 if (pCurHcb->HCS_Msg[3]) { 2291 if (host->msg[3]) {
2503 pCurHcb->HCS_ActTcs->TCS_JS_Period |= pCurHcb->HCS_Msg[3]; 2292 host->active_tc->js_period |= host->msg[3];
2504 for (i = 0; i < 8; i++) { 2293 for (i = 0; i < 8; i++) {
2505 if (tul_rate_tbl[i] >= pCurHcb->HCS_Msg[2]) /* pick the big one */ 2294 if (initio_rate_tbl[i] >= host->msg[2]) /* pick the big one */
2506 break; 2295 break;
2507 } 2296 }
2508 pCurHcb->HCS_ActTcs->TCS_JS_Period |= (i << 4); 2297 host->active_tc->js_period |= (i << 4);
2509 pCurHcb->HCS_ActTcs->TCS_SConfig0 |= TSC_ALT_PERIOD; 2298 host->active_tc->sconfig0 |= TSC_ALT_PERIOD;
2510 } 2299 }
2511 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0); 2300 outb(host->active_tc->sconfig0, host->addr + TUL_SConfig);
2512 TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period); 2301 outb(host->active_tc->js_period, host->addr + TUL_SPeriod);
2513 2302
2514 return (-1); 2303 return -1;
2515} 2304}
2516 2305
2517 2306
2518int tul_post_scsi_rst(HCS * pCurHcb) 2307static int initio_post_scsi_rst(struct initio_host * host)
2519{ 2308{
2520 SCB *pCurScb; 2309 struct scsi_ctrl_blk *scb;
2521 TCS *pCurTcb; 2310 struct target_control *active_tc;
2522 int i; 2311 int i;
2523 2312
2524 pCurHcb->HCS_ActScb = NULL; 2313 host->active = NULL;
2525 pCurHcb->HCS_ActTcs = NULL; 2314 host->active_tc = NULL;
2526 pCurHcb->HCS_Flags = 0; 2315 host->flags = 0;
2527 2316
2528 while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) { 2317 while ((scb = initio_pop_busy_scb(host)) != NULL) {
2529 pCurScb->SCB_HaStat = HOST_BAD_PHAS; 2318 scb->hastat = HOST_BAD_PHAS;
2530 tul_append_done_scb(pCurHcb, pCurScb); 2319 initio_append_done_scb(host, scb);
2531 } 2320 }
2532 /* clear sync done flag */ 2321 /* clear sync done flag */
2533 pCurTcb = &pCurHcb->HCS_Tcs[0]; 2322 active_tc = &host->targets[0];
2534 for (i = 0; i < pCurHcb->HCS_MaxTar; pCurTcb++, i++) { 2323 for (i = 0; i < host->max_tar; active_tc++, i++) {
2535 pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE); 2324 active_tc->flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
2536 /* Initialize the sync. xfer register values to an asyn xfer */ 2325 /* Initialize the sync. xfer register values to an asyn xfer */
2537 pCurTcb->TCS_JS_Period = 0; 2326 active_tc->js_period = 0;
2538 pCurTcb->TCS_SConfig0 = pCurHcb->HCS_SConf1; 2327 active_tc->sconfig0 = host->sconf1;
2539 pCurHcb->HCS_ActTags[0] = 0; /* 07/22/98 */ 2328 host->act_tags[0] = 0; /* 07/22/98 */
2540 pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY; /* 07/22/98 */ 2329 host->targets[i].flags &= ~TCF_BUSY; /* 07/22/98 */
2541 } /* for */ 2330 } /* for */
2542 2331
2543 return (-1); 2332 return -1;
2544} 2333}
2545 2334
2546/***************************************************************************/ 2335static void initio_select_atn_stop(struct initio_host * host, struct scsi_ctrl_blk * scb)
2547void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb)
2548{ 2336{
2549 pCurScb->SCB_Status |= SCB_SELECT; 2337 scb->status |= SCB_SELECT;
2550 pCurScb->SCB_NxtStat = 0x1; 2338 scb->next_state = 0x1;
2551 pCurHcb->HCS_ActScb = pCurScb; 2339 host->active = scb;
2552 pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target]; 2340 host->active_tc = &host->targets[scb->target];
2553 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SELATNSTOP); 2341 outb(TSC_SELATNSTOP, host->addr + TUL_SCmd);
2554 return;
2555} 2342}
2556 2343
2557 2344
2558/***************************************************************************/ 2345static void initio_select_atn(struct initio_host * host, struct scsi_ctrl_blk * scb)
2559void tul_select_atn(HCS * pCurHcb, SCB * pCurScb)
2560{ 2346{
2561 int i; 2347 int i;
2562 2348
2563 pCurScb->SCB_Status |= SCB_SELECT; 2349 scb->status |= SCB_SELECT;
2564 pCurScb->SCB_NxtStat = 0x2; 2350 scb->next_state = 0x2;
2565 2351
2566 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident); 2352 outb(scb->ident, host->addr + TUL_SFifo);
2567 for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++) 2353 for (i = 0; i < (int) scb->cdblen; i++)
2568 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]); 2354 outb(scb->cdb[i], host->addr + TUL_SFifo);
2569 pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target]; 2355 host->active_tc = &host->targets[scb->target];
2570 pCurHcb->HCS_ActScb = pCurScb; 2356 host->active = scb;
2571 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN); 2357 outb(TSC_SEL_ATN, host->addr + TUL_SCmd);
2572 return;
2573} 2358}
2574 2359
2575/***************************************************************************/ 2360static void initio_select_atn3(struct initio_host * host, struct scsi_ctrl_blk * scb)
2576void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb)
2577{ 2361{
2578 int i; 2362 int i;
2579 2363
2580 pCurScb->SCB_Status |= SCB_SELECT; 2364 scb->status |= SCB_SELECT;
2581 pCurScb->SCB_NxtStat = 0x2; 2365 scb->next_state = 0x2;
2582 2366
2583 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident); 2367 outb(scb->ident, host->addr + TUL_SFifo);
2584 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg); 2368 outb(scb->tagmsg, host->addr + TUL_SFifo);
2585 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId); 2369 outb(scb->tagid, host->addr + TUL_SFifo);
2586 for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++) 2370 for (i = 0; i < scb->cdblen; i++)
2587 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]); 2371 outb(scb->cdb[i], host->addr + TUL_SFifo);
2588 pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target]; 2372 host->active_tc = &host->targets[scb->target];
2589 pCurHcb->HCS_ActScb = pCurScb; 2373 host->active = scb;
2590 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN3); 2374 outb(TSC_SEL_ATN3, host->addr + TUL_SCmd);
2591 return;
2592} 2375}
2593 2376
2594/***************************************************************************/ 2377/**
2595/* SCSI Bus Device Reset */ 2378 * initio_bus_device_reset - SCSI Bus Device Reset
2596int tul_bus_device_reset(HCS * pCurHcb) 2379 * @host: InitIO host to reset
2380 *
2381 * Perform a device reset and abort all pending SCBs for the
2382 * victim device
2383 */
2384int initio_bus_device_reset(struct initio_host * host)
2597{ 2385{
2598 SCB *pCurScb = pCurHcb->HCS_ActScb; 2386 struct scsi_ctrl_blk *scb = host->active;
2599 TCS *pCurTcb = pCurHcb->HCS_ActTcs; 2387 struct target_control *active_tc = host->active_tc;
2600 SCB *pTmpScb, *pPrevScb; 2388 struct scsi_ctrl_blk *tmp, *prev;
2601 BYTE tar; 2389 u8 tar;
2602 2390
2603 if (pCurHcb->HCS_Phase != MSG_OUT) { 2391 if (host->phase != MSG_OUT)
2604 return (int_tul_bad_seq(pCurHcb)); /* Unexpected phase */ 2392 return int_initio_bad_seq(host); /* Unexpected phase */
2605 } 2393
2606 tul_unlink_pend_scb(pCurHcb, pCurScb); 2394 initio_unlink_pend_scb(host, scb);
2607 tul_release_scb(pCurHcb, pCurScb); 2395 initio_release_scb(host, scb);
2608 2396
2609 2397
2610 tar = pCurScb->SCB_Target; /* target */ 2398 tar = scb->target; /* target */
2611 pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE | TCF_BUSY); 2399 active_tc->flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE | TCF_BUSY);
2612 /* clr sync. nego & WDTR flags 07/22/98 */ 2400 /* clr sync. nego & WDTR flags 07/22/98 */
2613 2401
2614 /* abort all SCB with same target */ 2402 /* abort all SCB with same target */
2615 pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */ 2403 prev = tmp = host->first_busy; /* Check Busy queue */
2616 while (pTmpScb != NULL) { 2404 while (tmp != NULL) {
2617 2405 if (tmp->target == tar) {
2618 if (pTmpScb->SCB_Target == tar) {
2619 /* unlink it */ 2406 /* unlink it */
2620 if (pTmpScb == pCurHcb->HCS_FirstBusy) { 2407 if (tmp == host->first_busy) {
2621 if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL) 2408 if ((host->first_busy = tmp->next) == NULL)
2622 pCurHcb->HCS_LastBusy = NULL; 2409 host->last_busy = NULL;
2623 } else { 2410 } else {
2624 pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb; 2411 prev->next = tmp->next;
2625 if (pTmpScb == pCurHcb->HCS_LastBusy) 2412 if (tmp == host->last_busy)
2626 pCurHcb->HCS_LastBusy = pPrevScb; 2413 host->last_busy = prev;
2627 } 2414 }
2628 pTmpScb->SCB_HaStat = HOST_ABORTED; 2415 tmp->hastat = HOST_ABORTED;
2629 tul_append_done_scb(pCurHcb, pTmpScb); 2416 initio_append_done_scb(host, tmp);
2630 } 2417 }
2631 /* Previous haven't change */ 2418 /* Previous haven't change */
2632 else { 2419 else {
2633 pPrevScb = pTmpScb; 2420 prev = tmp;
2634 } 2421 }
2635 pTmpScb = pTmpScb->SCB_NxtScb; 2422 tmp = tmp->next;
2636 } 2423 }
2637 2424 outb(MSG_DEVRST, host->addr + TUL_SFifo);
2638 TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_DEVRST); 2425 outb(TSC_XF_FIFO_OUT, host->addr + TUL_SCmd);
2639 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT); 2426 return initio_wait_disc(host);
2640
2641 return tul_wait_disc(pCurHcb);
2642 2427
2643} 2428}
2644 2429
2645/***************************************************************************/ 2430static int initio_msgin_accept(struct initio_host * host)
2646int tul_msgin_accept(HCS * pCurHcb)
2647{ 2431{
2648 TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT); 2432 outb(TSC_MSG_ACCEPT, host->addr + TUL_SCmd);
2649 return (wait_tulip(pCurHcb)); 2433 return wait_tulip(host);
2650} 2434}
2651 2435
2652/***************************************************************************/ 2436static int wait_tulip(struct initio_host * host)
2653int wait_tulip(HCS * pCurHcb)
2654{ 2437{
2655 2438
2656 while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0)) 2439 while (!((host->jsstatus0 = inb(host->addr + TUL_SStatus0))
2657 & TSS_INT_PENDING)); 2440 & TSS_INT_PENDING))
2441 cpu_relax();
2658 2442
2659 pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt); 2443 host->jsint = inb(host->addr + TUL_SInt);
2660 pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK; 2444 host->phase = host->jsstatus0 & TSS_PH_MASK;
2661 pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1); 2445 host->jsstatus1 = inb(host->addr + TUL_SStatus1);
2662 2446
2663 if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if SCSI bus reset detected */ 2447 if (host->jsint & TSS_RESEL_INT) /* if SCSI bus reset detected */
2664 return (int_tul_resel(pCurHcb)); 2448 return int_initio_resel(host);
2665 } 2449 if (host->jsint & TSS_SEL_TIMEOUT) /* if selected/reselected timeout interrupt */
2666 if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) { /* if selected/reselected timeout interrupt */ 2450 return int_initio_busfree(host);
2667 return (int_tul_busfree(pCurHcb)); 2451 if (host->jsint & TSS_SCSIRST_INT) /* if SCSI bus reset detected */
2668 } 2452 return int_initio_scsi_rst(host);
2669 if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */ 2453
2670 return (int_tul_scsi_rst(pCurHcb)); 2454 if (host->jsint & TSS_DISC_INT) { /* BUS disconnection */
2671 } 2455 if (host->flags & HCF_EXPECT_DONE_DISC) {
2672 if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */ 2456 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0); /* Flush SCSI FIFO */
2673 if (pCurHcb->HCS_Flags & HCF_EXPECT_DONE_DISC) { 2457 initio_unlink_busy_scb(host, host->active);
2674 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */ 2458 host->active->hastat = 0;
2675 tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb); 2459 initio_append_done_scb(host, host->active);
2676 pCurHcb->HCS_ActScb->SCB_HaStat = 0; 2460 host->active = NULL;
2677 tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb); 2461 host->active_tc = NULL;
2678 pCurHcb->HCS_ActScb = NULL; 2462 host->flags &= ~HCF_EXPECT_DONE_DISC;
2679 pCurHcb->HCS_ActTcs = NULL; 2463 outb(TSC_INITDEFAULT, host->addr + TUL_SConfig);
2680 pCurHcb->HCS_Flags &= ~HCF_EXPECT_DONE_DISC; 2464 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1); /* Enable HW reselect */
2681 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT); 2465 return -1;
2682 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
2683 return (-1);
2684 } 2466 }
2685 if (pCurHcb->HCS_Flags & HCF_EXPECT_DISC) { 2467 if (host->flags & HCF_EXPECT_DISC) {
2686 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */ 2468 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0); /* Flush SCSI FIFO */
2687 pCurHcb->HCS_ActScb = NULL; 2469 host->active = NULL;
2688 pCurHcb->HCS_ActTcs = NULL; 2470 host->active_tc = NULL;
2689 pCurHcb->HCS_Flags &= ~HCF_EXPECT_DISC; 2471 host->flags &= ~HCF_EXPECT_DISC;
2690 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT); 2472 outb(TSC_INITDEFAULT, host->addr + TUL_SConfig);
2691 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */ 2473 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1); /* Enable HW reselect */
2692 return (-1); 2474 return -1;
2693 } 2475 }
2694 return (int_tul_busfree(pCurHcb)); 2476 return int_initio_busfree(host);
2695 }
2696 if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) {
2697 return (pCurHcb->HCS_Phase);
2698 } 2477 }
2699 return (pCurHcb->HCS_Phase); 2478 /* The old code really does the below. Can probably be removed */
2479 if (host->jsint & (TSS_FUNC_COMP | TSS_BUS_SERV))
2480 return host->phase;
2481 return host->phase;
2700} 2482}
2701/***************************************************************************/
2702int tul_wait_disc(HCS * pCurHcb)
2703{
2704
2705 while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
2706 & TSS_INT_PENDING));
2707 2483
2484static int initio_wait_disc(struct initio_host * host)
2485{
2486 while (!((host->jsstatus0 = inb(host->addr + TUL_SStatus0)) & TSS_INT_PENDING))
2487 cpu_relax();
2708 2488
2709 pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt); 2489 host->jsint = inb(host->addr + TUL_SInt);
2710 2490
2711 if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */ 2491 if (host->jsint & TSS_SCSIRST_INT) /* if SCSI bus reset detected */
2712 return (int_tul_scsi_rst(pCurHcb)); 2492 return int_initio_scsi_rst(host);
2713 } 2493 if (host->jsint & TSS_DISC_INT) { /* BUS disconnection */
2714 if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */ 2494 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0); /* Flush SCSI FIFO */
2715 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */ 2495 outb(TSC_INITDEFAULT, host->addr + TUL_SConfig);
2716 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT); 2496 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1); /* Enable HW reselect */
2717 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */ 2497 host->active = NULL;
2718 pCurHcb->HCS_ActScb = NULL; 2498 return -1;
2719 return (-1);
2720 } 2499 }
2721 return (tul_bad_seq(pCurHcb)); 2500 return initio_bad_seq(host);
2722} 2501}
2723 2502
2724/***************************************************************************/ 2503static int initio_wait_done_disc(struct initio_host * host)
2725int tul_wait_done_disc(HCS * pCurHcb)
2726{ 2504{
2505 while (!((host->jsstatus0 = inb(host->addr + TUL_SStatus0))
2506 & TSS_INT_PENDING))
2507 cpu_relax();
2727 2508
2509 host->jsint = inb(host->addr + TUL_SInt);
2728 2510
2729 while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0)) 2511 if (host->jsint & TSS_SCSIRST_INT) /* if SCSI bus reset detected */
2730 & TSS_INT_PENDING)); 2512 return int_initio_scsi_rst(host);
2731 2513 if (host->jsint & TSS_DISC_INT) { /* BUS disconnection */
2732 pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt); 2514 outb(TSC_FLUSH_FIFO, host->addr + TUL_SCtrl0); /* Flush SCSI FIFO */
2733 2515 outb(TSC_INITDEFAULT, host->addr + TUL_SConfig);
2734 2516 outb(TSC_HW_RESELECT, host->addr + TUL_SCtrl1); /* Enable HW reselect */
2735 if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */ 2517 initio_unlink_busy_scb(host, host->active);
2736 return (int_tul_scsi_rst(pCurHcb));
2737 }
2738 if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
2739 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
2740 TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
2741 TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
2742 tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
2743 2518
2744 tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb); 2519 initio_append_done_scb(host, host->active);
2745 pCurHcb->HCS_ActScb = NULL; 2520 host->active = NULL;
2746 return (-1); 2521 return -1;
2747 } 2522 }
2748 return (tul_bad_seq(pCurHcb)); 2523 return initio_bad_seq(host);
2749} 2524}
2750 2525
2526/**
2527 * i91u_intr - IRQ handler
2528 * @irqno: IRQ number
2529 * @dev_id: IRQ identifier
2530 *
2531 * Take the relevant locks and then invoke the actual isr processing
2532 * code under the lock.
2533 */
2534
2751static irqreturn_t i91u_intr(int irqno, void *dev_id) 2535static irqreturn_t i91u_intr(int irqno, void *dev_id)
2752{ 2536{
2753 struct Scsi_Host *dev = dev_id; 2537 struct Scsi_Host *dev = dev_id;
2754 unsigned long flags; 2538 unsigned long flags;
2539 int r;
2755 2540
2756 spin_lock_irqsave(dev->host_lock, flags); 2541 spin_lock_irqsave(dev->host_lock, flags);
2757 tul_isr((HCS *)dev->base); 2542 r = initio_isr((struct initio_host *)dev->hostdata);
2758 spin_unlock_irqrestore(dev->host_lock, flags); 2543 spin_unlock_irqrestore(dev->host_lock, flags);
2759 return IRQ_HANDLED; 2544 if (r)
2760} 2545 return IRQ_HANDLED;
2761 2546 else
2762static int tul_NewReturnNumberOfAdapters(void) 2547 return IRQ_NONE;
2763{
2764 struct pci_dev *pDev = NULL; /* Start from none */
2765 int iAdapters = 0;
2766 long dRegValue;
2767 WORD wBIOS;
2768 int i = 0;
2769
2770 init_i91uAdapter_table();
2771
2772 for (i = 0; i < ARRAY_SIZE(i91u_pci_devices); i++)
2773 {
2774 while ((pDev = pci_find_device(i91u_pci_devices[i].vendor, i91u_pci_devices[i].device, pDev)) != NULL) {
2775 if (pci_enable_device(pDev))
2776 continue;
2777 pci_read_config_dword(pDev, 0x44, (u32 *) & dRegValue);
2778 wBIOS = (UWORD) (dRegValue & 0xFF);
2779 if (((dRegValue & 0xFF00) >> 8) == 0xFF)
2780 dRegValue = 0;
2781 wBIOS = (wBIOS << 8) + ((UWORD) ((dRegValue & 0xFF00) >> 8));
2782 if (pci_set_dma_mask(pDev, DMA_32BIT_MASK)) {
2783 printk(KERN_WARNING
2784 "i91u: Could not set 32 bit DMA mask\n");
2785 continue;
2786 }
2787
2788 if (Addi91u_into_Adapter_table(wBIOS,
2789 (pDev->resource[0].start),
2790 pDev->irq,
2791 pDev->bus->number,
2792 (pDev->devfn >> 3)
2793 ) == 0)
2794 iAdapters++;
2795 }
2796 }
2797
2798 return (iAdapters);
2799} 2548}
2800 2549
2801static int i91u_detect(struct scsi_host_template * tpnt)
2802{
2803 HCS *pHCB;
2804 struct Scsi_Host *hreg;
2805 unsigned long i; /* 01/14/98 */
2806 int ok = 0, iAdapters;
2807 ULONG dBiosAdr;
2808 BYTE *pbBiosAdr;
2809
2810 /* Get total number of adapters in the motherboard */
2811 iAdapters = tul_NewReturnNumberOfAdapters();
2812 if (iAdapters == 0) /* If no tulip founded, return */
2813 return (0);
2814
2815 tul_num_ch = (iAdapters > tul_num_ch) ? tul_num_ch : iAdapters;
2816 /* Update actually channel number */
2817 if (tul_tag_enable) { /* 1.01i */
2818 tul_num_scb = MAX_TARGETS * i91u_MAXQUEUE;
2819 } else {
2820 tul_num_scb = MAX_TARGETS + 3; /* 1-tape, 1-CD_ROM, 1- extra */
2821 } /* Update actually SCBs per adapter */
2822
2823 /* Get total memory needed for HCS */
2824 i = tul_num_ch * sizeof(HCS);
2825 memset((unsigned char *) &tul_hcs[0], 0, i); /* Initialize tul_hcs 0 */
2826 /* Get total memory needed for SCB */
2827
2828 for (; tul_num_scb >= MAX_TARGETS + 3; tul_num_scb--) {
2829 i = tul_num_ch * tul_num_scb * sizeof(SCB);
2830 if ((tul_scb = kmalloc(i, GFP_ATOMIC | GFP_DMA)) != NULL)
2831 break;
2832 }
2833 if (tul_scb == NULL) {
2834 printk("i91u: SCB memory allocation error\n");
2835 return (0);
2836 }
2837 memset((unsigned char *) tul_scb, 0, i);
2838 2550
2839 for (i = 0, pHCB = &tul_hcs[0]; /* Get pointer for control block */ 2551/**
2840 i < tul_num_ch; 2552 * initio_build_scb - Build the mappings and SCB
2841 i++, pHCB++) { 2553 * @host: InitIO host taking the command
2842 get_tulipPCIConfig(pHCB, i); 2554 * @cblk: Firmware command block
2843 2555 * @cmnd: SCSI midlayer command block
2844 dBiosAdr = pHCB->HCS_BIOS; 2556 *
2845 dBiosAdr = (dBiosAdr << 4); 2557 * Translate the abstract SCSI command into a firmware command block
2846 2558 * suitable for feeding to the InitIO host controller. This also requires
2847 pbBiosAdr = phys_to_virt(dBiosAdr); 2559 * we build the scatter gather lists and ensure they are mapped properly.
2848 2560 */
2849 init_tulip(pHCB, tul_scb + (i * tul_num_scb), tul_num_scb, pbBiosAdr, 10);
2850 request_region(pHCB->HCS_Base, 256, "i91u"); /* Register */
2851
2852 pHCB->HCS_Index = i; /* 7/29/98 */
2853 hreg = scsi_register(tpnt, sizeof(HCS));
2854 if(hreg == NULL) {
2855 release_region(pHCB->HCS_Base, 256);
2856 return 0;
2857 }
2858 hreg->io_port = pHCB->HCS_Base;
2859 hreg->n_io_port = 0xff;
2860 hreg->can_queue = tul_num_scb; /* 03/05/98 */
2861 hreg->unique_id = pHCB->HCS_Base;
2862 hreg->max_id = pHCB->HCS_MaxTar;
2863 hreg->max_lun = 32; /* 10/21/97 */
2864 hreg->irq = pHCB->HCS_Intr;
2865 hreg->this_id = pHCB->HCS_SCSI_ID; /* Assign HCS index */
2866 hreg->base = (unsigned long)pHCB;
2867 hreg->sg_tablesize = TOTAL_SG_ENTRY; /* Maximun support is 32 */
2868
2869 /* Initial tulip chip */
2870 ok = request_irq(pHCB->HCS_Intr, i91u_intr, IRQF_DISABLED | IRQF_SHARED, "i91u", hreg);
2871 if (ok < 0) {
2872 printk(KERN_WARNING "i91u: unable to request IRQ %d\n\n", pHCB->HCS_Intr);
2873 return 0;
2874 }
2875 }
2876
2877 tpnt->this_id = -1;
2878 tpnt->can_queue = 1;
2879
2880 return 1;
2881}
2882 2561
2883static void i91uBuildSCB(HCS * pHCB, SCB * pSCB, struct scsi_cmnd * SCpnt) 2562static void initio_build_scb(struct initio_host * host, struct scsi_ctrl_blk * cblk, struct scsi_cmnd * cmnd)
2884{ /* Create corresponding SCB */ 2563{ /* Create corresponding SCB */
2885 struct scatterlist *pSrbSG; 2564 struct scatterlist *sglist;
2886 SG *pSG; /* Pointer to SG list */ 2565 struct sg_entry *sg; /* Pointer to SG list */
2887 int i; 2566 int i;
2888 long TotalLen; 2567 long total_len;
2889 dma_addr_t dma_addr; 2568 dma_addr_t dma_addr;
2890 2569
2891 pSCB->SCB_Post = i91uSCBPost; /* i91u's callback routine */ 2570 /* Fill in the command headers */
2892 pSCB->SCB_Srb = SCpnt; 2571 cblk->post = i91uSCBPost; /* i91u's callback routine */
2893 pSCB->SCB_Opcode = ExecSCSI; 2572 cblk->srb = cmnd;
2894 pSCB->SCB_Flags = SCF_POST; /* After SCSI done, call post routine */ 2573 cblk->opcode = ExecSCSI;
2895 pSCB->SCB_Target = SCpnt->device->id; 2574 cblk->flags = SCF_POST; /* After SCSI done, call post routine */
2896 pSCB->SCB_Lun = SCpnt->device->lun; 2575 cblk->target = cmnd->device->id;
2897 pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW; 2576 cblk->lun = cmnd->device->lun;
2898 2577 cblk->ident = cmnd->device->lun | DISC_ALLOW;
2899 pSCB->SCB_Flags |= SCF_SENSE; /* Turn on auto request sense */
2900 dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->sense_buffer,
2901 SENSE_SIZE, DMA_FROM_DEVICE);
2902 pSCB->SCB_SensePtr = cpu_to_le32((u32)dma_addr);
2903 pSCB->SCB_SenseLen = cpu_to_le32(SENSE_SIZE);
2904 SCpnt->SCp.ptr = (char *)(unsigned long)dma_addr;
2905 2578
2906 pSCB->SCB_CDBLen = SCpnt->cmd_len; 2579 cblk->flags |= SCF_SENSE; /* Turn on auto request sense */
2907 pSCB->SCB_HaStat = 0;
2908 pSCB->SCB_TaStat = 0;
2909 memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, SCpnt->cmd_len);
2910 2580
2911 if (SCpnt->device->tagged_supported) { /* Tag Support */ 2581 /* Map the sense buffer into bus memory */
2912 pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG; /* Do simple tag only */ 2582 dma_addr = dma_map_single(&host->pci_dev->dev, cmnd->sense_buffer,
2583 SENSE_SIZE, DMA_FROM_DEVICE);
2584 cblk->senseptr = cpu_to_le32((u32)dma_addr);
2585 cblk->senselen = cpu_to_le32(SENSE_SIZE);
2586 cmnd->SCp.ptr = (char *)(unsigned long)dma_addr;
2587 cblk->cdblen = cmnd->cmd_len;
2588
2589 /* Clear the returned status */
2590 cblk->hastat = 0;
2591 cblk->tastat = 0;
2592 /* Command the command */
2593 memcpy(&cblk->cdb[0], &cmnd->cmnd, cmnd->cmd_len);
2594
2595 /* Set up tags */
2596 if (cmnd->device->tagged_supported) { /* Tag Support */
2597 cblk->tagmsg = SIMPLE_QUEUE_TAG; /* Do simple tag only */
2913 } else { 2598 } else {
2914 pSCB->SCB_TagMsg = 0; /* No tag support */ 2599 cblk->tagmsg = 0; /* No tag support */
2915 } 2600 }
2601
2916 /* todo handle map_sg error */ 2602 /* todo handle map_sg error */
2917 if (SCpnt->use_sg) { 2603 if (cmnd->use_sg) {
2918 dma_addr = dma_map_single(&pHCB->pci_dev->dev, &pSCB->SCB_SGList[0], 2604 dma_addr = dma_map_single(&host->pci_dev->dev, &cblk->sglist[0],
2919 sizeof(struct SG_Struc) * TOTAL_SG_ENTRY, 2605 sizeof(struct sg_entry) * TOTAL_SG_ENTRY,
2920 DMA_BIDIRECTIONAL); 2606 DMA_BIDIRECTIONAL);
2921 pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr); 2607 cblk->bufptr = cpu_to_le32((u32)dma_addr);
2922 SCpnt->SCp.dma_handle = dma_addr; 2608 cmnd->SCp.dma_handle = dma_addr;
2923 2609
2924 pSrbSG = (struct scatterlist *) SCpnt->request_buffer; 2610 sglist = (struct scatterlist *) cmnd->request_buffer;
2925 pSCB->SCB_SGLen = dma_map_sg(&pHCB->pci_dev->dev, pSrbSG, 2611 cblk->sglen = dma_map_sg(&host->pci_dev->dev, sglist,
2926 SCpnt->use_sg, SCpnt->sc_data_direction); 2612 cmnd->use_sg, cmnd->sc_data_direction);
2927 2613
2928 pSCB->SCB_Flags |= SCF_SG; /* Turn on SG list flag */ 2614 cblk->flags |= SCF_SG; /* Turn on SG list flag */
2929 for (i = 0, TotalLen = 0, pSG = &pSCB->SCB_SGList[0]; /* 1.01g */ 2615 for (i = 0, total_len = 0, sg = &cblk->sglist[0]; /* 1.01g */
2930 i < pSCB->SCB_SGLen; i++, pSG++, pSrbSG++) { 2616 i < cblk->sglen; i++, sg++, sglist++) {
2931 pSG->SG_Ptr = cpu_to_le32((u32)sg_dma_address(pSrbSG)); 2617 sg->data = cpu_to_le32((u32)sg_dma_address(sglist));
2932 TotalLen += pSG->SG_Len = cpu_to_le32((u32)sg_dma_len(pSrbSG)); 2618 total_len += sg->len = cpu_to_le32((u32)sg_dma_len(sglist));
2933 } 2619 }
2934 2620
2935 pSCB->SCB_BufLen = (SCpnt->request_bufflen > TotalLen) ? 2621 cblk->buflen = (cmnd->request_bufflen > total_len) ?
2936 TotalLen : SCpnt->request_bufflen; 2622 total_len : cmnd->request_bufflen;
2937 } else if (SCpnt->request_bufflen) { /* Non SG */ 2623 } else if (cmnd->request_bufflen) { /* Non SG */
2938 dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->request_buffer, 2624 dma_addr = dma_map_single(&host->pci_dev->dev, cmnd->request_buffer,
2939 SCpnt->request_bufflen, 2625 cmnd->request_bufflen,
2940 SCpnt->sc_data_direction); 2626 cmnd->sc_data_direction);
2941 SCpnt->SCp.dma_handle = dma_addr; 2627 cmnd->SCp.dma_handle = dma_addr;
2942 pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr); 2628 cblk->bufptr = cpu_to_le32((u32)dma_addr);
2943 pSCB->SCB_BufLen = cpu_to_le32((u32)SCpnt->request_bufflen); 2629 cblk->buflen = cpu_to_le32((u32)cmnd->request_bufflen);
2944 pSCB->SCB_SGLen = 0; 2630 cblk->sglen = 0;
2945 } else { 2631 } else { /* No data transfer required */
2946 pSCB->SCB_BufLen = 0; 2632 cblk->buflen = 0;
2947 pSCB->SCB_SGLen = 0; 2633 cblk->sglen = 0;
2948 } 2634 }
2949} 2635}
2636
2637/**
2638 * i91u_queuecommand - Queue a new command if possible
2639 * @cmd: SCSI command block from the mid layer
2640 * @done: Completion handler
2641 *
2642 * Attempts to queue a new command with the host adapter. Will return
2643 * zero if successful or indicate a host busy condition if not (which
2644 * will cause the mid layer to call us again later with the command)
2645 */
2950 2646
2951static int i91u_queuecommand(struct scsi_cmnd *cmd, 2647static int i91u_queuecommand(struct scsi_cmnd *cmd,
2952 void (*done)(struct scsi_cmnd *)) 2648 void (*done)(struct scsi_cmnd *))
2953{ 2649{
2954 HCS *pHCB = (HCS *) cmd->device->host->base; 2650 struct initio_host *host = (struct initio_host *) cmd->device->host->hostdata;
2955 register SCB *pSCB; 2651 struct scsi_ctrl_blk *cmnd;
2956 2652
2957 cmd->scsi_done = done; 2653 cmd->scsi_done = done;
2958 2654
2959 pSCB = tul_alloc_scb(pHCB); 2655 cmnd = initio_alloc_scb(host);
2960 if (!pSCB) 2656 if (!cmnd)
2961 return SCSI_MLQUEUE_HOST_BUSY; 2657 return SCSI_MLQUEUE_HOST_BUSY;
2962 2658
2963 i91uBuildSCB(pHCB, pSCB, cmd); 2659 initio_build_scb(host, cmnd, cmd);
2964 tul_exec_scb(pHCB, pSCB); 2660 initio_exec_scb(host, cmnd);
2965 return 0; 2661 return 0;
2966} 2662}
2967 2663
2968#if 0 /* no new EH yet */ 2664/**
2969/* 2665 * i91u_bus_reset - reset the SCSI bus
2970 * Abort a queued command 2666 * @cmnd: Command block we want to trigger the reset for
2971 * (commands that are on the bus can't be aborted easily) 2667 *
2972 */ 2668 * Initiate a SCSI bus reset sequence
2973static int i91u_abort(struct scsi_cmnd * SCpnt)
2974{
2975 HCS *pHCB;
2976
2977 pHCB = (HCS *) SCpnt->device->host->base;
2978 return tul_abort_srb(pHCB, SCpnt);
2979}
2980
2981/*
2982 * Reset registers, reset a hanging bus and
2983 * kill active and disconnected commands for target w/o soft reset
2984 */ 2669 */
2985static int i91u_reset(struct scsi_cmnd * SCpnt, unsigned int reset_flags)
2986{ /* I need Host Control Block Information */
2987 HCS *pHCB;
2988 2670
2989 pHCB = (HCS *) SCpnt->device->host->base; 2671static int i91u_bus_reset(struct scsi_cmnd * cmnd)
2990
2991 if (reset_flags & (SCSI_RESET_SUGGEST_BUS_RESET | SCSI_RESET_SUGGEST_HOST_RESET))
2992 return tul_reset_scsi_bus(pHCB);
2993 else
2994 return tul_device_reset(pHCB, SCpnt, SCpnt->device->id, reset_flags);
2995}
2996#endif
2997
2998static int i91u_bus_reset(struct scsi_cmnd * SCpnt)
2999{ 2672{
3000 HCS *pHCB; 2673 struct initio_host *host;
3001 2674
3002 pHCB = (HCS *) SCpnt->device->host->base; 2675 host = (struct initio_host *) cmnd->device->host->hostdata;
3003 2676
3004 spin_lock_irq(SCpnt->device->host->host_lock); 2677 spin_lock_irq(cmnd->device->host->host_lock);
3005 tul_reset_scsi(pHCB, 0); 2678 initio_reset_scsi(host, 0);
3006 spin_unlock_irq(SCpnt->device->host->host_lock); 2679 spin_unlock_irq(cmnd->device->host->host_lock);
3007 2680
3008 return SUCCESS; 2681 return SUCCESS;
3009} 2682}
3010 2683
3011/* 2684/**
3012 * Return the "logical geometry" 2685 * i91u_biospararm - return the "logical geometry
2686 * @sdev: SCSI device
2687 * @dev; Matching block device
2688 * @capacity: Sector size of drive
2689 * @info_array: Return space for BIOS geometry
2690 *
2691 * Map the device geometry in a manner compatible with the host
2692 * controller BIOS behaviour.
2693 *
2694 * FIXME: limited to 2^32 sector devices.
3013 */ 2695 */
2696
3014static int i91u_biosparam(struct scsi_device *sdev, struct block_device *dev, 2697static int i91u_biosparam(struct scsi_device *sdev, struct block_device *dev,
3015 sector_t capacity, int *info_array) 2698 sector_t capacity, int *info_array)
3016{ 2699{
3017 HCS *pHcb; /* Point to Host adapter control block */ 2700 struct initio_host *host; /* Point to Host adapter control block */
3018 TCS *pTcb; 2701 struct target_control *tc;
3019 2702
3020 pHcb = (HCS *) sdev->host->base; 2703 host = (struct initio_host *) sdev->host->hostdata;
3021 pTcb = &pHcb->HCS_Tcs[sdev->id]; 2704 tc = &host->targets[sdev->id];
3022 2705
3023 if (pTcb->TCS_DrvHead) { 2706 if (tc->heads) {
3024 info_array[0] = pTcb->TCS_DrvHead; 2707 info_array[0] = tc->heads;
3025 info_array[1] = pTcb->TCS_DrvSector; 2708 info_array[1] = tc->sectors;
3026 info_array[2] = (unsigned long)capacity / pTcb->TCS_DrvHead / pTcb->TCS_DrvSector; 2709 info_array[2] = (unsigned long)capacity / tc->heads / tc->sectors;
3027 } else { 2710 } else {
3028 if (pTcb->TCS_DrvFlags & TCF_DRV_255_63) { 2711 if (tc->drv_flags & TCF_DRV_255_63) {
3029 info_array[0] = 255; 2712 info_array[0] = 255;
3030 info_array[1] = 63; 2713 info_array[1] = 63;
3031 info_array[2] = (unsigned long)capacity / 255 / 63; 2714 info_array[2] = (unsigned long)capacity / 255 / 63;
@@ -3047,7 +2730,16 @@ static int i91u_biosparam(struct scsi_device *sdev, struct block_device *dev,
3047 return 0; 2730 return 0;
3048} 2731}
3049 2732
3050static void i91u_unmap_cmnd(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd) 2733/**
2734 * i91u_unmap_scb - Unmap a command
2735 * @pci_dev: PCI device the command is for
2736 * @cmnd: The command itself
2737 *
2738 * Unmap any PCI mapping/IOMMU resources allocated when the command
2739 * was mapped originally as part of initio_build_scb
2740 */
2741
2742static void i91u_unmap_scb(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd)
3051{ 2743{
3052 /* auto sense buffer */ 2744 /* auto sense buffer */
3053 if (cmnd->SCp.ptr) { 2745 if (cmnd->SCp.ptr) {
@@ -3060,7 +2752,7 @@ static void i91u_unmap_cmnd(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd)
3060 /* request buffer */ 2752 /* request buffer */
3061 if (cmnd->use_sg) { 2753 if (cmnd->use_sg) {
3062 dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle, 2754 dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
3063 sizeof(struct SG_Struc) * TOTAL_SG_ENTRY, 2755 sizeof(struct sg_entry) * TOTAL_SG_ENTRY,
3064 DMA_BIDIRECTIONAL); 2756 DMA_BIDIRECTIONAL);
3065 2757
3066 dma_unmap_sg(&pci_dev->dev, cmnd->request_buffer, 2758 dma_unmap_sg(&pci_dev->dev, cmnd->request_buffer,
@@ -3073,50 +2765,54 @@ static void i91u_unmap_cmnd(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd)
3073 } 2765 }
3074} 2766}
3075 2767
3076/***************************************************************************** 2768/**
3077 Function name : i91uSCBPost 2769 * i91uSCBPost - SCSI callback
3078 Description : This is callback routine be called when tulip finish one 2770 * @host: Pointer to host adapter control block.
3079 SCSI command. 2771 * @cmnd: Pointer to SCSI control block.
3080 Input : pHCB - Pointer to host adapter control block. 2772 *
3081 pSCB - Pointer to SCSI control block. 2773 * This is callback routine be called when tulip finish one
3082 Output : None. 2774 * SCSI command.
3083 Return : None. 2775 */
3084*****************************************************************************/
3085static void i91uSCBPost(BYTE * pHcb, BYTE * pScb)
3086{
3087 struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */
3088 HCS *pHCB;
3089 SCB *pSCB;
3090 2776
3091 pHCB = (HCS *) pHcb; 2777static void i91uSCBPost(u8 * host_mem, u8 * cblk_mem)
3092 pSCB = (SCB *) pScb; 2778{
3093 if ((pSRB = pSCB->SCB_Srb) == 0) { 2779 struct scsi_cmnd *cmnd; /* Pointer to SCSI request block */
3094 printk("i91uSCBPost: SRB pointer is empty\n"); 2780 struct initio_host *host;
2781 struct scsi_ctrl_blk *cblk;
3095 2782
3096 tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */ 2783 host = (struct initio_host *) host_mem;
2784 cblk = (struct scsi_ctrl_blk *) cblk_mem;
2785 if ((cmnd = cblk->srb) == NULL) {
2786 printk(KERN_ERR "i91uSCBPost: SRB pointer is empty\n");
2787 WARN_ON(1);
2788 initio_release_scb(host, cblk); /* Release SCB for current channel */
3097 return; 2789 return;
3098 } 2790 }
3099 switch (pSCB->SCB_HaStat) { 2791
2792 /*
2793 * Remap the firmware error status into a mid layer one
2794 */
2795 switch (cblk->hastat) {
3100 case 0x0: 2796 case 0x0:
3101 case 0xa: /* Linked command complete without error and linked normally */ 2797 case 0xa: /* Linked command complete without error and linked normally */
3102 case 0xb: /* Linked command complete without error interrupt generated */ 2798 case 0xb: /* Linked command complete without error interrupt generated */
3103 pSCB->SCB_HaStat = 0; 2799 cblk->hastat = 0;
3104 break; 2800 break;
3105 2801
3106 case 0x11: /* Selection time out-The initiator selection or target 2802 case 0x11: /* Selection time out-The initiator selection or target
3107 reselection was not complete within the SCSI Time out period */ 2803 reselection was not complete within the SCSI Time out period */
3108 pSCB->SCB_HaStat = DID_TIME_OUT; 2804 cblk->hastat = DID_TIME_OUT;
3109 break; 2805 break;
3110 2806
3111 case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus 2807 case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus
3112 phase sequence was requested by the target. The host adapter 2808 phase sequence was requested by the target. The host adapter
3113 will generate a SCSI Reset Condition, notifying the host with 2809 will generate a SCSI Reset Condition, notifying the host with
3114 a SCRD interrupt */ 2810 a SCRD interrupt */
3115 pSCB->SCB_HaStat = DID_RESET; 2811 cblk->hastat = DID_RESET;
3116 break; 2812 break;
3117 2813
3118 case 0x1a: /* SCB Aborted. 07/21/98 */ 2814 case 0x1a: /* SCB Aborted. 07/21/98 */
3119 pSCB->SCB_HaStat = DID_ABORT; 2815 cblk->hastat = DID_ABORT;
3120 break; 2816 break;
3121 2817
3122 case 0x12: /* Data overrun/underrun-The target attempted to transfer more data 2818 case 0x12: /* Data overrun/underrun-The target attempted to transfer more data
@@ -3126,49 +2822,196 @@ static void i91uSCBPost(BYTE * pHcb, BYTE * pScb)
3126 case 0x16: /* Invalid SCB Operation Code. */ 2822 case 0x16: /* Invalid SCB Operation Code. */
3127 2823
3128 default: 2824 default:
3129 printk("ini9100u: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat); 2825 printk("ini9100u: %x %x\n", cblk->hastat, cblk->tastat);
3130 pSCB->SCB_HaStat = DID_ERROR; /* Couldn't find any better */ 2826 cblk->hastat = DID_ERROR; /* Couldn't find any better */
3131 break; 2827 break;
3132 } 2828 }
3133 2829
3134 pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16); 2830 cmnd->result = cblk->tastat | (cblk->hastat << 16);
2831 WARN_ON(cmnd == NULL);
2832 i91u_unmap_scb(host->pci_dev, cmnd);
2833 cmnd->scsi_done(cmnd); /* Notify system DONE */
2834 initio_release_scb(host, cblk); /* Release SCB for current channel */
2835}
2836
2837static struct scsi_host_template initio_template = {
2838 .proc_name = "INI9100U",
2839 .name = "Initio INI-9X00U/UW SCSI device driver",
2840 .queuecommand = i91u_queuecommand,
2841 .eh_bus_reset_handler = i91u_bus_reset,
2842 .bios_param = i91u_biosparam,
2843 .can_queue = MAX_TARGETS * i91u_MAXQUEUE,
2844 .this_id = 1,
2845 .sg_tablesize = SG_ALL,
2846 .cmd_per_lun = 1,
2847 .use_clustering = ENABLE_CLUSTERING,
2848};
2849
2850static int initio_probe_one(struct pci_dev *pdev,
2851 const struct pci_device_id *id)
2852{
2853 struct Scsi_Host *shost;
2854 struct initio_host *host;
2855 u32 reg;
2856 u16 bios_seg;
2857 struct scsi_ctrl_blk *scb, *tmp, *prev = NULL /* silence gcc */;
2858 int num_scb, i, error;
2859
2860 error = pci_enable_device(pdev);
2861 if (error)
2862 return error;
2863
2864 pci_read_config_dword(pdev, 0x44, (u32 *) & reg);
2865 bios_seg = (u16) (reg & 0xFF);
2866 if (((reg & 0xFF00) >> 8) == 0xFF)
2867 reg = 0;
2868 bios_seg = (bios_seg << 8) + ((u16) ((reg & 0xFF00) >> 8));
2869
2870 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
2871 printk(KERN_WARNING "i91u: Could not set 32 bit DMA mask\n");
2872 error = -ENODEV;
2873 goto out_disable_device;
2874 }
2875 shost = scsi_host_alloc(&initio_template, sizeof(struct initio_host));
2876 if (!shost) {
2877 printk(KERN_WARNING "initio: Could not allocate host structure.\n");
2878 error = -ENOMEM;
2879 goto out_disable_device;
2880 }
2881 host = (struct initio_host *)shost->hostdata;
2882 memset(host, 0, sizeof(struct initio_host));
3135 2883
3136 if (pSRB == NULL) { 2884 if (!request_region(host->addr, 256, "i91u")) {
3137 printk("pSRB is NULL\n"); 2885 printk(KERN_WARNING "initio: I/O port range 0x%x is busy.\n", host->addr);
2886 error = -ENODEV;
2887 goto out_host_put;
3138 } 2888 }
3139 2889
3140 i91u_unmap_cmnd(pHCB->pci_dev, pSRB); 2890 if (initio_tag_enable) /* 1.01i */
3141 pSRB->scsi_done(pSRB); /* Notify system DONE */ 2891 num_scb = MAX_TARGETS * i91u_MAXQUEUE;
2892 else
2893 num_scb = MAX_TARGETS + 3; /* 1-tape, 1-CD_ROM, 1- extra */
3142 2894
3143 tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */ 2895 for (; num_scb >= MAX_TARGETS + 3; num_scb--) {
3144} 2896 i = num_scb * sizeof(struct scsi_ctrl_blk);
2897 if ((scb = kzalloc(i, GFP_DMA)) != NULL)
2898 break;
2899 }
2900
2901 if (!scb) {
2902 printk(KERN_WARNING "initio: Cannot allocate SCB array.\n");
2903 error = -ENOMEM;
2904 goto out_release_region;
2905 }
3145 2906
3146/* 2907 host->num_scbs = num_scb;
3147 * Release ressources 2908 host->scb = scb;
2909 host->next_pending = scb;
2910 host->next_avail = scb;
2911 for (i = 0, tmp = scb; i < num_scb; i++, tmp++) {
2912 tmp->tagid = i;
2913 if (i != 0)
2914 prev->next = tmp;
2915 prev = tmp;
2916 }
2917 prev->next = NULL;
2918 host->scb_end = tmp;
2919 host->first_avail = scb;
2920 host->last_avail = prev;
2921
2922 initio_init(host, phys_to_virt(bios_seg << 4));
2923
2924 host->jsstatus0 = 0;
2925
2926 shost->io_port = host->addr;
2927 shost->n_io_port = 0xff;
2928 shost->can_queue = num_scb; /* 03/05/98 */
2929 shost->unique_id = host->addr;
2930 shost->max_id = host->max_tar;
2931 shost->max_lun = 32; /* 10/21/97 */
2932 shost->irq = pdev->irq;
2933 shost->this_id = host->scsi_id; /* Assign HCS index */
2934 shost->base = host->addr;
2935 shost->sg_tablesize = TOTAL_SG_ENTRY;
2936
2937 error = request_irq(pdev->irq, i91u_intr, IRQF_DISABLED|IRQF_SHARED, "i91u", shost);
2938 if (error < 0) {
2939 printk(KERN_WARNING "initio: Unable to request IRQ %d\n", pdev->irq);
2940 goto out_free_scbs;
2941 }
2942
2943 pci_set_drvdata(pdev, shost);
2944 host->pci_dev = pdev;
2945
2946 error = scsi_add_host(shost, &pdev->dev);
2947 if (error)
2948 goto out_free_irq;
2949 scsi_scan_host(shost);
2950 return 0;
2951out_free_irq:
2952 free_irq(pdev->irq, shost);
2953out_free_scbs:
2954 kfree(host->scb);
2955out_release_region:
2956 release_region(host->addr, 256);
2957out_host_put:
2958 scsi_host_put(shost);
2959out_disable_device:
2960 pci_disable_device(pdev);
2961 return error;
2962}
2963
2964/**
2965 * initio_remove_one - control shutdown
2966 * @pdev: PCI device being released
2967 *
2968 * Release the resources assigned to this adapter after it has
2969 * finished being used.
3148 */ 2970 */
3149static int i91u_release(struct Scsi_Host *hreg) 2971
2972static void initio_remove_one(struct pci_dev *pdev)
3150{ 2973{
3151 free_irq(hreg->irq, hreg); 2974 struct Scsi_Host *host = pci_get_drvdata(pdev);
3152 release_region(hreg->io_port, 256); 2975 struct initio_host *s = (struct initio_host *)host->hostdata;
3153 return 0; 2976 scsi_remove_host(host);
2977 free_irq(pdev->irq, host);
2978 release_region(s->addr, 256);
2979 scsi_host_put(host);
2980 pci_disable_device(pdev);
3154} 2981}
3155MODULE_LICENSE("Dual BSD/GPL"); 2982
3156 2983MODULE_LICENSE("GPL");
3157static struct scsi_host_template driver_template = { 2984
3158 .proc_name = "INI9100U", 2985static struct pci_device_id initio_pci_tbl[] = {
3159 .name = i91u_REVID, 2986 {PCI_VENDOR_ID_INIT, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
3160 .detect = i91u_detect, 2987 {PCI_VENDOR_ID_INIT, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
3161 .release = i91u_release, 2988 {PCI_VENDOR_ID_INIT, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
3162 .queuecommand = i91u_queuecommand, 2989 {PCI_VENDOR_ID_INIT, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
3163// .abort = i91u_abort, 2990 {PCI_VENDOR_ID_DOMEX, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
3164// .reset = i91u_reset, 2991 {0,}
3165 .eh_bus_reset_handler = i91u_bus_reset, 2992};
3166 .bios_param = i91u_biosparam, 2993MODULE_DEVICE_TABLE(pci, initio_pci_tbl);
3167 .can_queue = 1, 2994
3168 .this_id = 1, 2995static struct pci_driver initio_pci_driver = {
3169 .sg_tablesize = SG_ALL, 2996 .name = "initio",
3170 .cmd_per_lun = 1, 2997 .id_table = initio_pci_tbl,
3171 .use_clustering = ENABLE_CLUSTERING, 2998 .probe = initio_probe_one,
2999 .remove = __devexit_p(initio_remove_one),
3172}; 3000};
3173#include "scsi_module.c"
3174 3001
3002static int __init initio_init_driver(void)
3003{
3004 return pci_register_driver(&initio_pci_driver);
3005}
3006
3007static void __exit initio_exit_driver(void)
3008{
3009 pci_unregister_driver(&initio_pci_driver);
3010}
3011
3012MODULE_DESCRIPTION("Initio INI-9X00U/UW SCSI device driver");
3013MODULE_AUTHOR("Initio Corporation");
3014MODULE_LICENSE("GPL");
3015
3016module_init(initio_init_driver);
3017module_exit(initio_exit_driver);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 19:57:13 -0500