diff options
author | Don Brace <brace@beardog.cce.hp.com> | 2010-02-04 09:42:40 -0500 |
---|---|---|
committer | James Bottomley <James.Bottomley@suse.de> | 2010-02-17 14:20:26 -0500 |
commit | 303932fd4ff63e8650d5d5da6cc286a8b5f8318d (patch) | |
tree | f48d9a236ffa5a43ed873d429243a12ceb19aa93 /drivers/scsi/hpsa_cmd.h | |
parent | 900c54404a9456b3ff10745e5e8f64b12c3a6ef7 (diff) |
[SCSI] hpsa: Allow multiple command completions per interrupt.
This is done by adding support for the so-called "performant mode"
(that's really what they called it). Smart Array controllers
have a mode which enables multiple command completions to be
delivered with a single interrupt, "performant" mode. We want to use
that mode, as some newer controllers will be requiring this mode.
Signed-off-by: Don Brace <brace@beardog.cce.hp.com>
Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com>
Signed-off-by: Mike Miller <mikem@beardog.cce.hp.com>
Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers/scsi/hpsa_cmd.h')
-rw-r--r-- | drivers/scsi/hpsa_cmd.h | 78 |
1 files changed, 63 insertions, 15 deletions
diff --git a/drivers/scsi/hpsa_cmd.h b/drivers/scsi/hpsa_cmd.h index 88bb3b0a21d3..3e0abdf76689 100644 --- a/drivers/scsi/hpsa_cmd.h +++ b/drivers/scsi/hpsa_cmd.h | |||
@@ -101,6 +101,7 @@ | |||
101 | #define CFGTBL_AccCmds 0x00000001l | 101 | #define CFGTBL_AccCmds 0x00000001l |
102 | 102 | ||
103 | #define CFGTBL_Trans_Simple 0x00000002l | 103 | #define CFGTBL_Trans_Simple 0x00000002l |
104 | #define CFGTBL_Trans_Performant 0x00000004l | ||
104 | 105 | ||
105 | #define CFGTBL_BusType_Ultra2 0x00000001l | 106 | #define CFGTBL_BusType_Ultra2 0x00000001l |
106 | #define CFGTBL_BusType_Ultra3 0x00000002l | 107 | #define CFGTBL_BusType_Ultra3 0x00000002l |
@@ -267,12 +268,31 @@ struct ErrorInfo { | |||
267 | #define CMD_IOCTL_PEND 0x01 | 268 | #define CMD_IOCTL_PEND 0x01 |
268 | #define CMD_SCSI 0x03 | 269 | #define CMD_SCSI 0x03 |
269 | 270 | ||
271 | /* This structure needs to be divisible by 32 for new | ||
272 | * indexing method and performant mode. | ||
273 | */ | ||
274 | #define PAD32 32 | ||
275 | #define PAD64DIFF 0 | ||
276 | #define USEEXTRA ((sizeof(void *) - 4)/4) | ||
277 | #define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA) | ||
278 | |||
279 | #define DIRECT_LOOKUP_SHIFT 5 | ||
280 | #define DIRECT_LOOKUP_BIT 0x10 | ||
281 | |||
282 | #define HPSA_ERROR_BIT 0x02 | ||
270 | struct ctlr_info; /* defined in hpsa.h */ | 283 | struct ctlr_info; /* defined in hpsa.h */ |
271 | /* The size of this structure needs to be divisible by 8 | 284 | /* The size of this structure needs to be divisible by 32 |
272 | * on all architectures, because the controller uses 2 | 285 | * on all architectures because low 5 bits of the addresses |
273 | * lower bits of the address, and the driver uses 1 lower | 286 | * are used as follows: |
274 | * bit (3 bits total.) | 287 | * |
288 | * bit 0: to device, used to indicate "performant mode" command | ||
289 | * from device, indidcates error status. | ||
290 | * bit 1-3: to device, indicates block fetch table entry for | ||
291 | * reducing DMA in fetching commands from host memory. | ||
292 | * bit 4: used to indicate whether tag is "direct lookup" (index), | ||
293 | * or a bus address. | ||
275 | */ | 294 | */ |
295 | |||
276 | struct CommandList { | 296 | struct CommandList { |
277 | struct CommandListHeader Header; | 297 | struct CommandListHeader Header; |
278 | struct RequestBlock Request; | 298 | struct RequestBlock Request; |
@@ -291,6 +311,14 @@ struct CommandList { | |||
291 | struct completion *waiting; | 311 | struct completion *waiting; |
292 | int retry_count; | 312 | int retry_count; |
293 | void *scsi_cmd; | 313 | void *scsi_cmd; |
314 | |||
315 | /* on 64 bit architectures, to get this to be 32-byte-aligned | ||
316 | * it so happens we need no padding, on 32 bit systems, | ||
317 | * we need 8 bytes of padding. This does that. | ||
318 | */ | ||
319 | #define COMMANDLIST_PAD ((8 - sizeof(long))/4 * 8) | ||
320 | u8 pad[COMMANDLIST_PAD]; | ||
321 | |||
294 | }; | 322 | }; |
295 | 323 | ||
296 | /* Configuration Table Structure */ | 324 | /* Configuration Table Structure */ |
@@ -301,18 +329,38 @@ struct HostWrite { | |||
301 | u32 CoalIntCount; | 329 | u32 CoalIntCount; |
302 | }; | 330 | }; |
303 | 331 | ||
332 | #define SIMPLE_MODE 0x02 | ||
333 | #define PERFORMANT_MODE 0x04 | ||
334 | #define MEMQ_MODE 0x08 | ||
335 | |||
304 | struct CfgTable { | 336 | struct CfgTable { |
305 | u8 Signature[4]; | 337 | u8 Signature[4]; |
306 | u32 SpecValence; | 338 | u32 SpecValence; |
307 | u32 TransportSupport; | 339 | u32 TransportSupport; |
308 | u32 TransportActive; | 340 | u32 TransportActive; |
309 | struct HostWrite HostWrite; | 341 | struct HostWrite HostWrite; |
310 | u32 CmdsOutMax; | 342 | u32 CmdsOutMax; |
311 | u32 BusTypes; | 343 | u32 BusTypes; |
312 | u32 Reserved; | 344 | u32 TransMethodOffset; |
313 | u8 ServerName[16]; | 345 | u8 ServerName[16]; |
314 | u32 HeartBeat; | 346 | u32 HeartBeat; |
315 | u32 SCSI_Prefetch; | 347 | u32 SCSI_Prefetch; |
348 | u32 MaxScatterGatherElements; | ||
349 | u32 MaxLogicalUnits; | ||
350 | u32 MaxPhysicalDevices; | ||
351 | u32 MaxPhysicalDrivesPerLogicalUnit; | ||
352 | u32 MaxPerformantModeCommands; | ||
353 | }; | ||
354 | |||
355 | #define NUM_BLOCKFETCH_ENTRIES 8 | ||
356 | struct TransTable_struct { | ||
357 | u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; | ||
358 | u32 RepQSize; | ||
359 | u32 RepQCount; | ||
360 | u32 RepQCtrAddrLow32; | ||
361 | u32 RepQCtrAddrHigh32; | ||
362 | u32 RepQAddr0Low32; | ||
363 | u32 RepQAddr0High32; | ||
316 | }; | 364 | }; |
317 | 365 | ||
318 | struct hpsa_pci_info { | 366 | struct hpsa_pci_info { |