diff options
author | Stephen M. Cameron <scameron@beardog.cce.hp.com> | 2012-05-01 12:42:30 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2012-05-10 04:11:43 -0400 |
commit | 2c17d2da8c9ef2c5be5077d3995041791e38094d (patch) | |
tree | a305edafa6170096b2cffc1100a38fbb33d7a28c /drivers/scsi/hpsa.h | |
parent | 21b8e4ef0357041854819d0f97bf1052ab4763e6 (diff) |
[SCSI] hpsa: do not read from controller unnecessarily in completion code
MSI/MSI-X interrupts can't race the DMA completion they are communicating
so no need to read from controller to flush the DMA to the host if
MSI or MSI-X interrupts are being used.
Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/hpsa.h')
-rw-r--r-- | drivers/scsi/hpsa.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h index 7b28d54fa878..48f78123d1e6 100644 --- a/drivers/scsi/hpsa.h +++ b/drivers/scsi/hpsa.h | |||
@@ -258,12 +258,12 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h) | |||
258 | { | 258 | { |
259 | unsigned long register_value = FIFO_EMPTY; | 259 | unsigned long register_value = FIFO_EMPTY; |
260 | 260 | ||
261 | /* flush the controller write of the reply queue by reading | ||
262 | * outbound doorbell status register. | ||
263 | */ | ||
264 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); | ||
265 | /* msi auto clears the interrupt pending bit. */ | 261 | /* msi auto clears the interrupt pending bit. */ |
266 | if (!(h->msi_vector || h->msix_vector)) { | 262 | if (!(h->msi_vector || h->msix_vector)) { |
263 | /* flush the controller write of the reply queue by reading | ||
264 | * outbound doorbell status register. | ||
265 | */ | ||
266 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); | ||
267 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); | 267 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); |
268 | /* Do a read in order to flush the write to the controller | 268 | /* Do a read in order to flush the write to the controller |
269 | * (as per spec.) | 269 | * (as per spec.) |