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authorArvind Bhushan <arvindb@chelsio.com>2013-03-14 01:09:07 -0400
committerDavid S. Miller <davem@davemloft.net>2013-03-14 11:36:00 -0400
commitd69630e8a42220b04318995d8ed0637ea79a717e (patch)
tree3e08568d2f0a4032aea5ad721f9d76ab819aa13d /drivers/scsi/csiostor
parent4a22edb593012041ee656a88ea7f9889837cb0d1 (diff)
csiostor: Header file modifications for chip support and bug fixes.
This patch defines the common operations to support multiple chips. It includes common header file modifications to support the current chips (T4 and T5). It also includes the following bug fixes: - reconfirms the rnode state after an implicit logo. - corrects the stats array size. - sets up and checks flags correctly when coming up as master and finding the card initialized Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Arvind Bhushan <arvindb@chelsio.com> Signed-off-by: Naresh Kumar Inna <naresh@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/scsi/csiostor')
-rw-r--r--drivers/scsi/csiostor/csio_hw_chip.h175
-rw-r--r--drivers/scsi/csiostor/csio_lnode.h2
-rw-r--r--drivers/scsi/csiostor/csio_rnode.c10
-rw-r--r--drivers/scsi/csiostor/csio_rnode.h2
-rw-r--r--drivers/scsi/csiostor/csio_wr.c41
5 files changed, 212 insertions, 18 deletions
diff --git a/drivers/scsi/csiostor/csio_hw_chip.h b/drivers/scsi/csiostor/csio_hw_chip.h
new file mode 100644
index 000000000000..bca0de61ae80
--- /dev/null
+++ b/drivers/scsi/csiostor/csio_hw_chip.h
@@ -0,0 +1,175 @@
1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef __CSIO_HW_CHIP_H__
35#define __CSIO_HW_CHIP_H__
36
37#include "csio_defs.h"
38
39/* FCoE device IDs for T4 */
40#define CSIO_DEVID_T440DBG_FCOE 0x4600
41#define CSIO_DEVID_T420CR_FCOE 0x4601
42#define CSIO_DEVID_T422CR_FCOE 0x4602
43#define CSIO_DEVID_T440CR_FCOE 0x4603
44#define CSIO_DEVID_T420BCH_FCOE 0x4604
45#define CSIO_DEVID_T440BCH_FCOE 0x4605
46#define CSIO_DEVID_T440CH_FCOE 0x4606
47#define CSIO_DEVID_T420SO_FCOE 0x4607
48#define CSIO_DEVID_T420CX_FCOE 0x4608
49#define CSIO_DEVID_T420BT_FCOE 0x4609
50#define CSIO_DEVID_T404BT_FCOE 0x460A
51#define CSIO_DEVID_B420_FCOE 0x460B
52#define CSIO_DEVID_B404_FCOE 0x460C
53#define CSIO_DEVID_T480CR_FCOE 0x460D
54#define CSIO_DEVID_T440LPCR_FCOE 0x460E
55#define CSIO_DEVID_AMSTERDAM_T4_FCOE 0x460F
56#define CSIO_DEVID_HUAWEI_T480_FCOE 0x4680
57#define CSIO_DEVID_HUAWEI_T440_FCOE 0x4681
58#define CSIO_DEVID_HUAWEI_STG310_FCOE 0x4682
59#define CSIO_DEVID_ACROMAG_XMC_XAUI 0x4683
60#define CSIO_DEVID_ACROMAG_XMC_SFP_FCOE 0x4684
61#define CSIO_DEVID_QUANTA_MEZZ_SFP_FCOE 0x4685
62#define CSIO_DEVID_HUAWEI_10GT_FCOE 0x4686
63#define CSIO_DEVID_HUAWEI_T440_TOE_FCOE 0x4687
64
65/* FCoE device IDs for T5 */
66#define CSIO_DEVID_T580DBG_FCOE 0x5600
67#define CSIO_DEVID_T520CR_FCOE 0x5601
68#define CSIO_DEVID_T522CR_FCOE 0x5602
69#define CSIO_DEVID_T540CR_FCOE 0x5603
70#define CSIO_DEVID_T520BCH_FCOE 0x5604
71#define CSIO_DEVID_T540BCH_FCOE 0x5605
72#define CSIO_DEVID_T540CH_FCOE 0x5606
73#define CSIO_DEVID_T520SO_FCOE 0x5607
74#define CSIO_DEVID_T520CX_FCOE 0x5608
75#define CSIO_DEVID_T520BT_FCOE 0x5609
76#define CSIO_DEVID_T504BT_FCOE 0x560A
77#define CSIO_DEVID_B520_FCOE 0x560B
78#define CSIO_DEVID_B504_FCOE 0x560C
79#define CSIO_DEVID_T580CR2_FCOE 0x560D
80#define CSIO_DEVID_T540LPCR_FCOE 0x560E
81#define CSIO_DEVID_AMSTERDAM_T5_FCOE 0x560F
82#define CSIO_DEVID_T580LPCR_FCOE 0x5610
83#define CSIO_DEVID_T520LLCR_FCOE 0x5611
84#define CSIO_DEVID_T560CR_FCOE 0x5612
85#define CSIO_DEVID_T580CR_FCOE 0x5613
86
87/* Define MACRO values */
88#define CSIO_HW_T4 0x4000
89#define CSIO_T4_FCOE_ASIC 0x4600
90#define CSIO_HW_T5 0x5000
91#define CSIO_T5_FCOE_ASIC 0x5600
92#define CSIO_HW_CHIP_MASK 0xF000
93#define T4_REGMAP_SIZE (160 * 1024)
94#define T5_REGMAP_SIZE (332 * 1024)
95#define FW_FNAME_T4 "cxgb4/t4fw.bin"
96#define FW_FNAME_T5 "cxgb4/t5fw.bin"
97#define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
98#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
99
100/* Define static functions */
101static inline int csio_is_t4(uint16_t chip)
102{
103 return (chip == CSIO_HW_T4);
104}
105
106static inline int csio_is_t5(uint16_t chip)
107{
108 return (chip == CSIO_HW_T5);
109}
110
111/* Define MACRO DEFINITIONS */
112#define CSIO_DEVICE(devid, idx) \
113 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
114
115#define CSIO_HW_PIDX(hw, index) \
116 (csio_is_t4(hw->chip_id) ? (PIDX(index)) : \
117 (PIDX_T5(index) | DBTYPE(1U)))
118
119#define CSIO_HW_LP_INT_THRESH(hw, val) \
120 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \
121 (V_LP_INT_THRESH_T5(val)))
122
123#define CSIO_HW_M_LP_INT_THRESH(hw) \
124 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
125
126#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
127 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
128 (T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
129
130#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
131#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
132#define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
133
134#define CSIO_FW_FNAME(hw) \
135 (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
136
137#define CSIO_CF_FNAME(hw) \
138 (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
139
140/* Declare ENUMS */
141enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
142
143enum {
144 MEMWIN_APERTURE = 2048,
145 MEMWIN_BASE = 0x1b800,
146 MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
147};
148
149/* Slow path handlers */
150struct intr_info {
151 unsigned int mask; /* bits to check in interrupt status */
152 const char *msg; /* message to print or NULL */
153 short stat_idx; /* stat counter to increment or -1 */
154 unsigned short fatal; /* whether the condition reported is fatal */
155};
156
157/* T4/T5 Chip specific ops */
158struct csio_hw;
159struct csio_hw_chip_ops {
160 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
161 void (*chip_pcie_intr_handler)(struct csio_hw *);
162 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
163 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
164 __be32 *, uint64_t *);
165 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
166 __be32 *, uint64_t *);
167 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
168 u32, uint32_t *, int);
169 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
170};
171
172extern struct csio_hw_chip_ops t4_ops;
173extern struct csio_hw_chip_ops t5_ops;
174
175#endif /* #ifndef __CSIO_HW_CHIP_H__ */
diff --git a/drivers/scsi/csiostor/csio_lnode.h b/drivers/scsi/csiostor/csio_lnode.h
index 8d84988ab06d..0f9c04175b11 100644
--- a/drivers/scsi/csiostor/csio_lnode.h
+++ b/drivers/scsi/csiostor/csio_lnode.h
@@ -114,7 +114,7 @@ struct csio_lnode_stats {
114 uint32_t n_rnode_match; /* matched rnode */ 114 uint32_t n_rnode_match; /* matched rnode */
115 uint32_t n_dev_loss_tmo; /* Device loss timeout */ 115 uint32_t n_dev_loss_tmo; /* Device loss timeout */
116 uint32_t n_fdmi_err; /* fdmi err */ 116 uint32_t n_fdmi_err; /* fdmi err */
117 uint32_t n_evt_fw[RSCN_DEV_LOST]; /* fw events */ 117 uint32_t n_evt_fw[PROTO_ERR_IMPL_LOGO]; /* fw events */
118 enum csio_ln_ev n_evt_sm[CSIO_LNE_MAX_EVENT]; /* State m/c events */ 118 enum csio_ln_ev n_evt_sm[CSIO_LNE_MAX_EVENT]; /* State m/c events */
119 uint32_t n_rnode_alloc; /* rnode allocated */ 119 uint32_t n_rnode_alloc; /* rnode allocated */
120 uint32_t n_rnode_free; /* rnode freed */ 120 uint32_t n_rnode_free; /* rnode freed */
diff --git a/drivers/scsi/csiostor/csio_rnode.c b/drivers/scsi/csiostor/csio_rnode.c
index 51c6a388de2b..e9c3b045f587 100644
--- a/drivers/scsi/csiostor/csio_rnode.c
+++ b/drivers/scsi/csiostor/csio_rnode.c
@@ -302,7 +302,7 @@ csio_confirm_rnode(struct csio_lnode *ln, uint32_t rdev_flowid,
302{ 302{
303 uint8_t rport_type; 303 uint8_t rport_type;
304 struct csio_rnode *rn, *match_rn; 304 struct csio_rnode *rn, *match_rn;
305 uint32_t vnp_flowid; 305 uint32_t vnp_flowid = 0;
306 __be32 *port_id; 306 __be32 *port_id;
307 307
308 port_id = (__be32 *)&rdevp->r_id[0]; 308 port_id = (__be32 *)&rdevp->r_id[0];
@@ -350,6 +350,14 @@ csio_confirm_rnode(struct csio_lnode *ln, uint32_t rdev_flowid,
350 * Else, go ahead and alloc a new rnode. 350 * Else, go ahead and alloc a new rnode.
351 */ 351 */
352 if (!memcmp(csio_rn_wwpn(match_rn), rdevp->wwpn, 8)) { 352 if (!memcmp(csio_rn_wwpn(match_rn), rdevp->wwpn, 8)) {
353 if (rn == match_rn)
354 goto found_rnode;
355 csio_ln_dbg(ln,
356 "nport_id:x%x and wwpn:%llx"
357 " match for ssni:x%x\n",
358 rn->nport_id,
359 wwn_to_u64(rdevp->wwpn),
360 rdev_flowid);
353 if (csio_is_rnode_ready(rn)) { 361 if (csio_is_rnode_ready(rn)) {
354 csio_ln_warn(ln, 362 csio_ln_warn(ln,
355 "rnode is already" 363 "rnode is already"
diff --git a/drivers/scsi/csiostor/csio_rnode.h b/drivers/scsi/csiostor/csio_rnode.h
index a3b434c801da..65940096a80d 100644
--- a/drivers/scsi/csiostor/csio_rnode.h
+++ b/drivers/scsi/csiostor/csio_rnode.h
@@ -63,7 +63,7 @@ struct csio_rnode_stats {
63 uint32_t n_err_nomem; /* error nomem */ 63 uint32_t n_err_nomem; /* error nomem */
64 uint32_t n_evt_unexp; /* unexpected event */ 64 uint32_t n_evt_unexp; /* unexpected event */
65 uint32_t n_evt_drop; /* unexpected event */ 65 uint32_t n_evt_drop; /* unexpected event */
66 uint32_t n_evt_fw[RSCN_DEV_LOST]; /* fw events */ 66 uint32_t n_evt_fw[PROTO_ERR_IMPL_LOGO]; /* fw events */
67 enum csio_rn_ev n_evt_sm[CSIO_RNFE_MAX_EVENT]; /* State m/c events */ 67 enum csio_rn_ev n_evt_sm[CSIO_RNFE_MAX_EVENT]; /* State m/c events */
68 uint32_t n_lun_rst; /* Number of resets of 68 uint32_t n_lun_rst; /* Number of resets of
69 * of LUNs under this 69 * of LUNs under this
diff --git a/drivers/scsi/csiostor/csio_wr.c b/drivers/scsi/csiostor/csio_wr.c
index c32df1bdaa97..713e77d12cb4 100644
--- a/drivers/scsi/csiostor/csio_wr.c
+++ b/drivers/scsi/csiostor/csio_wr.c
@@ -1331,14 +1331,21 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
1331 1331
1332 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */ 1332 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
1333 csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0); 1333 csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0);
1334 csio_wr_reg32(hw, 1334
1335 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) + 1335 /*
1336 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1), 1336 * If using hard params, the following will get set correctly
1337 SGE_FL_BUFFER_SIZE2); 1337 * in csio_wr_set_sge().
1338 csio_wr_reg32(hw, 1338 */
1339 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) + 1339 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) {
1340 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1), 1340 csio_wr_reg32(hw,
1341 SGE_FL_BUFFER_SIZE3); 1341 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) +
1342 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
1343 SGE_FL_BUFFER_SIZE2);
1344 csio_wr_reg32(hw,
1345 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) +
1346 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
1347 SGE_FL_BUFFER_SIZE3);
1348 }
1342 1349
1343 csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ); 1350 csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ);
1344 1351
@@ -1470,8 +1477,10 @@ csio_wr_set_sge(struct csio_hw *hw)
1470 /* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */ 1477 /* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */
1471 1478
1472 CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1); 1479 CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1);
1473 CSIO_SET_FLBUF_SIZE(hw, 2, CSIO_SGE_FLBUF_SIZE2); 1480 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1)
1474 CSIO_SET_FLBUF_SIZE(hw, 3, CSIO_SGE_FLBUF_SIZE3); 1481 & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2);
1482 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1)
1483 & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3);
1475 CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4); 1484 CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4);
1476 CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5); 1485 CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5);
1477 CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6); 1486 CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6);
@@ -1522,22 +1531,24 @@ void
1522csio_wr_sge_init(struct csio_hw *hw) 1531csio_wr_sge_init(struct csio_hw *hw)
1523{ 1532{
1524 /* 1533 /*
1525 * If we are master: 1534 * If we are master and chip is not initialized:
1526 * - If we plan to use the config file, we need to fixup some 1535 * - If we plan to use the config file, we need to fixup some
1527 * host specific registers, and read the rest of the SGE 1536 * host specific registers, and read the rest of the SGE
1528 * configuration. 1537 * configuration.
1529 * - If we dont plan to use the config file, we need to initialize 1538 * - If we dont plan to use the config file, we need to initialize
1530 * SGE entirely, including fixing the host specific registers. 1539 * SGE entirely, including fixing the host specific registers.
1540 * If we are master and chip is initialized, just read and work off of
1541 * the already initialized SGE values.
1531 * If we arent the master, we are only allowed to read and work off of 1542 * If we arent the master, we are only allowed to read and work off of
1532 * the already initialized SGE values. 1543 * the already initialized SGE values.
1533 * 1544 *
1534 * Therefore, before calling this function, we assume that the master- 1545 * Therefore, before calling this function, we assume that the master-
1535 * ship of the card, and whether to use config file or not, have 1546 * ship of the card, state and whether to use config file or not, have
1536 * already been decided. In other words, CSIO_HWF_USING_SOFT_PARAMS and 1547 * already been decided.
1537 * CSIO_HWF_MASTER should be set/unset.
1538 */ 1548 */
1539 if (csio_is_hw_master(hw)) { 1549 if (csio_is_hw_master(hw)) {
1540 csio_wr_fixup_host_params(hw); 1550 if (hw->fw_state != CSIO_DEV_STATE_INIT)
1551 csio_wr_fixup_host_params(hw);
1541 1552
1542 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) 1553 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS)
1543 csio_wr_get_sge(hw); 1554 csio_wr_get_sge(hw);