csiostor: Cleanup chip specific operations.

This patch removes chip specific operations from the common hardware
paths, as well as the Makefile change to accomodate the new files.

Signed-off-by: Arvind Bhushan <arvindb@chelsio.com>
Signed-off-by: Naresh Kumar Inna <naresh@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 18 insertions, 29 deletions

diff --git a/drivers/scsi/csiostor/csio_hw.h b/drivers/scsi/csiostor/csio_hw.h
index 9edcca4c71af..489fc095cb03 100644
--- a/drivers/scsi/csiostor/csio_hw.h
+++ b/drivers/scsi/csiostor/csio_hw.h
@@ -48,6 +48,7 @@
 #include <scsi/scsi_device.h>
 #include <scsi/scsi_transport_fc.h>
 
+#include "csio_hw_chip.h"
 #include "csio_wr.h"
 #include "csio_mb.h"
 #include "csio_scsi.h"
@@ -60,13 +61,6 @@
  */
 #define FW_HOSTERROR                    255
 
-#define CSIO_FW_FNAME           "cxgb4/t4fw.bin"
-#define CSIO_CF_FNAME           "cxgb4/t4-config.txt"
-
-#define FW_VERSION_MAJOR        1
-#define FW_VERSION_MINOR        2
-#define FW_VERSION_MICRO        8
-
 #define CSIO_HW_NAME            "Chelsio FCoE Adapter"
 #define CSIO_MAX_PFN            8
 #define CSIO_MAX_PPORTS         4
@@ -123,8 +117,6 @@ extern int csio_msi;
 #define CSIO_VENDOR_ID                          0x1425
 #define CSIO_ASIC_DEVID_PROTO_MASK              0xFF00
 #define CSIO_ASIC_DEVID_TYPE_MASK               0x00FF
-#define CSIO_FPGA                               0xA000
-#define CSIO_T4_FCOE_ASIC                       0x4600
 
 #define CSIO_GLBL_INTR_MASK             (CIM | MPS | PL | PCIE | MC | EDC0 | \
                                          EDC1 | LE | TP | MA | PM_TX | PM_RX | \
@@ -207,17 +199,6 @@ enum {
         SF_SIZE = SF_SEC_SIZE * 16,   /* serial flash size */
 };
 
-enum { MEM_EDC0, MEM_EDC1, MEM_MC };
-
-enum {
-        MEMWIN0_APERTURE = 2048,
-        MEMWIN0_BASE     = 0x1b800,
-        MEMWIN1_APERTURE = 32768,
-        MEMWIN1_BASE     = 0x28000,
-        MEMWIN2_APERTURE = 65536,
-        MEMWIN2_BASE     = 0x30000,
-};
-
 /* serial flash and firmware constants */
 enum {
         SF_ATTEMPTS = 10,             /* max retries for SF operations */
@@ -239,9 +220,6 @@ enum {
         FLASH_CFG_MAX_SIZE    = 0x10000 , /* max size of the flash config file*/
         FLASH_CFG_OFFSET      = 0x1f0000,
         FLASH_CFG_START_SEC   = FLASH_CFG_OFFSET / SF_SEC_SIZE,
-        FPGA_FLASH_CFG_OFFSET = 0xf0000 , /* if FPGA mode, then cfg file is
-                                           * at 1MB - 64KB */
-        FPGA_FLASH_CFG_START_SEC  = FPGA_FLASH_CFG_OFFSET / SF_SEC_SIZE,
 };
 
 /*
@@ -259,6 +237,8 @@ enum {
         FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
         FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
 
+        /* Location of Firmware Configuration File in FLASH. */
+        FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
 };
 
 #undef FLASH_START
@@ -310,7 +290,7 @@ struct csio_adap_desc {
 struct pci_params {
         uint16_t   vendor_id;
         uint16_t   device_id;
-        uint32_t   vpd_cap_addr;
+        int        vpd_cap_addr;
         uint16_t   speed;
         uint8_t    width;
 };
@@ -513,6 +493,7 @@ struct csio_hw {
         uint32_t                fwrev;
         uint32_t                tp_vers;
         char                    chip_ver;
+        uint16_t                chip_id;                /* Tells T4/T5 chip */
         uint32_t                cfg_finiver;
         uint32_t                cfg_finicsum;
         uint32_t                cfg_cfcsum;
@@ -556,6 +537,9 @@ struct csio_hw {
                                                          */
 
         struct csio_fcoe_res_info  fres_info;           /* Fcoe resource info */
+        struct csio_hw_chip_ops *chip_ops;              /* T4/T5 Chip specific
+                                                         * Operations
+                                                         */
 
         /* MSIX vectors */
         struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
@@ -636,9 +620,16 @@ csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
 #define csio_dbg(__hw, __fmt, ...)
 #endif
 
+int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
+                             int, int, uint32_t *);
+void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
+                                 unsigned int, unsigned int);
 int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
 void csio_hw_intr_disable(struct csio_hw *);
-int csio_hw_slow_intr_handler(struct csio_hw *hw);
+int csio_hw_slow_intr_handler(struct csio_hw *);
+int csio_handle_intr_status(struct csio_hw *, unsigned int,
+                            const struct intr_info *);
+
 int csio_hw_start(struct csio_hw *);
 int csio_hw_stop(struct csio_hw *);
 int csio_hw_reset(struct csio_hw *);
@@ -647,19 +638,17 @@ int csio_is_hw_removing(struct csio_hw *);
 
 int csio_fwevtq_handler(struct csio_hw *);
 void csio_evtq_worker(struct work_struct *);
-int csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type,
-                                void *evt_msg, uint16_t len);
+int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
 void csio_evtq_flush(struct csio_hw *hw);
 
 int csio_request_irqs(struct csio_hw *);
 void csio_intr_enable(struct csio_hw *);
 void csio_intr_disable(struct csio_hw *, bool);
+void csio_hw_fatal_err(struct csio_hw *);
 
 struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
 int csio_config_queues(struct csio_hw *);
 
-int csio_hw_mc_read(struct csio_hw *, uint32_t, __be32 *, uint64_t *);
-int csio_hw_edc_read(struct csio_hw *, int, uint32_t, __be32 *, uint64_t *);
 int csio_hw_init(struct csio_hw *);
 void csio_hw_exit(struct csio_hw *);
 #endif /* ifndef __CSIO_HW_H__ */