diff options
author | Krishna Gudipati <kgudipat@brocade.com> | 2011-06-13 18:50:35 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2011-06-29 16:31:31 -0400 |
commit | 111892082ed7a3214bc7a7ec6b8b20e8f847501a (patch) | |
tree | fb4950f69aaf7c2bf07ce8987884bb52aa497ffa /drivers/scsi/bfa/bfa_ioc_cb.c | |
parent | 43ffdf4dfb827babcdca5345a76031598a985dc8 (diff) |
[SCSI] bfa: Brocade-1860 Fabric Adapter Hardware Enablement
- Added support for Brocade-1860 Fabric Adapter.
- Made changes to support single firmware image per asic type.
- Combined bfi_cbreg.h and bfi_ctreg.h defines into bfi_reg.h with
only minimal defines used by host.
- Added changes to setup CPE/RME Queue register offsets based on
firmware response.
- Removed queue register offset initializations and added register offsets
to BFI config response message.
- Added Brocade-1860 asic specific interrupt status definitions and
mailbox interfaces.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/bfa/bfa_ioc_cb.c')
-rw-r--r-- | drivers/scsi/bfa/bfa_ioc_cb.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c index 89ae4c8f95a2..e858bc0c48d0 100644 --- a/drivers/scsi/bfa/bfa_ioc_cb.c +++ b/drivers/scsi/bfa/bfa_ioc_cb.c | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | #include "bfad_drv.h" | 18 | #include "bfad_drv.h" |
19 | #include "bfa_ioc.h" | 19 | #include "bfa_ioc.h" |
20 | #include "bfi_cbreg.h" | 20 | #include "bfi_reg.h" |
21 | #include "bfa_defs.h" | 21 | #include "bfa_defs.h" |
22 | 22 | ||
23 | BFA_TRC_FILE(CNA, IOC_CB); | 23 | BFA_TRC_FILE(CNA, IOC_CB); |
@@ -77,7 +77,7 @@ bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) | |||
77 | 77 | ||
78 | bfa_ioc_fwver_get(ioc, &fwhdr); | 78 | bfa_ioc_fwver_get(ioc, &fwhdr); |
79 | 79 | ||
80 | if (swab32(fwhdr.exec) == BFI_BOOT_TYPE_NORMAL) | 80 | if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL) |
81 | return BFA_TRUE; | 81 | return BFA_TRUE; |
82 | 82 | ||
83 | bfa_trc(ioc, fwstate); | 83 | bfa_trc(ioc, fwstate); |
@@ -98,7 +98,7 @@ bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc) | |||
98 | static void | 98 | static void |
99 | bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) | 99 | bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) |
100 | { | 100 | { |
101 | writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set); | 101 | writel(~0U, ioc->ioc_regs.err_set); |
102 | readl(ioc->ioc_regs.err_set); | 102 | readl(ioc->ioc_regs.err_set); |
103 | } | 103 | } |
104 | 104 | ||
@@ -152,8 +152,8 @@ bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) | |||
152 | */ | 152 | */ |
153 | ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); | 153 | ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); |
154 | ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); | 154 | ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); |
155 | ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG); | 155 | ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG); |
156 | ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG); | 156 | ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG); |
157 | 157 | ||
158 | /* | 158 | /* |
159 | * IOC semaphore registers and serialization | 159 | * IOC semaphore registers and serialization |
@@ -285,18 +285,18 @@ bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc) | |||
285 | } | 285 | } |
286 | 286 | ||
287 | bfa_status_t | 287 | bfa_status_t |
288 | bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode) | 288 | bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode) |
289 | { | 289 | { |
290 | u32 pll_sclk, pll_fclk; | 290 | u32 pll_sclk, pll_fclk; |
291 | 291 | ||
292 | pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN | | 292 | pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN | |
293 | __APP_PLL_212_P0_1(3U) | | 293 | __APP_PLL_SCLK_P0_1(3U) | |
294 | __APP_PLL_212_JITLMT0_1(3U) | | 294 | __APP_PLL_SCLK_JITLMT0_1(3U) | |
295 | __APP_PLL_212_CNTLMT0_1(3U); | 295 | __APP_PLL_SCLK_CNTLMT0_1(3U); |
296 | pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN | | 296 | pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN | |
297 | __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) | | 297 | __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) | |
298 | __APP_PLL_400_JITLMT0_1(3U) | | 298 | __APP_PLL_LCLK_JITLMT0_1(3U) | |
299 | __APP_PLL_400_CNTLMT0_1(3U); | 299 | __APP_PLL_LCLK_CNTLMT0_1(3U); |
300 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); | 300 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); |
301 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); | 301 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); |
302 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); | 302 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); |
@@ -305,24 +305,24 @@ bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode) | |||
305 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); | 305 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); |
306 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); | 306 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); |
307 | writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); | 307 | writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); |
308 | writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); | 308 | writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); |
309 | writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET, | 309 | writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET, |
310 | rb + APP_PLL_212_CTL_REG); | 310 | rb + APP_PLL_SCLK_CTL_REG); |
311 | writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); | 311 | writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); |
312 | writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET, | 312 | writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET, |
313 | rb + APP_PLL_400_CTL_REG); | 313 | rb + APP_PLL_LCLK_CTL_REG); |
314 | udelay(2); | 314 | udelay(2); |
315 | writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); | 315 | writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); |
316 | writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); | 316 | writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); |
317 | writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET, | 317 | writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET, |
318 | rb + APP_PLL_212_CTL_REG); | 318 | rb + APP_PLL_SCLK_CTL_REG); |
319 | writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET, | 319 | writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET, |
320 | rb + APP_PLL_400_CTL_REG); | 320 | rb + APP_PLL_LCLK_CTL_REG); |
321 | udelay(2000); | 321 | udelay(2000); |
322 | writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); | 322 | writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); |
323 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); | 323 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); |
324 | writel(pll_sclk, (rb + APP_PLL_212_CTL_REG)); | 324 | writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG)); |
325 | writel(pll_fclk, (rb + APP_PLL_400_CTL_REG)); | 325 | writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG)); |
326 | 326 | ||
327 | return BFA_STATUS_OK; | 327 | return BFA_STATUS_OK; |
328 | } | 328 | } |