diff options
author | Jing Huang <huangj@brocade.com> | 2009-09-23 20:46:15 -0400 |
---|---|---|
committer | James Bottomley <James.Bottomley@suse.de> | 2009-10-02 10:47:40 -0400 |
commit | 7725ccfda59715ecf8f99e3b520a0b84cc2ea79e (patch) | |
tree | df76910891c6b92bf23c06c84955bf600c9d7573 /drivers/scsi/bfa/bfa_hw_ct.c | |
parent | 5415907af1f5ef80c95147bacbd321b0d4236dd5 (diff) |
[SCSI] bfa: Brocade BFA FC SCSI driver
Add new driver for Brocade Hardware
Signed-off-by: Jing Huang <huangj@brocade.com>
Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers/scsi/bfa/bfa_hw_ct.c')
-rw-r--r-- | drivers/scsi/bfa/bfa_hw_ct.c | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/drivers/scsi/bfa/bfa_hw_ct.c b/drivers/scsi/bfa/bfa_hw_ct.c new file mode 100644 index 000000000000..51ae5740e6e9 --- /dev/null +++ b/drivers/scsi/bfa/bfa_hw_ct.c | |||
@@ -0,0 +1,162 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. | ||
3 | * All rights reserved | ||
4 | * www.brocade.com | ||
5 | * | ||
6 | * Linux driver for Brocade Fibre Channel Host Bus Adapter. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License (GPL) Version 2 as | ||
10 | * published by the Free Software Foundation | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but | ||
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
15 | * General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #include <bfa_priv.h> | ||
19 | #include <bfi/bfi_ctreg.h> | ||
20 | #include <bfa_ioc.h> | ||
21 | |||
22 | BFA_TRC_FILE(HAL, IOCFC_CT); | ||
23 | |||
24 | static u32 __ct_msix_err_vec_reg[] = { | ||
25 | HOST_MSIX_ERR_INDEX_FN0, | ||
26 | HOST_MSIX_ERR_INDEX_FN1, | ||
27 | HOST_MSIX_ERR_INDEX_FN2, | ||
28 | HOST_MSIX_ERR_INDEX_FN3, | ||
29 | }; | ||
30 | |||
31 | static void | ||
32 | bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec) | ||
33 | { | ||
34 | int fn = bfa_ioc_pcifn(&bfa->ioc); | ||
35 | bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); | ||
36 | |||
37 | if (msix) | ||
38 | bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], vec); | ||
39 | else | ||
40 | bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], 0); | ||
41 | } | ||
42 | |||
43 | /** | ||
44 | * Dummy interrupt handler for handling spurious interrupt during chip-reinit. | ||
45 | */ | ||
46 | static void | ||
47 | bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec) | ||
48 | { | ||
49 | } | ||
50 | |||
51 | void | ||
52 | bfa_hwct_reginit(struct bfa_s *bfa) | ||
53 | { | ||
54 | struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; | ||
55 | bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); | ||
56 | int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); | ||
57 | |||
58 | if (fn == 0) { | ||
59 | bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); | ||
60 | bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); | ||
61 | } else { | ||
62 | bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); | ||
63 | bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); | ||
64 | } | ||
65 | |||
66 | for (i = 0; i < BFI_IOC_MAX_CQS; i++) { | ||
67 | /* | ||
68 | * CPE registers | ||
69 | */ | ||
70 | q = CPE_Q_NUM(fn, i); | ||
71 | bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5)); | ||
72 | bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5)); | ||
73 | bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5)); | ||
74 | bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5)); | ||
75 | |||
76 | /* | ||
77 | * RME registers | ||
78 | */ | ||
79 | q = CPE_Q_NUM(fn, i); | ||
80 | bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5)); | ||
81 | bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5)); | ||
82 | bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5)); | ||
83 | bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5)); | ||
84 | } | ||
85 | } | ||
86 | |||
87 | void | ||
88 | bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq) | ||
89 | { | ||
90 | u32 r32; | ||
91 | |||
92 | r32 = bfa_reg_read(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); | ||
93 | bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq], r32); | ||
94 | } | ||
95 | |||
96 | void | ||
97 | bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, | ||
98 | u32 *num_vecs, u32 *max_vec_bit) | ||
99 | { | ||
100 | *msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1; | ||
101 | *max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1)); | ||
102 | *num_vecs = BFA_MSIX_CT_MAX; | ||
103 | } | ||
104 | |||
105 | /** | ||
106 | * Setup MSI-X vector for catapult | ||
107 | */ | ||
108 | void | ||
109 | bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs) | ||
110 | { | ||
111 | bfa_assert((nvecs == 1) || (nvecs == BFA_MSIX_CT_MAX)); | ||
112 | bfa_trc(bfa, nvecs); | ||
113 | |||
114 | bfa->msix.nvecs = nvecs; | ||
115 | bfa_hwct_msix_uninstall(bfa); | ||
116 | } | ||
117 | |||
118 | void | ||
119 | bfa_hwct_msix_install(struct bfa_s *bfa) | ||
120 | { | ||
121 | int i; | ||
122 | |||
123 | if (bfa->msix.nvecs == 0) | ||
124 | return; | ||
125 | |||
126 | if (bfa->msix.nvecs == 1) { | ||
127 | for (i = 0; i < BFA_MSIX_CT_MAX; i++) | ||
128 | bfa->msix.handler[i] = bfa_msix_all; | ||
129 | return; | ||
130 | } | ||
131 | |||
132 | for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++) | ||
133 | bfa->msix.handler[i] = bfa_msix_reqq; | ||
134 | |||
135 | for (; i <= BFA_MSIX_RME_Q3; i++) | ||
136 | bfa->msix.handler[i] = bfa_msix_rspq; | ||
137 | |||
138 | bfa_assert(i == BFA_MSIX_LPU_ERR); | ||
139 | bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err; | ||
140 | } | ||
141 | |||
142 | void | ||
143 | bfa_hwct_msix_uninstall(struct bfa_s *bfa) | ||
144 | { | ||
145 | int i; | ||
146 | |||
147 | for (i = 0; i < BFA_MSIX_CT_MAX; i++) | ||
148 | bfa->msix.handler[i] = bfa_hwct_msix_dummy; | ||
149 | } | ||
150 | |||
151 | /** | ||
152 | * Enable MSI-X vectors | ||
153 | */ | ||
154 | void | ||
155 | bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) | ||
156 | { | ||
157 | bfa_trc(bfa, 0); | ||
158 | bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR); | ||
159 | bfa_ioc_isr_mode_set(&bfa->ioc, msix); | ||
160 | } | ||
161 | |||
162 | |||