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authorJayamohan Kallickal <jayamohank@gmail.com>2013-09-28 18:35:46 -0400
committerJames Bottomley <JBottomley@Parallels.com>2013-10-25 04:58:06 -0400
commita129d92fc3e202d8135112a7ac7ad48849ab6812 (patch)
tree7c4a2b6ea396018808c622d35bea0a69a032f4fd /drivers/scsi/be2iscsi
parent8a86e8336f37fde1d62bd731e82ca5b22a678926 (diff)
[SCSI] be2iscsi: Fix Template HDR support for Dual Chute mode
Template HDR is created for each chute which has iSCSI Protocol loaded. For BE-X family iSCSI protocol is loaded only on single chute. Signed-off-by: John Soni Jose <sony.john-n@emulex.com> Signed-off-by: Jayamohan Kallickal <jayamohan.kallickal@emulex.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/be2iscsi')
-rw-r--r--drivers/scsi/be2iscsi/be_main.c43
-rw-r--r--drivers/scsi/be2iscsi/be_main.h13
2 files changed, 33 insertions, 23 deletions
diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c
index 779be2b3ede8..942a8969ce0d 100644
--- a/drivers/scsi/be2iscsi/be_main.c
+++ b/drivers/scsi/be2iscsi/be_main.c
@@ -2539,8 +2539,6 @@ static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2539 phba->params.icds_per_ctrl; 2539 phba->params.icds_per_ctrl;
2540 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * 2540 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2541 phba->params.num_sge_per_io * phba->params.icds_per_ctrl; 2541 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
2542 phba->mem_req[HWI_MEM_TEMPLATE_HDR] = phba->params.cxns_per_ctrl *
2543 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2544 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2542 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2545 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2543 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
2546 2544
@@ -2564,6 +2562,12 @@ static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2564 phba, ulp_num) * 2562 phba, ulp_num) *
2565 sizeof(struct phys_addr)); 2563 sizeof(struct phys_addr));
2566 2564
2565 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2566 (ulp_num * MEM_DESCR_OFFSET));
2567 phba->mem_req[mem_descr_index] =
2568 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2569 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2570
2567 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2571 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2568 (ulp_num * MEM_DESCR_OFFSET)); 2572 (ulp_num * MEM_DESCR_OFFSET));
2569 phba->mem_req[mem_descr_index] = 2573 phba->mem_req[mem_descr_index] =
@@ -3405,26 +3409,31 @@ beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3405 struct be_mem_descriptor *mem_descr; 3409 struct be_mem_descriptor *mem_descr;
3406 struct mem_array *pm_arr; 3410 struct mem_array *pm_arr;
3407 struct be_dma_mem sgl; 3411 struct be_dma_mem sgl;
3408 int status, i; 3412 int status, ulp_num;
3409 3413
3410 mem_descr = phba->init_mem; 3414 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3411 mem_descr += HWI_MEM_TEMPLATE_HDR; 3415 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3412 pm_arr = mem_descr->mem_array; 3416 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3417 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3418 (ulp_num * MEM_DESCR_OFFSET);
3419 pm_arr = mem_descr->mem_array;
3413 3420
3414 for (i = 0; i < mem_descr->num_elements; i++) { 3421 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3415 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3422 status = be_cmd_iscsi_post_template_hdr(
3416 status = be_cmd_iscsi_post_template_hdr(&phba->ctrl, &sgl); 3423 &phba->ctrl, &sgl);
3417 3424
3418 if (status != 0) { 3425 if (status != 0) {
3419 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3426 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3420 "BM_%d : Post Template HDR Failed\n"); 3427 "BM_%d : Post Template HDR Failed for"
3421 return status; 3428 "ULP_%d\n", ulp_num);
3429 return status;
3430 }
3431
3432 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3433 "BM_%d : Template HDR Pages Posted for"
3434 "ULP_%d\n", ulp_num);
3422 } 3435 }
3423 } 3436 }
3424
3425 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3426 "BM_%d : Template HDR Pages Posted\n");
3427
3428 return 0; 3437 return 0;
3429} 3438}
3430 3439
diff --git a/drivers/scsi/be2iscsi/be_main.h b/drivers/scsi/be2iscsi/be_main.h
index d0bbf373cb2e..bb96ba4f6468 100644
--- a/drivers/scsi/be2iscsi/be_main.h
+++ b/drivers/scsi/be2iscsi/be_main.h
@@ -161,7 +161,7 @@
161 161
162#define BEISCSI_MSI_NAME 20 /* size of msi_name string */ 162#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
163 163
164#define MEM_DESCR_OFFSET 7 164#define MEM_DESCR_OFFSET 8
165#define BEISCSI_DEFQ_HDR 1 165#define BEISCSI_DEFQ_HDR 1
166#define BEISCSI_DEFQ_DATA 0 166#define BEISCSI_DEFQ_DATA 0
167enum be_mem_enum { 167enum be_mem_enum {
@@ -170,20 +170,21 @@ enum be_mem_enum {
170 HWI_MEM_WRBH, 170 HWI_MEM_WRBH,
171 HWI_MEM_SGLH, 171 HWI_MEM_SGLH,
172 HWI_MEM_SGE, 172 HWI_MEM_SGE,
173 HWI_MEM_TEMPLATE_HDR, 173 HWI_MEM_TEMPLATE_HDR_ULP0,
174 HWI_MEM_ASYNC_HEADER_BUF_ULP0, 174 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
175 HWI_MEM_ASYNC_DATA_BUF_ULP0, 175 HWI_MEM_ASYNC_DATA_BUF_ULP0,
176 HWI_MEM_ASYNC_HEADER_RING_ULP0, 176 HWI_MEM_ASYNC_HEADER_RING_ULP0,
177 HWI_MEM_ASYNC_DATA_RING_ULP0, 177 HWI_MEM_ASYNC_DATA_RING_ULP0,
178 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0, 178 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
179 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, 179 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
180 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0, 180 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
181 HWI_MEM_ASYNC_HEADER_BUF_ULP1, 181 HWI_MEM_TEMPLATE_HDR_ULP1,
182 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
182 HWI_MEM_ASYNC_DATA_BUF_ULP1, 183 HWI_MEM_ASYNC_DATA_BUF_ULP1,
183 HWI_MEM_ASYNC_HEADER_RING_ULP1, 184 HWI_MEM_ASYNC_HEADER_RING_ULP1,
184 HWI_MEM_ASYNC_DATA_RING_ULP1, 185 HWI_MEM_ASYNC_DATA_RING_ULP1,
185 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1, 186 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
186 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, 187 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
187 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1, 188 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
188 ISCSI_MEM_GLOBAL_HEADER, 189 ISCSI_MEM_GLOBAL_HEADER,
189 SE_MEM_MAX 190 SE_MEM_MAX