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authorTejun Heo <htejun@gmail.com>2006-02-28 11:25:39 -0500
committerJeff Garzik <jeff@garzik.org>2006-03-03 15:39:54 -0500
commit1d076e5b8d91babc018ffaefafd4f85a53c9a1b1 (patch)
tree8f610a291cfd45cf041fd51d91de73e051a7d44e /drivers/scsi/ata_piix.c
parent597afd21401c85bdf9441830abf431c2be6fd45f (diff)
[PATCH] ata_piix: finer-grained port_info
Make port_info finer-grained. This patch doesn't cause any functional change. Later init reimplementation will make use of it. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/scsi/ata_piix.c')
-rw-r--r--drivers/scsi/ata_piix.c77
1 files changed, 58 insertions, 19 deletions
diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
index c662bf531514..5988d5fe1e18 100644
--- a/drivers/scsi/ata_piix.c
+++ b/drivers/scsi/ata_piix.c
@@ -119,11 +119,14 @@ enum {
119 PIIX_80C_PRI = (1 << 5) | (1 << 4), 119 PIIX_80C_PRI = (1 << 5) | (1 << 4),
120 PIIX_80C_SEC = (1 << 7) | (1 << 6), 120 PIIX_80C_SEC = (1 << 7) | (1 << 6),
121 121
122 ich5_pata = 0, 122 /* controller IDs */
123 ich5_sata = 1, 123 piix4_pata = 0,
124 piix4_pata = 2, 124 ich5_pata = 1,
125 ich6_sata = 3, 125 ich5_sata = 2,
126 ich6_sata_ahci = 4, 126 esb_sata = 3,
127 ich6_sata = 4,
128 ich6_sata_ahci = 5,
129 ich6m_sata_ahci = 6,
127 130
128 PIIX_AHCI_DEVICE = 6, 131 PIIX_AHCI_DEVICE = 6,
129}; 132};
@@ -149,19 +152,32 @@ static const struct pci_device_id piix_pci_tbl[] = {
149 * list in drivers/pci/quirks.c. 152 * list in drivers/pci/quirks.c.
150 */ 153 */
151 154
155 /* 82801EB (ICH5) */
152 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 156 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
157 /* 82801EB (ICH5) */
153 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 158 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
154 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 159 /* 6300ESB (ICH5 variant with broken PCS present bits) */
155 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 160 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
161 /* 6300ESB pretending RAID */
162 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
163 /* 82801FB/FW (ICH6/ICH6W) */
156 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 164 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
165 /* 82801FR/FRW (ICH6R/ICH6RW) */
157 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 166 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
158 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 167 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
168 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
169 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
159 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 170 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
160 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 171 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
172 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
173 /* Enterprise Southbridge 2 (where's the datasheet?) */
161 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 174 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
175 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
162 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 176 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
177 /* SATA Controller 2 IDE (ICH8, ditto) */
163 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 178 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
164 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 179 /* Mobile SATA Controller IDE (ICH8M, ditto) */
180 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
165 181
166 { } /* terminate list */ 182 { } /* terminate list */
167}; 183};
@@ -255,6 +271,20 @@ static const struct ata_port_operations piix_sata_ops = {
255}; 271};
256 272
257static struct ata_port_info piix_port_info[] = { 273static struct ata_port_info piix_port_info[] = {
274 /* piix4_pata */
275 {
276 .sht = &piix_sht,
277 .host_flags = ATA_FLAG_SLAVE_POSS,
278 .pio_mask = 0x1f, /* pio0-4 */
279#if 0
280 .mwdma_mask = 0x06, /* mwdma1-2 */
281#else
282 .mwdma_mask = 0x00, /* mwdma broken */
283#endif
284 .udma_mask = ATA_UDMA_MASK_40C,
285 .port_ops = &piix_pata_ops,
286 },
287
258 /* ich5_pata */ 288 /* ich5_pata */
259 { 289 {
260 .sht = &piix_sht, 290 .sht = &piix_sht,
@@ -280,18 +310,15 @@ static struct ata_port_info piix_port_info[] = {
280 .port_ops = &piix_sata_ops, 310 .port_ops = &piix_sata_ops,
281 }, 311 },
282 312
283 /* piix4_pata */ 313 /* i6300esb_sata */
284 { 314 {
285 .sht = &piix_sht, 315 .sht = &piix_sht,
286 .host_flags = ATA_FLAG_SLAVE_POSS, 316 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
317 PIIX_FLAG_CHECKINTR,
287 .pio_mask = 0x1f, /* pio0-4 */ 318 .pio_mask = 0x1f, /* pio0-4 */
288#if 0 319 .mwdma_mask = 0x07, /* mwdma0-2 */
289 .mwdma_mask = 0x06, /* mwdma1-2 */ 320 .udma_mask = 0x7f, /* udma0-6 */
290#else 321 .port_ops = &piix_sata_ops,
291 .mwdma_mask = 0x00, /* mwdma broken */
292#endif
293 .udma_mask = ATA_UDMA_MASK_40C,
294 .port_ops = &piix_pata_ops,
295 }, 322 },
296 323
297 /* ich6_sata */ 324 /* ich6_sata */
@@ -316,6 +343,18 @@ static struct ata_port_info piix_port_info[] = {
316 .udma_mask = 0x7f, /* udma0-6 */ 343 .udma_mask = 0x7f, /* udma0-6 */
317 .port_ops = &piix_sata_ops, 344 .port_ops = &piix_sata_ops,
318 }, 345 },
346
347 /* ich6m_sata_ahci */
348 {
349 .sht = &piix_sht,
350 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
351 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
352 PIIX_FLAG_AHCI,
353 .pio_mask = 0x1f, /* pio0-4 */
354 .mwdma_mask = 0x07, /* mwdma0-2 */
355 .udma_mask = 0x7f, /* udma0-6 */
356 .port_ops = &piix_sata_ops,
357 },
319}; 358};
320 359
321static struct pci_bits piix_enable_bits[] = { 360static struct pci_bits piix_enable_bits[] = {