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authorNick Cheng <nick.cheng@areca.com.tw>2010-07-13 08:03:04 -0400
committerJames Bottomley <James.Bottomley@suse.de>2010-07-27 13:03:49 -0400
commitcdd3cb156f190edb37d7066ddbf879354da2b634 (patch)
tree8633100619eb382a49f79c7003d59ae048368abe /drivers/scsi/arcmsr/arcmsr.h
parenta91c1be21704113b023919826c6d531da46656ef (diff)
[SCSI] SCSI: Support Type C RAID controller
1. To support Type C RAID controller, ACB_ADAPTER_TYPE_C, i.e. PCI device ID: 0x1880. Signed-off-by: Nick Cheng< nick.cheng@areca.com.tw > Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers/scsi/arcmsr/arcmsr.h')
-rw-r--r--drivers/scsi/arcmsr/arcmsr.h208
1 files changed, 173 insertions, 35 deletions
diff --git a/drivers/scsi/arcmsr/arcmsr.h b/drivers/scsi/arcmsr/arcmsr.h
index c0861c05cd49..475c31ae985c 100644
--- a/drivers/scsi/arcmsr/arcmsr.h
+++ b/drivers/scsi/arcmsr/arcmsr.h
@@ -43,12 +43,11 @@
43******************************************************************************* 43*******************************************************************************
44*/ 44*/
45#include <linux/interrupt.h> 45#include <linux/interrupt.h>
46
47struct device_attribute; 46struct device_attribute;
48/*The limit of outstanding scsi command that firmware can handle*/ 47/*The limit of outstanding scsi command that firmware can handle*/
49#define ARCMSR_MAX_OUTSTANDING_CMD 256 48#define ARCMSR_MAX_OUTSTANDING_CMD 256
50#define ARCMSR_MAX_FREECCB_NUM 320 49#define ARCMSR_MAX_FREECCB_NUM 320
51#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2009/12/09" 50#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2010/02/02"
52#define ARCMSR_SCSI_INITIATOR_ID 255 51#define ARCMSR_SCSI_INITIATOR_ID 255
53#define ARCMSR_MAX_XFER_SECTORS 512 52#define ARCMSR_MAX_XFER_SECTORS 512
54#define ARCMSR_MAX_XFER_SECTORS_B 4096 53#define ARCMSR_MAX_XFER_SECTORS_B 4096
@@ -60,7 +59,8 @@ struct device_attribute;
60#define ARCMSR_DEFAULT_SG_ENTRIES 38 59#define ARCMSR_DEFAULT_SG_ENTRIES 38
61#define ARCMSR_MAX_HBB_POSTQUEUE 264 60#define ARCMSR_MAX_HBB_POSTQUEUE 264
62#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */ 61#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
63#define ARCMSR_CDB_SG_PAGE_LENGTH 256 62#define ARCMSR_CDB_SG_PAGE_LENGTH 256
63#define SCSI_CMD_ARECA_SPECIFIC 0xE1
64#ifndef PCI_DEVICE_ID_ARECA_1880 64#ifndef PCI_DEVICE_ID_ARECA_1880
65#define PCI_DEVICE_ID_ARECA_1880 0x1880 65#define PCI_DEVICE_ID_ARECA_1880 0x1880
66 #endif 66 #endif
@@ -138,9 +138,9 @@ struct CMD_MESSAGE_FIELD
138#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 138#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
139 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 139 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
140/* ARECA IOCTL ReturnCode */ 140/* ARECA IOCTL ReturnCode */
141#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 141#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
142#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 142#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
143#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 143#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
144#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 144#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
145/* 145/*
146************************************************************* 146*************************************************************
@@ -153,13 +153,13 @@ struct SG32ENTRY
153{ 153{
154 __le32 length; 154 __le32 length;
155 __le32 address; 155 __le32 address;
156} __attribute__ ((packed)); 156}__attribute__ ((packed));
157struct SG64ENTRY 157struct SG64ENTRY
158{ 158{
159 __le32 length; 159 __le32 length;
160 __le32 address; 160 __le32 address;
161 __le32 addresshigh; 161 __le32 addresshigh;
162} __attribute__ ((packed)); 162}__attribute__ ((packed));
163/* 163/*
164******************************************************************** 164********************************************************************
165** Q Buffer of IOP Message Transfer 165** Q Buffer of IOP Message Transfer
@@ -186,9 +186,9 @@ struct FIRMWARE_INFO
186 char model[8]; /*15, 60-67*/ 186 char model[8]; /*15, 60-67*/
187 char firmware_ver[16]; /*17, 68-83*/ 187 char firmware_ver[16]; /*17, 68-83*/
188 char device_map[16]; /*21, 84-99*/ 188 char device_map[16]; /*21, 84-99*/
189 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 189 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
190 uint8_t cfgSerial[16]; /*26,104-119*/ 190 uint8_t cfgSerial[16]; /*26,104-119*/
191 uint32_t cfgPicStatus; /*30,120-123*/ 191 uint32_t cfgPicStatus; /*30,120-123*/
192}; 192};
193/* signature of set and get firmware config */ 193/* signature of set and get firmware config */
194#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 194#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
@@ -212,11 +212,15 @@ struct FIRMWARE_INFO
212#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 212#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
213#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 213#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
214#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 214#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
215#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 215#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
216#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
216/* outbound firmware ok */ 217/* outbound firmware ok */
217#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 218#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
218/* ARC-1680 Bus Reset*/ 219/* ARC-1680 Bus Reset*/
219#define ARCMSR_ARC1680_BUS_RESET 0x00000003 220#define ARCMSR_ARC1680_BUS_RESET 0x00000003
221/* ARC-1880 Bus Reset*/
222#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
223#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
220 224
221/* 225/*
222************************************************************************ 226************************************************************************
@@ -273,6 +277,61 @@ struct FIRMWARE_INFO
273#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00 277#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
274/* iop message_rwbuffer for message command */ 278/* iop message_rwbuffer for message command */
275#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00 279#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
280/*
281************************************************************************
282** SPEC. for Areca HBC adapter
283************************************************************************
284*/
285#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
286#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
287/* Host Interrupt Mask */
288#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
289#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
290#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
291#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
292/* Host Interrupt Status */
293#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
294 /*
295 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
296 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
297 */
298#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
299 /*
300 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
301 ** value. This bit clears only when Outbound Doorbell bits
302 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
303 ** Clear register clears bits in the Outbound Doorbell register.
304 */
305#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
306 /*
307 ** Set whenever the Outbound Post List Producer/Consumer
308 ** Register (FIFO) is not empty. It clears when the Outbound
309 ** Post List FIFO is empty.
310 */
311#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
312 /*
313 ** This bit indicates a SAS interrupt from a source external to
314 ** the PCIe core. This bit is not maskable.
315 */
316 /* DoorBell*/
317#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
318#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
319 /*inbound message 0 ready*/
320#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
321 /*more than 12 request completed in a time*/
322#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
323#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
324 /*outbound DATA WRITE isr door bell clear*/
325#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
326#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
327 /*outbound DATA READ isr door bell clear*/
328#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
329 /*outbound message 0 ready*/
330#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
331 /*outbound message cmd isr door bell clear*/
332#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
333 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
334#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
276/* 335/*
277******************************************************************************* 336*******************************************************************************
278** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 337** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
@@ -310,7 +369,7 @@ struct ARCMSR_CDB
310 struct SG32ENTRY sg32entry[1]; 369 struct SG32ENTRY sg32entry[1];
311 struct SG64ENTRY sg64entry[1]; 370 struct SG64ENTRY sg64entry[1];
312 } u; 371 } u;
313} __attribute__ ((packed)); 372};
314/* 373/*
315******************************************************************************* 374*******************************************************************************
316** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 375** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
@@ -356,7 +415,81 @@ struct MessageUnit_B
356 uint32_t __iomem *message_wbuffer; 415 uint32_t __iomem *message_wbuffer;
357 uint32_t __iomem *message_rbuffer; 416 uint32_t __iomem *message_rbuffer;
358}; 417};
359 418/*
419*********************************************************************
420** LSI
421*********************************************************************
422*/
423struct MessageUnit_C{
424 uint32_t message_unit_status; /*0000 0003*/
425 uint32_t slave_error_attribute; /*0004 0007*/
426 uint32_t slave_error_address; /*0008 000B*/
427 uint32_t posted_outbound_doorbell; /*000C 000F*/
428 uint32_t master_error_attribute; /*0010 0013*/
429 uint32_t master_error_address_low; /*0014 0017*/
430 uint32_t master_error_address_high; /*0018 001B*/
431 uint32_t hcb_size; /*001C 001F*/
432 uint32_t inbound_doorbell; /*0020 0023*/
433 uint32_t diagnostic_rw_data; /*0024 0027*/
434 uint32_t diagnostic_rw_address_low; /*0028 002B*/
435 uint32_t diagnostic_rw_address_high; /*002C 002F*/
436 uint32_t host_int_status; /*0030 0033*/
437 uint32_t host_int_mask; /*0034 0037*/
438 uint32_t dcr_data; /*0038 003B*/
439 uint32_t dcr_address; /*003C 003F*/
440 uint32_t inbound_queueport; /*0040 0043*/
441 uint32_t outbound_queueport; /*0044 0047*/
442 uint32_t hcb_pci_address_low; /*0048 004B*/
443 uint32_t hcb_pci_address_high; /*004C 004F*/
444 uint32_t iop_int_status; /*0050 0053*/
445 uint32_t iop_int_mask; /*0054 0057*/
446 uint32_t iop_inbound_queue_port; /*0058 005B*/
447 uint32_t iop_outbound_queue_port; /*005C 005F*/
448 uint32_t inbound_free_list_index; /*0060 0063*/
449 uint32_t inbound_post_list_index; /*0064 0067*/
450 uint32_t outbound_free_list_index; /*0068 006B*/
451 uint32_t outbound_post_list_index; /*006C 006F*/
452 uint32_t inbound_doorbell_clear; /*0070 0073*/
453 uint32_t i2o_message_unit_control; /*0074 0077*/
454 uint32_t last_used_message_source_address_low; /*0078 007B*/
455 uint32_t last_used_message_source_address_high; /*007C 007F*/
456 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
457 uint32_t message_dest_address_index; /*0090 0093*/
458 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
459 uint32_t utility_A_int_counter_timer; /*0098 009B*/
460 uint32_t outbound_doorbell; /*009C 009F*/
461 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
462 uint32_t message_source_address_index; /*00A4 00A7*/
463 uint32_t message_done_queue_index; /*00A8 00AB*/
464 uint32_t reserved0; /*00AC 00AF*/
465 uint32_t inbound_msgaddr0; /*00B0 00B3*/
466 uint32_t inbound_msgaddr1; /*00B4 00B7*/
467 uint32_t outbound_msgaddr0; /*00B8 00BB*/
468 uint32_t outbound_msgaddr1; /*00BC 00BF*/
469 uint32_t inbound_queueport_low; /*00C0 00C3*/
470 uint32_t inbound_queueport_high; /*00C4 00C7*/
471 uint32_t outbound_queueport_low; /*00C8 00CB*/
472 uint32_t outbound_queueport_high; /*00CC 00CF*/
473 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
474 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
475 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
476 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
477 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
478 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
479 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
480 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
481 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
482 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
483 uint32_t host_diagnostic; /*00F8 00FB*/
484 uint32_t write_sequence; /*00FC 00FF*/
485 uint32_t reserved1[34]; /*0100 0187*/
486 uint32_t reserved2[1950]; /*0188 1FFF*/
487 uint32_t message_wbuffer[32]; /*2000 207F*/
488 uint32_t reserved3[32]; /*2080 20FF*/
489 uint32_t message_rbuffer[32]; /*2100 217F*/
490 uint32_t reserved4[32]; /*2180 21FF*/
491 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
492};
360/* 493/*
361******************************************************************************* 494*******************************************************************************
362** Adapter Control Block 495** Adapter Control Block
@@ -374,11 +507,14 @@ struct AdapterControlBlock
374 unsigned long vir2phy_offset; 507 unsigned long vir2phy_offset;
375 /* Offset is used in making arc cdb physical to virtual calculations */ 508 /* Offset is used in making arc cdb physical to virtual calculations */
376 uint32_t outbound_int_enable; 509 uint32_t outbound_int_enable;
510 uint32_t cdb_phyaddr_hi32;
511 uint32_t reg_mu_acc_handle0;
377 spinlock_t eh_lock; 512 spinlock_t eh_lock;
378 spinlock_t ccblist_lock; 513 spinlock_t ccblist_lock;
379 union { 514 union {
380 struct MessageUnit_A __iomem * pmuA; 515 struct MessageUnit_A __iomem *pmuA;
381 struct MessageUnit_B * pmuB; 516 struct MessageUnit_B *pmuB;
517 struct MessageUnit_C __iomem *pmuC;
382 }; 518 };
383 /* message unit ATU inbound base address0 */ 519 /* message unit ATU inbound base address0 */
384 void __iomem *mem_base0; 520 void __iomem *mem_base0;
@@ -399,6 +535,8 @@ struct AdapterControlBlock
399 /* message clear rqbuffer */ 535 /* message clear rqbuffer */
400 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 536 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
401 #define ACB_F_BUS_RESET 0x0080 537 #define ACB_F_BUS_RESET 0x0080
538 #define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */
539
402 #define ACB_F_IOP_INITED 0x0100 540 #define ACB_F_IOP_INITED 0x0100
403 /* iop init */ 541 /* iop init */
404 #define ACB_F_ABORT 0x0200 542 #define ACB_F_ABORT 0x0200
@@ -441,9 +579,9 @@ struct AdapterControlBlock
441 uint32_t firm_numbers_queue; 579 uint32_t firm_numbers_queue;
442 uint32_t firm_sdram_size; 580 uint32_t firm_sdram_size;
443 uint32_t firm_hd_channels; 581 uint32_t firm_hd_channels;
444 uint32_t firm_cfg_version; 582 uint32_t firm_cfg_version;
445 char firm_model[12]; 583 char firm_model[12];
446 char firm_version[20]; 584 char firm_version[20];
447 char device_map[20]; /*21,84-99*/ 585 char device_map[20]; /*21,84-99*/
448 struct work_struct arcmsr_do_message_isr_bh; 586 struct work_struct arcmsr_do_message_isr_bh;
449 struct timer_list eternal_timer; 587 struct timer_list eternal_timer;
@@ -460,31 +598,31 @@ struct AdapterControlBlock
460** this CCB length must be 32 bytes boundary 598** this CCB length must be 32 bytes boundary
461******************************************************************************* 599*******************************************************************************
462*/ 600*/
463struct CommandControlBlock 601struct CommandControlBlock{
464{
465 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/ 602 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
466 struct list_head list; /*x32: 8byte, x64: 16byte*/ 603 struct list_head list; /*x32: 8byte, x64: 16byte*/
467 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */ 604 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
468 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/ 605 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
469 uint32_t shifted_cdb_phyaddr; /*x32: 4byte, x64: 4byte*/ 606 uint32_t cdb_phyaddr_pattern; /*x32: 4byte, x64: 4byte*/
607 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
470 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/ 608 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
471 #define CCB_FLAG_READ 0x0000 609 #define CCB_FLAG_READ 0x0000
472 #define CCB_FLAG_WRITE 0x0001 610 #define CCB_FLAG_WRITE 0x0001
473 #define CCB_FLAG_ERROR 0x0002 611 #define CCB_FLAG_ERROR 0x0002
474 #define CCB_FLAG_FLUSHCACHE 0x0004 612 #define CCB_FLAG_FLUSHCACHE 0x0004
475 #define CCB_FLAG_MASTER_ABORTED 0x0008 613 #define CCB_FLAG_MASTER_ABORTED 0x0008
476 uint16_t startdone; /*x32:2byte,x32:2byte*/ 614 uint16_t startdone; /*x32:2byte,x32:2byte*/
477 #define ARCMSR_CCB_DONE 0x0000 615 #define ARCMSR_CCB_DONE 0x0000
478 #define ARCMSR_CCB_START 0x55AA 616 #define ARCMSR_CCB_START 0x55AA
479 #define ARCMSR_CCB_ABORTED 0xAA55 617 #define ARCMSR_CCB_ABORTED 0xAA55
480 #define ARCMSR_CCB_ILLEGAL 0xFFFF 618 #define ARCMSR_CCB_ILLEGAL 0xFFFF
481 #if BITS_PER_LONG == 64 619 #if BITS_PER_LONG == 64
482 /* ======================512+64 bytes======================== */ 620 /* ======================512+64 bytes======================== */
483 uint32_t reserved[6]; /*24 byte*/ 621 uint32_t reserved[5]; /*24 byte*/
484#else 622 #else
485 /* ======================512+32 bytes======================== */ 623 /* ======================512+32 bytes======================== */
486 uint32_t reserved[2]; /*8 byte*/ 624 uint32_t reserved; /*8 byte*/
487#endif 625 #endif
488 /* ======================================================= */ 626 /* ======================================================= */
489 struct ARCMSR_CDB arcmsr_cdb; 627 struct ARCMSR_CDB arcmsr_cdb;
490}; 628};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 23:46:36 -0500