aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/scsi/arcmsr/arcmsr.h
diff options
context:
space:
mode:
authorNick Cheng <nick.cheng@areca.com.tw>2007-09-13 05:26:40 -0400
committerJames Bottomley <jejb@mulgrave.localdomain>2007-10-12 14:48:27 -0400
commit1a4f550a09f89e3a15eff1971bc9db977571b9f6 (patch)
tree3ba5dea468391701664d4ca4c0b0e2a569521d89 /drivers/scsi/arcmsr/arcmsr.h
parentbfd129445f23c037d9a440ebfa4109e11c220301 (diff)
[SCSI] arcmsr: 1.20.00.15: add SATA RAID plus other fixes
Description: ** support ARC1200/1201/1202 SATA RAID adapter, which is named ACB_ADAPTER_TYPE_B ** modify the arcmsr_pci_slot_reset function ** modify the arcmsr_pci_ers_disconnect_forepart function ** modify the arcmsr_pci_ers_need_reset_forepart function  Signed-off-by: Nick Cheng <nick.cheng@areca.com.tw> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/arcmsr/arcmsr.h')
-rw-r--r--drivers/scsi/arcmsr/arcmsr.h192
1 files changed, 142 insertions, 50 deletions
diff --git a/drivers/scsi/arcmsr/arcmsr.h b/drivers/scsi/arcmsr/arcmsr.h
index f0b8bf4534f0..ace7a15b413e 100644
--- a/drivers/scsi/arcmsr/arcmsr.h
+++ b/drivers/scsi/arcmsr/arcmsr.h
@@ -9,7 +9,7 @@
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
10** 10**
11** Web site: www.areca.com.tw 11** Web site: www.areca.com.tw
12** E-mail: erich@areca.com.tw 12** E-mail: support@areca.com.tw
13** 13**
14** This program is free software; you can redistribute it and/or modify 14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as 15** it under the terms of the GNU General Public License version 2 as
@@ -45,19 +45,26 @@
45#include <linux/interrupt.h> 45#include <linux/interrupt.h>
46 46
47struct class_device_attribute; 47struct class_device_attribute;
48 48/*The limit of outstanding scsi command that firmware can handle*/
49#define ARCMSR_MAX_OUTSTANDING_CMD 256 49#define ARCMSR_MAX_OUTSTANDING_CMD 256
50#define ARCMSR_MAX_FREECCB_NUM 288 50#define ARCMSR_MAX_FREECCB_NUM 320
51#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.14" 51#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2007/08/30"
52#define ARCMSR_SCSI_INITIATOR_ID 255 52#define ARCMSR_SCSI_INITIATOR_ID 255
53#define ARCMSR_MAX_XFER_SECTORS 512 53#define ARCMSR_MAX_XFER_SECTORS 512
54#define ARCMSR_MAX_XFER_SECTORS_B 4096 54#define ARCMSR_MAX_XFER_SECTORS_B 4096
55#define ARCMSR_MAX_TARGETID 17 55#define ARCMSR_MAX_TARGETID 17
56#define ARCMSR_MAX_TARGETLUN 8 56#define ARCMSR_MAX_TARGETLUN 8
57#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 57#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
58#define ARCMSR_MAX_QBUFFER 4096 58#define ARCMSR_MAX_QBUFFER 4096
59#define ARCMSR_MAX_SG_ENTRIES 38 59#define ARCMSR_MAX_SG_ENTRIES 38
60 60#define ARCMSR_MAX_HBB_POSTQUEUE 264
61/*
62**********************************************************************************
63**
64**********************************************************************************
65*/
66#define ARC_SUCCESS 0
67#define ARC_FAILURE 1
61/* 68/*
62******************************************************************************* 69*******************************************************************************
63** split 64bits dma addressing 70** split 64bits dma addressing
@@ -90,7 +97,7 @@ struct CMD_MESSAGE_FIELD
90 uint8_t messagedatabuffer[1032]; 97 uint8_t messagedatabuffer[1032];
91}; 98};
92/* IOP message transfer */ 99/* IOP message transfer */
93#define ARCMSR_MESSAGE_FAIL 0x0001 100#define ARCMSR_MESSAGE_FAIL 0x0001
94/* DeviceType */ 101/* DeviceType */
95#define ARECA_SATA_RAID 0x90000000 102#define ARECA_SATA_RAID 0x90000000
96/* FunctionCode */ 103/* FunctionCode */
@@ -163,27 +170,27 @@ struct QBUFFER
163}; 170};
164/* 171/*
165******************************************************************************* 172*******************************************************************************
166** FIRMWARE INFO 173** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
167******************************************************************************* 174*******************************************************************************
168*/ 175*/
169struct FIRMWARE_INFO 176struct FIRMWARE_INFO
170{ 177{
171 uint32_t signature; /*0, 00-03*/ 178 uint32_t signature; /*0, 00-03*/
172 uint32_t request_len; /*1, 04-07*/ 179 uint32_t request_len; /*1, 04-07*/
173 uint32_t numbers_queue; /*2, 08-11*/ 180 uint32_t numbers_queue; /*2, 08-11*/
174 uint32_t sdram_size; /*3, 12-15*/ 181 uint32_t sdram_size; /*3, 12-15*/
175 uint32_t ide_channels; /*4, 16-19*/ 182 uint32_t ide_channels; /*4, 16-19*/
176 char vendor[40]; /*5, 20-59*/ 183 char vendor[40]; /*5, 20-59*/
177 char model[8]; /*15, 60-67*/ 184 char model[8]; /*15, 60-67*/
178 char firmware_ver[16]; /*17, 68-83*/ 185 char firmware_ver[16]; /*17, 68-83*/
179 char device_map[16]; /*21, 84-99*/ 186 char device_map[16]; /*21, 84-99*/
180}; 187};
181/* signature of set and get firmware config */ 188/* signature of set and get firmware config */
182#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 189#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
183#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 190#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
184/* message code of inbound message register */ 191/* message code of inbound message register */
185#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 192#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
186#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 193#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
187#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 194#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
188#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 195#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
189#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 196#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
@@ -203,6 +210,60 @@ struct FIRMWARE_INFO
203#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 210#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
204/* outbound firmware ok */ 211/* outbound firmware ok */
205#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 212#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
213
214/*
215************************************************************************
216** SPEC. for Areca Type B adapter
217************************************************************************
218*/
219/* ARECA HBB COMMAND for its FIRMWARE */
220/* window of "instruction flags" from driver to iop */
221#define ARCMSR_DRV2IOP_DOORBELL 0x00020400
222#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
223/* window of "instruction flags" from iop to driver */
224#define ARCMSR_IOP2DRV_DOORBELL 0x00020408
225#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
226/* ARECA FLAG LANGUAGE */
227/* ioctl transfer */
228#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
229/* ioctl transfer */
230#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
231#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
232#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
233
234#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
235#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
236#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
237/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
238#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
239/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
240#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
241/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
242#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
243/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
244#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
245/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
246#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
247/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
248#define ARCMSR_MESSAGE_START_BGRB 0x00060008
249#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
250#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
251/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
252#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
253/* ioctl transfer */
254#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
255/* ioctl transfer */
256#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
257#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
258#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
259
260/* data tunnel buffer between user space program and its firmware */
261/* user space data to iop 128bytes */
262#define ARCMSR_IOCTL_WBUFFER 0x0000fe00
263/* iop data to user space 128bytes */
264#define ARCMSR_IOCTL_RBUFFER 0x0000ff00
265/* iop message_rwbuffer for message command */
266#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00
206/* 267/*
207******************************************************************************* 268*******************************************************************************
208** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 269** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
@@ -214,7 +275,6 @@ struct ARCMSR_CDB
214 uint8_t TargetID; 275 uint8_t TargetID;
215 uint8_t LUN; 276 uint8_t LUN;
216 uint8_t Function; 277 uint8_t Function;
217
218 uint8_t CdbLength; 278 uint8_t CdbLength;
219 uint8_t sgcount; 279 uint8_t sgcount;
220 uint8_t Flags; 280 uint8_t Flags;
@@ -224,20 +284,18 @@ struct ARCMSR_CDB
224#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 284#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
225#define ARCMSR_CDB_FLAG_HEADQ 0x08 285#define ARCMSR_CDB_FLAG_HEADQ 0x08
226#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 286#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
227 uint8_t Reserved1;
228 287
288 uint8_t Reserved1;
229 uint32_t Context; 289 uint32_t Context;
230 uint32_t DataLength; 290 uint32_t DataLength;
231
232 uint8_t Cdb[16]; 291 uint8_t Cdb[16];
233
234 uint8_t DeviceStatus; 292 uint8_t DeviceStatus;
235#define ARCMSR_DEV_CHECK_CONDITION 0x02 293#define ARCMSR_DEV_CHECK_CONDITION 0x02
236#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 294#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
237#define ARCMSR_DEV_ABORTED 0xF1 295#define ARCMSR_DEV_ABORTED 0xF1
238#define ARCMSR_DEV_INIT_FAIL 0xF2 296#define ARCMSR_DEV_INIT_FAIL 0xF2
239 uint8_t SenseData[15];
240 297
298 uint8_t SenseData[15];
241 union 299 union
242 { 300 {
243 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 301 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES];
@@ -246,10 +304,10 @@ struct ARCMSR_CDB
246}; 304};
247/* 305/*
248******************************************************************************* 306*******************************************************************************
249** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 307** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
250******************************************************************************* 308*******************************************************************************
251*/ 309*/
252struct MessageUnit 310struct MessageUnit_A
253{ 311{
254 uint32_t resrved0[4]; /*0000 000F*/ 312 uint32_t resrved0[4]; /*0000 000F*/
255 uint32_t inbound_msgaddr0; /*0010 0013*/ 313 uint32_t inbound_msgaddr0; /*0010 0013*/
@@ -274,6 +332,30 @@ struct MessageUnit
274 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 332 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
275 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 333 uint32_t reserved6[32]; /*0F80 0FFF 32*/
276}; 334};
335
336struct MessageUnit_B
337{
338 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
339 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
340 uint32_t postq_index;
341 uint32_t doneq_index;
342 uint32_t *drv2iop_doorbell_reg;
343 uint32_t *drv2iop_doorbell_mask_reg;
344 uint32_t *iop2drv_doorbell_reg;
345 uint32_t *iop2drv_doorbell_mask_reg;
346 uint32_t *msgcode_rwbuffer_reg;
347 uint32_t *ioctl_wbuffer_reg;
348 uint32_t *ioctl_rbuffer_reg;
349};
350
351struct MessageUnit
352{
353 union
354 {
355 struct MessageUnit_A pmu_A;
356 struct MessageUnit_B pmu_B;
357 } u;
358};
277/* 359/*
278******************************************************************************* 360*******************************************************************************
279** Adapter Control Block 361** Adapter Control Block
@@ -281,37 +363,45 @@ struct MessageUnit
281*/ 363*/
282struct AdapterControlBlock 364struct AdapterControlBlock
283{ 365{
366 uint32_t adapter_type; /* adapter A,B..... */
367 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
368 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
369 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */
370 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */
284 struct pci_dev * pdev; 371 struct pci_dev * pdev;
285 struct Scsi_Host * host; 372 struct Scsi_Host * host;
286 unsigned long vir2phy_offset; 373 unsigned long vir2phy_offset;
287 /* Offset is used in making arc cdb physical to virtual calculations */ 374 /* Offset is used in making arc cdb physical to virtual calculations */
288 uint32_t outbound_int_enable; 375 uint32_t outbound_int_enable;
289 376
290 struct MessageUnit __iomem * pmu; 377 struct MessageUnit * pmu;
291 /* message unit ATU inbound base address0 */ 378 /* message unit ATU inbound base address0 */
292 379
293 uint32_t acb_flags; 380 uint32_t acb_flags;
294#define ACB_F_SCSISTOPADAPTER 0x0001 381 #define ACB_F_SCSISTOPADAPTER 0x0001
295#define ACB_F_MSG_STOP_BGRB 0x0002 382 #define ACB_F_MSG_STOP_BGRB 0x0002
296 /* stop RAID background rebuild */ 383 /* stop RAID background rebuild */
297#define ACB_F_MSG_START_BGRB 0x0004 384 #define ACB_F_MSG_START_BGRB 0x0004
298 /* stop RAID background rebuild */ 385 /* stop RAID background rebuild */
299#define ACB_F_IOPDATA_OVERFLOW 0x0008 386 #define ACB_F_IOPDATA_OVERFLOW 0x0008
300 /* iop message data rqbuffer overflow */ 387 /* iop message data rqbuffer overflow */
301#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 388 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
302 /* message clear wqbuffer */ 389 /* message clear wqbuffer */
303#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 390 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
304 /* message clear rqbuffer */ 391 /* message clear rqbuffer */
305#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 392 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
306#define ACB_F_BUS_RESET 0x0080 393 #define ACB_F_BUS_RESET 0x0080
307#define ACB_F_IOP_INITED 0x0100 394 #define ACB_F_IOP_INITED 0x0100
308 /* iop init */ 395 /* iop init */
309 396
310 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 397 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
311 /* used for memory free */ 398 /* used for memory free */
312 struct list_head ccb_free_list; 399 struct list_head ccb_free_list;
313 /* head of free ccb list */ 400 /* head of free ccb list */
401
314 atomic_t ccboutstandingcount; 402 atomic_t ccboutstandingcount;
403 /*The present outstanding command number that in the IOP that
404 waiting for being handled by FW*/
315 405
316 void * dma_coherent; 406 void * dma_coherent;
317 /* dma_coherent used for memory free */ 407 /* dma_coherent used for memory free */
@@ -353,7 +443,7 @@ struct CommandControlBlock
353{ 443{
354 struct ARCMSR_CDB arcmsr_cdb; 444 struct ARCMSR_CDB arcmsr_cdb;
355 /* 445 /*
356 ** 0-503 (size of CDB=504): 446 ** 0-503 (size of CDB = 504):
357 ** arcmsr messenger scsi command descriptor size 504 bytes 447 ** arcmsr messenger scsi command descriptor size 504 bytes
358 */ 448 */
359 uint32_t cdb_shifted_phyaddr; 449 uint32_t cdb_shifted_phyaddr;
@@ -466,7 +556,9 @@ struct SENSE_DATA
466#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 556#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
467#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 557#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
468 558
469extern void arcmsr_post_Qbuffer(struct AdapterControlBlock *acb); 559extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *);
560extern void arcmsr_iop_message_read(struct AdapterControlBlock *);
561extern struct QBUFFER *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
470extern struct class_device_attribute *arcmsr_host_attrs[]; 562extern struct class_device_attribute *arcmsr_host_attrs[];
471extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *acb); 563extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
472void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 564void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);