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authorHannes Reinecke <hare@suse.de>2008-04-25 09:03:05 -0400
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2008-04-27 13:20:00 -0400
commitd10c2e4627b0dda286bcd1c77720eb5fe4a04f93 (patch)
treeb8f72d6908ab1564da3eda146644742edba156b8 /drivers/scsi/aic7xxx
parent3dbd10f3d8b00dad35d3fac95e91c066ae71d9a8 (diff)
[SCSI] aic7xxx: Update _shipped files
Update the precompiled sequencer code to match the latest aicasm changes. Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers/scsi/aic7xxx')
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg.h_shipped1145
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped1555
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_seq.h_shipped6
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped233
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped6
5 files changed, 401 insertions, 2544 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
index 2068e00d2c75..c21ceab8e913 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
@@ -48,13 +48,6 @@ ahd_reg_print_t ahd_error_print;
48#endif 48#endif
49 49
50#if AIC_DEBUG_REGISTERS 50#if AIC_DEBUG_REGISTERS
51ahd_reg_print_t ahd_clrerr_print;
52#else
53#define ahd_clrerr_print(regvalue, cur_col, wrap) \
54 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap)
55#endif
56
57#if AIC_DEBUG_REGISTERS
58ahd_reg_print_t ahd_hcntrl_print; 51ahd_reg_print_t ahd_hcntrl_print;
59#else 52#else
60#define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 53#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
@@ -167,13 +160,6 @@ ahd_reg_print_t ahd_sg_cache_shadow_print;
167#endif 160#endif
168 161
169#if AIC_DEBUG_REGISTERS 162#if AIC_DEBUG_REGISTERS
170ahd_reg_print_t ahd_arbctl_print;
171#else
172#define ahd_arbctl_print(regvalue, cur_col, wrap) \
173 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
174#endif
175
176#if AIC_DEBUG_REGISTERS
177ahd_reg_print_t ahd_sg_cache_pre_print; 163ahd_reg_print_t ahd_sg_cache_pre_print;
178#else 164#else
179#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 165#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
@@ -188,20 +174,6 @@ ahd_reg_print_t ahd_lqin_print;
188#endif 174#endif
189 175
190#if AIC_DEBUG_REGISTERS 176#if AIC_DEBUG_REGISTERS
191ahd_reg_print_t ahd_typeptr_print;
192#else
193#define ahd_typeptr_print(regvalue, cur_col, wrap) \
194 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
195#endif
196
197#if AIC_DEBUG_REGISTERS
198ahd_reg_print_t ahd_tagptr_print;
199#else
200#define ahd_tagptr_print(regvalue, cur_col, wrap) \
201 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap)
202#endif
203
204#if AIC_DEBUG_REGISTERS
205ahd_reg_print_t ahd_lunptr_print; 177ahd_reg_print_t ahd_lunptr_print;
206#else 178#else
207#define ahd_lunptr_print(regvalue, cur_col, wrap) \ 179#define ahd_lunptr_print(regvalue, cur_col, wrap) \
@@ -209,20 +181,6 @@ ahd_reg_print_t ahd_lunptr_print;
209#endif 181#endif
210 182
211#if AIC_DEBUG_REGISTERS 183#if AIC_DEBUG_REGISTERS
212ahd_reg_print_t ahd_datalenptr_print;
213#else
214#define ahd_datalenptr_print(regvalue, cur_col, wrap) \
215 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap)
216#endif
217
218#if AIC_DEBUG_REGISTERS
219ahd_reg_print_t ahd_statlenptr_print;
220#else
221#define ahd_statlenptr_print(regvalue, cur_col, wrap) \
222 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap)
223#endif
224
225#if AIC_DEBUG_REGISTERS
226ahd_reg_print_t ahd_cmdlenptr_print; 184ahd_reg_print_t ahd_cmdlenptr_print;
227#else 185#else
228#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 186#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
@@ -258,13 +216,6 @@ ahd_reg_print_t ahd_qnextptr_print;
258#endif 216#endif
259 217
260#if AIC_DEBUG_REGISTERS 218#if AIC_DEBUG_REGISTERS
261ahd_reg_print_t ahd_idptr_print;
262#else
263#define ahd_idptr_print(regvalue, cur_col, wrap) \
264 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap)
265#endif
266
267#if AIC_DEBUG_REGISTERS
268ahd_reg_print_t ahd_abrtbyteptr_print; 219ahd_reg_print_t ahd_abrtbyteptr_print;
269#else 220#else
270#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 221#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
@@ -279,27 +230,6 @@ ahd_reg_print_t ahd_abrtbitptr_print;
279#endif 230#endif
280 231
281#if AIC_DEBUG_REGISTERS 232#if AIC_DEBUG_REGISTERS
282ahd_reg_print_t ahd_maxcmdbytes_print;
283#else
284#define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \
285 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap)
286#endif
287
288#if AIC_DEBUG_REGISTERS
289ahd_reg_print_t ahd_maxcmd2rcv_print;
290#else
291#define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \
292 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap)
293#endif
294
295#if AIC_DEBUG_REGISTERS
296ahd_reg_print_t ahd_shortthresh_print;
297#else
298#define ahd_shortthresh_print(regvalue, cur_col, wrap) \
299 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahd_reg_print_t ahd_lunlen_print; 233ahd_reg_print_t ahd_lunlen_print;
304#else 234#else
305#define ahd_lunlen_print(regvalue, cur_col, wrap) \ 235#define ahd_lunlen_print(regvalue, cur_col, wrap) \
@@ -328,41 +258,6 @@ ahd_reg_print_t ahd_maxcmdcnt_print;
328#endif 258#endif
329 259
330#if AIC_DEBUG_REGISTERS 260#if AIC_DEBUG_REGISTERS
331ahd_reg_print_t ahd_lqrsvd01_print;
332#else
333#define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \
334 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap)
335#endif
336
337#if AIC_DEBUG_REGISTERS
338ahd_reg_print_t ahd_lqrsvd16_print;
339#else
340#define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \
341 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap)
342#endif
343
344#if AIC_DEBUG_REGISTERS
345ahd_reg_print_t ahd_lqrsvd17_print;
346#else
347#define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \
348 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap)
349#endif
350
351#if AIC_DEBUG_REGISTERS
352ahd_reg_print_t ahd_cmdrsvd0_print;
353#else
354#define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \
355 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap)
356#endif
357
358#if AIC_DEBUG_REGISTERS
359ahd_reg_print_t ahd_lqctl0_print;
360#else
361#define ahd_lqctl0_print(regvalue, cur_col, wrap) \
362 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap)
363#endif
364
365#if AIC_DEBUG_REGISTERS
366ahd_reg_print_t ahd_lqctl1_print; 261ahd_reg_print_t ahd_lqctl1_print;
367#else 262#else
368#define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 263#define ahd_lqctl1_print(regvalue, cur_col, wrap) \
@@ -370,13 +265,6 @@ ahd_reg_print_t ahd_lqctl1_print;
370#endif 265#endif
371 266
372#if AIC_DEBUG_REGISTERS 267#if AIC_DEBUG_REGISTERS
373ahd_reg_print_t ahd_scsbist0_print;
374#else
375#define ahd_scsbist0_print(regvalue, cur_col, wrap) \
376 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap)
377#endif
378
379#if AIC_DEBUG_REGISTERS
380ahd_reg_print_t ahd_lqctl2_print; 268ahd_reg_print_t ahd_lqctl2_print;
381#else 269#else
382#define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 270#define ahd_lqctl2_print(regvalue, cur_col, wrap) \
@@ -384,13 +272,6 @@ ahd_reg_print_t ahd_lqctl2_print;
384#endif 272#endif
385 273
386#if AIC_DEBUG_REGISTERS 274#if AIC_DEBUG_REGISTERS
387ahd_reg_print_t ahd_scsbist1_print;
388#else
389#define ahd_scsbist1_print(regvalue, cur_col, wrap) \
390 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap)
391#endif
392
393#if AIC_DEBUG_REGISTERS
394ahd_reg_print_t ahd_scsiseq0_print; 275ahd_reg_print_t ahd_scsiseq0_print;
395#else 276#else
396#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 277#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
@@ -412,20 +293,6 @@ ahd_reg_print_t ahd_sxfrctl0_print;
412#endif 293#endif
413 294
414#if AIC_DEBUG_REGISTERS 295#if AIC_DEBUG_REGISTERS
415ahd_reg_print_t ahd_dlcount_print;
416#else
417#define ahd_dlcount_print(regvalue, cur_col, wrap) \
418 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
419#endif
420
421#if AIC_DEBUG_REGISTERS
422ahd_reg_print_t ahd_businitid_print;
423#else
424#define ahd_businitid_print(regvalue, cur_col, wrap) \
425 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap)
426#endif
427
428#if AIC_DEBUG_REGISTERS
429ahd_reg_print_t ahd_sxfrctl1_print; 296ahd_reg_print_t ahd_sxfrctl1_print;
430#else 297#else
431#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 298#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
@@ -433,20 +300,6 @@ ahd_reg_print_t ahd_sxfrctl1_print;
433#endif 300#endif
434 301
435#if AIC_DEBUG_REGISTERS 302#if AIC_DEBUG_REGISTERS
436ahd_reg_print_t ahd_bustargid_print;
437#else
438#define ahd_bustargid_print(regvalue, cur_col, wrap) \
439 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap)
440#endif
441
442#if AIC_DEBUG_REGISTERS
443ahd_reg_print_t ahd_sxfrctl2_print;
444#else
445#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
446 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
447#endif
448
449#if AIC_DEBUG_REGISTERS
450ahd_reg_print_t ahd_dffstat_print; 303ahd_reg_print_t ahd_dffstat_print;
451#else 304#else
452#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 305#define ahd_dffstat_print(regvalue, cur_col, wrap) \
@@ -454,17 +307,17 @@ ahd_reg_print_t ahd_dffstat_print;
454#endif 307#endif
455 308
456#if AIC_DEBUG_REGISTERS 309#if AIC_DEBUG_REGISTERS
457ahd_reg_print_t ahd_scsisigo_print; 310ahd_reg_print_t ahd_multargid_print;
458#else 311#else
459#define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 312#define ahd_multargid_print(regvalue, cur_col, wrap) \
460 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 313 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
461#endif 314#endif
462 315
463#if AIC_DEBUG_REGISTERS 316#if AIC_DEBUG_REGISTERS
464ahd_reg_print_t ahd_multargid_print; 317ahd_reg_print_t ahd_scsisigo_print;
465#else 318#else
466#define ahd_multargid_print(regvalue, cur_col, wrap) \ 319#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
467 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 320 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
468#endif 321#endif
469 322
470#if AIC_DEBUG_REGISTERS 323#if AIC_DEBUG_REGISTERS
@@ -482,13 +335,6 @@ ahd_reg_print_t ahd_scsiphase_print;
482#endif 335#endif
483 336
484#if AIC_DEBUG_REGISTERS 337#if AIC_DEBUG_REGISTERS
485ahd_reg_print_t ahd_scsidat0_img_print;
486#else
487#define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \
488 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap)
489#endif
490
491#if AIC_DEBUG_REGISTERS
492ahd_reg_print_t ahd_scsidat_print; 338ahd_reg_print_t ahd_scsidat_print;
493#else 339#else
494#define ahd_scsidat_print(regvalue, cur_col, wrap) \ 340#define ahd_scsidat_print(regvalue, cur_col, wrap) \
@@ -531,13 +377,6 @@ ahd_reg_print_t ahd_sblkctl_print;
531#endif 377#endif
532 378
533#if AIC_DEBUG_REGISTERS 379#if AIC_DEBUG_REGISTERS
534ahd_reg_print_t ahd_clrsint0_print;
535#else
536#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
537 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
538#endif
539
540#if AIC_DEBUG_REGISTERS
541ahd_reg_print_t ahd_sstat0_print; 380ahd_reg_print_t ahd_sstat0_print;
542#else 381#else
543#define ahd_sstat0_print(regvalue, cur_col, wrap) \ 382#define ahd_sstat0_print(regvalue, cur_col, wrap) \
@@ -552,10 +391,10 @@ ahd_reg_print_t ahd_simode0_print;
552#endif 391#endif
553 392
554#if AIC_DEBUG_REGISTERS 393#if AIC_DEBUG_REGISTERS
555ahd_reg_print_t ahd_clrsint1_print; 394ahd_reg_print_t ahd_clrsint0_print;
556#else 395#else
557#define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 396#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
558 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 397 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
559#endif 398#endif
560 399
561#if AIC_DEBUG_REGISTERS 400#if AIC_DEBUG_REGISTERS
@@ -566,17 +405,17 @@ ahd_reg_print_t ahd_sstat1_print;
566#endif 405#endif
567 406
568#if AIC_DEBUG_REGISTERS 407#if AIC_DEBUG_REGISTERS
569ahd_reg_print_t ahd_sstat2_print; 408ahd_reg_print_t ahd_clrsint1_print;
570#else 409#else
571#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 410#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
572 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 411 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
573#endif 412#endif
574 413
575#if AIC_DEBUG_REGISTERS 414#if AIC_DEBUG_REGISTERS
576ahd_reg_print_t ahd_simode2_print; 415ahd_reg_print_t ahd_sstat2_print;
577#else 416#else
578#define ahd_simode2_print(regvalue, cur_col, wrap) \ 417#define ahd_sstat2_print(regvalue, cur_col, wrap) \
579 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 418 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
580#endif 419#endif
581 420
582#if AIC_DEBUG_REGISTERS 421#if AIC_DEBUG_REGISTERS
@@ -622,17 +461,17 @@ ahd_reg_print_t ahd_lqistat0_print;
622#endif 461#endif
623 462
624#if AIC_DEBUG_REGISTERS 463#if AIC_DEBUG_REGISTERS
625ahd_reg_print_t ahd_clrlqiint0_print; 464ahd_reg_print_t ahd_lqimode0_print;
626#else 465#else
627#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 466#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
628 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 467 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
629#endif 468#endif
630 469
631#if AIC_DEBUG_REGISTERS 470#if AIC_DEBUG_REGISTERS
632ahd_reg_print_t ahd_lqimode0_print; 471ahd_reg_print_t ahd_clrlqiint0_print;
633#else 472#else
634#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 473#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
635 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 474 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
636#endif 475#endif
637 476
638#if AIC_DEBUG_REGISTERS 477#if AIC_DEBUG_REGISTERS
@@ -790,13 +629,6 @@ ahd_reg_print_t ahd_seqintsrc_print;
790#endif 629#endif
791 630
792#if AIC_DEBUG_REGISTERS 631#if AIC_DEBUG_REGISTERS
793ahd_reg_print_t ahd_currscb_print;
794#else
795#define ahd_currscb_print(regvalue, cur_col, wrap) \
796 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
797#endif
798
799#if AIC_DEBUG_REGISTERS
800ahd_reg_print_t ahd_seqimode_print; 632ahd_reg_print_t ahd_seqimode_print;
801#else 633#else
802#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 634#define ahd_seqimode_print(regvalue, cur_col, wrap) \
@@ -804,24 +636,17 @@ ahd_reg_print_t ahd_seqimode_print;
804#endif 636#endif
805 637
806#if AIC_DEBUG_REGISTERS 638#if AIC_DEBUG_REGISTERS
807ahd_reg_print_t ahd_mdffstat_print; 639ahd_reg_print_t ahd_currscb_print;
808#else
809#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
810 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
811#endif
812
813#if AIC_DEBUG_REGISTERS
814ahd_reg_print_t ahd_crccontrol_print;
815#else 640#else
816#define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 641#define ahd_currscb_print(regvalue, cur_col, wrap) \
817 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 642 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
818#endif 643#endif
819 644
820#if AIC_DEBUG_REGISTERS 645#if AIC_DEBUG_REGISTERS
821ahd_reg_print_t ahd_dfftag_print; 646ahd_reg_print_t ahd_mdffstat_print;
822#else 647#else
823#define ahd_dfftag_print(regvalue, cur_col, wrap) \ 648#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
824 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 649 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
825#endif 650#endif
826 651
827#if AIC_DEBUG_REGISTERS 652#if AIC_DEBUG_REGISTERS
@@ -832,20 +657,6 @@ ahd_reg_print_t ahd_lastscb_print;
832#endif 657#endif
833 658
834#if AIC_DEBUG_REGISTERS 659#if AIC_DEBUG_REGISTERS
835ahd_reg_print_t ahd_scsitest_print;
836#else
837#define ahd_scsitest_print(regvalue, cur_col, wrap) \
838 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap)
839#endif
840
841#if AIC_DEBUG_REGISTERS
842ahd_reg_print_t ahd_iopdnctl_print;
843#else
844#define ahd_iopdnctl_print(regvalue, cur_col, wrap) \
845 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap)
846#endif
847
848#if AIC_DEBUG_REGISTERS
849ahd_reg_print_t ahd_shaddr_print; 660ahd_reg_print_t ahd_shaddr_print;
850#else 661#else
851#define ahd_shaddr_print(regvalue, cur_col, wrap) \ 662#define ahd_shaddr_print(regvalue, cur_col, wrap) \
@@ -860,13 +671,6 @@ ahd_reg_print_t ahd_negoaddr_print;
860#endif 671#endif
861 672
862#if AIC_DEBUG_REGISTERS 673#if AIC_DEBUG_REGISTERS
863ahd_reg_print_t ahd_dgrpcrci_print;
864#else
865#define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \
866 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap)
867#endif
868
869#if AIC_DEBUG_REGISTERS
870ahd_reg_print_t ahd_negperiod_print; 674ahd_reg_print_t ahd_negperiod_print;
871#else 675#else
872#define ahd_negperiod_print(regvalue, cur_col, wrap) \ 676#define ahd_negperiod_print(regvalue, cur_col, wrap) \
@@ -874,13 +678,6 @@ ahd_reg_print_t ahd_negperiod_print;
874#endif 678#endif
875 679
876#if AIC_DEBUG_REGISTERS 680#if AIC_DEBUG_REGISTERS
877ahd_reg_print_t ahd_packcrci_print;
878#else
879#define ahd_packcrci_print(regvalue, cur_col, wrap) \
880 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap)
881#endif
882
883#if AIC_DEBUG_REGISTERS
884ahd_reg_print_t ahd_negoffset_print; 681ahd_reg_print_t ahd_negoffset_print;
885#else 682#else
886#define ahd_negoffset_print(regvalue, cur_col, wrap) \ 683#define ahd_negoffset_print(regvalue, cur_col, wrap) \
@@ -930,13 +727,6 @@ ahd_reg_print_t ahd_iownid_print;
930#endif 727#endif
931 728
932#if AIC_DEBUG_REGISTERS 729#if AIC_DEBUG_REGISTERS
933ahd_reg_print_t ahd_pll960ctl0_print;
934#else
935#define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \
936 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahd_reg_print_t ahd_shcnt_print; 730ahd_reg_print_t ahd_shcnt_print;
941#else 731#else
942#define ahd_shcnt_print(regvalue, cur_col, wrap) \ 732#define ahd_shcnt_print(regvalue, cur_col, wrap) \
@@ -951,27 +741,6 @@ ahd_reg_print_t ahd_townid_print;
951#endif 741#endif
952 742
953#if AIC_DEBUG_REGISTERS 743#if AIC_DEBUG_REGISTERS
954ahd_reg_print_t ahd_pll960ctl1_print;
955#else
956#define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \
957 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap)
958#endif
959
960#if AIC_DEBUG_REGISTERS
961ahd_reg_print_t ahd_pll960cnt0_print;
962#else
963#define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \
964 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap)
965#endif
966
967#if AIC_DEBUG_REGISTERS
968ahd_reg_print_t ahd_xsig_print;
969#else
970#define ahd_xsig_print(regvalue, cur_col, wrap) \
971 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap)
972#endif
973
974#if AIC_DEBUG_REGISTERS
975ahd_reg_print_t ahd_seloid_print; 744ahd_reg_print_t ahd_seloid_print;
976#else 745#else
977#define ahd_seloid_print(regvalue, cur_col, wrap) \ 746#define ahd_seloid_print(regvalue, cur_col, wrap) \
@@ -979,41 +748,6 @@ ahd_reg_print_t ahd_seloid_print;
979#endif 748#endif
980 749
981#if AIC_DEBUG_REGISTERS 750#if AIC_DEBUG_REGISTERS
982ahd_reg_print_t ahd_pll400ctl0_print;
983#else
984#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
985 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
986#endif
987
988#if AIC_DEBUG_REGISTERS
989ahd_reg_print_t ahd_fairness_print;
990#else
991#define ahd_fairness_print(regvalue, cur_col, wrap) \
992 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
993#endif
994
995#if AIC_DEBUG_REGISTERS
996ahd_reg_print_t ahd_pll400ctl1_print;
997#else
998#define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \
999 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap)
1000#endif
1001
1002#if AIC_DEBUG_REGISTERS
1003ahd_reg_print_t ahd_unfairness_print;
1004#else
1005#define ahd_unfairness_print(regvalue, cur_col, wrap) \
1006 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahd_reg_print_t ahd_pll400cnt0_print;
1011#else
1012#define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \
1013 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap)
1014#endif
1015
1016#if AIC_DEBUG_REGISTERS
1017ahd_reg_print_t ahd_haddr_print; 751ahd_reg_print_t ahd_haddr_print;
1018#else 752#else
1019#define ahd_haddr_print(regvalue, cur_col, wrap) \ 753#define ahd_haddr_print(regvalue, cur_col, wrap) \
@@ -1021,27 +755,6 @@ ahd_reg_print_t ahd_haddr_print;
1021#endif 755#endif
1022 756
1023#if AIC_DEBUG_REGISTERS 757#if AIC_DEBUG_REGISTERS
1024ahd_reg_print_t ahd_plldelay_print;
1025#else
1026#define ahd_plldelay_print(regvalue, cur_col, wrap) \
1027 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap)
1028#endif
1029
1030#if AIC_DEBUG_REGISTERS
1031ahd_reg_print_t ahd_hodmaadr_print;
1032#else
1033#define ahd_hodmaadr_print(regvalue, cur_col, wrap) \
1034 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahd_reg_print_t ahd_hodmacnt_print;
1039#else
1040#define ahd_hodmacnt_print(regvalue, cur_col, wrap) \
1041 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahd_reg_print_t ahd_hcnt_print; 758ahd_reg_print_t ahd_hcnt_print;
1046#else 759#else
1047#define ahd_hcnt_print(regvalue, cur_col, wrap) \ 760#define ahd_hcnt_print(regvalue, cur_col, wrap) \
@@ -1049,10 +762,10 @@ ahd_reg_print_t ahd_hcnt_print;
1049#endif 762#endif
1050 763
1051#if AIC_DEBUG_REGISTERS 764#if AIC_DEBUG_REGISTERS
1052ahd_reg_print_t ahd_hodmaen_print; 765ahd_reg_print_t ahd_sghaddr_print;
1053#else 766#else
1054#define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 767#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
1055 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 768 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
1056#endif 769#endif
1057 770
1058#if AIC_DEBUG_REGISTERS 771#if AIC_DEBUG_REGISTERS
@@ -1063,10 +776,10 @@ ahd_reg_print_t ahd_scbhaddr_print;
1063#endif 776#endif
1064 777
1065#if AIC_DEBUG_REGISTERS 778#if AIC_DEBUG_REGISTERS
1066ahd_reg_print_t ahd_sghaddr_print; 779ahd_reg_print_t ahd_sghcnt_print;
1067#else 780#else
1068#define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 781#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1069 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 782 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1070#endif 783#endif
1071 784
1072#if AIC_DEBUG_REGISTERS 785#if AIC_DEBUG_REGISTERS
@@ -1077,13 +790,6 @@ ahd_reg_print_t ahd_scbhcnt_print;
1077#endif 790#endif
1078 791
1079#if AIC_DEBUG_REGISTERS 792#if AIC_DEBUG_REGISTERS
1080ahd_reg_print_t ahd_sghcnt_print;
1081#else
1082#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1083 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1084#endif
1085
1086#if AIC_DEBUG_REGISTERS
1087ahd_reg_print_t ahd_dff_thrsh_print; 793ahd_reg_print_t ahd_dff_thrsh_print;
1088#else 794#else
1089#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 795#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
@@ -1091,132 +797,6 @@ ahd_reg_print_t ahd_dff_thrsh_print;
1091#endif 797#endif
1092 798
1093#if AIC_DEBUG_REGISTERS 799#if AIC_DEBUG_REGISTERS
1094ahd_reg_print_t ahd_romaddr_print;
1095#else
1096#define ahd_romaddr_print(regvalue, cur_col, wrap) \
1097 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap)
1098#endif
1099
1100#if AIC_DEBUG_REGISTERS
1101ahd_reg_print_t ahd_romcntrl_print;
1102#else
1103#define ahd_romcntrl_print(regvalue, cur_col, wrap) \
1104 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap)
1105#endif
1106
1107#if AIC_DEBUG_REGISTERS
1108ahd_reg_print_t ahd_romdata_print;
1109#else
1110#define ahd_romdata_print(regvalue, cur_col, wrap) \
1111 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap)
1112#endif
1113
1114#if AIC_DEBUG_REGISTERS
1115ahd_reg_print_t ahd_cmcrxmsg0_print;
1116#else
1117#define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \
1118 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap)
1119#endif
1120
1121#if AIC_DEBUG_REGISTERS
1122ahd_reg_print_t ahd_roenable_print;
1123#else
1124#define ahd_roenable_print(regvalue, cur_col, wrap) \
1125 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
1126#endif
1127
1128#if AIC_DEBUG_REGISTERS
1129ahd_reg_print_t ahd_ovlyrxmsg0_print;
1130#else
1131#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
1132 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap)
1133#endif
1134
1135#if AIC_DEBUG_REGISTERS
1136ahd_reg_print_t ahd_dchrxmsg0_print;
1137#else
1138#define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \
1139 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap)
1140#endif
1141
1142#if AIC_DEBUG_REGISTERS
1143ahd_reg_print_t ahd_ovlyrxmsg1_print;
1144#else
1145#define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \
1146 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap)
1147#endif
1148
1149#if AIC_DEBUG_REGISTERS
1150ahd_reg_print_t ahd_nsenable_print;
1151#else
1152#define ahd_nsenable_print(regvalue, cur_col, wrap) \
1153 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
1154#endif
1155
1156#if AIC_DEBUG_REGISTERS
1157ahd_reg_print_t ahd_cmcrxmsg1_print;
1158#else
1159#define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \
1160 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap)
1161#endif
1162
1163#if AIC_DEBUG_REGISTERS
1164ahd_reg_print_t ahd_dchrxmsg1_print;
1165#else
1166#define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \
1167 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap)
1168#endif
1169
1170#if AIC_DEBUG_REGISTERS
1171ahd_reg_print_t ahd_dchrxmsg2_print;
1172#else
1173#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
1174 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap)
1175#endif
1176
1177#if AIC_DEBUG_REGISTERS
1178ahd_reg_print_t ahd_cmcrxmsg2_print;
1179#else
1180#define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \
1181 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap)
1182#endif
1183
1184#if AIC_DEBUG_REGISTERS
1185ahd_reg_print_t ahd_ost_print;
1186#else
1187#define ahd_ost_print(regvalue, cur_col, wrap) \
1188 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap)
1189#endif
1190
1191#if AIC_DEBUG_REGISTERS
1192ahd_reg_print_t ahd_ovlyrxmsg2_print;
1193#else
1194#define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \
1195 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap)
1196#endif
1197
1198#if AIC_DEBUG_REGISTERS
1199ahd_reg_print_t ahd_dchrxmsg3_print;
1200#else
1201#define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \
1202 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap)
1203#endif
1204
1205#if AIC_DEBUG_REGISTERS
1206ahd_reg_print_t ahd_ovlyrxmsg3_print;
1207#else
1208#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
1209 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
1210#endif
1211
1212#if AIC_DEBUG_REGISTERS
1213ahd_reg_print_t ahd_cmcrxmsg3_print;
1214#else
1215#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
1216 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap)
1217#endif
1218
1219#if AIC_DEBUG_REGISTERS
1220ahd_reg_print_t ahd_pcixctl_print; 800ahd_reg_print_t ahd_pcixctl_print;
1221#else 801#else
1222#define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 802#define ahd_pcixctl_print(regvalue, cur_col, wrap) \
@@ -1224,34 +804,6 @@ ahd_reg_print_t ahd_pcixctl_print;
1224#endif 804#endif
1225 805
1226#if AIC_DEBUG_REGISTERS 806#if AIC_DEBUG_REGISTERS
1227ahd_reg_print_t ahd_ovlyseqbcnt_print;
1228#else
1229#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
1230 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap)
1231#endif
1232
1233#if AIC_DEBUG_REGISTERS
1234ahd_reg_print_t ahd_dchseqbcnt_print;
1235#else
1236#define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \
1237 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap)
1238#endif
1239
1240#if AIC_DEBUG_REGISTERS
1241ahd_reg_print_t ahd_cmcseqbcnt_print;
1242#else
1243#define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \
1244 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap)
1245#endif
1246
1247#if AIC_DEBUG_REGISTERS
1248ahd_reg_print_t ahd_cmcspltstat0_print;
1249#else
1250#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
1251 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1252#endif
1253
1254#if AIC_DEBUG_REGISTERS
1255ahd_reg_print_t ahd_dchspltstat0_print; 807ahd_reg_print_t ahd_dchspltstat0_print;
1256#else 808#else
1257#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 809#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
@@ -1259,27 +811,6 @@ ahd_reg_print_t ahd_dchspltstat0_print;
1259#endif 811#endif
1260 812
1261#if AIC_DEBUG_REGISTERS 813#if AIC_DEBUG_REGISTERS
1262ahd_reg_print_t ahd_ovlyspltstat0_print;
1263#else
1264#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
1265 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1266#endif
1267
1268#if AIC_DEBUG_REGISTERS
1269ahd_reg_print_t ahd_cmcspltstat1_print;
1270#else
1271#define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \
1272 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1273#endif
1274
1275#if AIC_DEBUG_REGISTERS
1276ahd_reg_print_t ahd_ovlyspltstat1_print;
1277#else
1278#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
1279 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1280#endif
1281
1282#if AIC_DEBUG_REGISTERS
1283ahd_reg_print_t ahd_dchspltstat1_print; 814ahd_reg_print_t ahd_dchspltstat1_print;
1284#else 815#else
1285#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 816#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
@@ -1287,90 +818,6 @@ ahd_reg_print_t ahd_dchspltstat1_print;
1287#endif 818#endif
1288 819
1289#if AIC_DEBUG_REGISTERS 820#if AIC_DEBUG_REGISTERS
1290ahd_reg_print_t ahd_sgrxmsg0_print;
1291#else
1292#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
1293 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap)
1294#endif
1295
1296#if AIC_DEBUG_REGISTERS
1297ahd_reg_print_t ahd_slvspltoutadr0_print;
1298#else
1299#define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \
1300 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap)
1301#endif
1302
1303#if AIC_DEBUG_REGISTERS
1304ahd_reg_print_t ahd_sgrxmsg1_print;
1305#else
1306#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
1307 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap)
1308#endif
1309
1310#if AIC_DEBUG_REGISTERS
1311ahd_reg_print_t ahd_slvspltoutadr1_print;
1312#else
1313#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
1314 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
1315#endif
1316
1317#if AIC_DEBUG_REGISTERS
1318ahd_reg_print_t ahd_sgrxmsg2_print;
1319#else
1320#define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \
1321 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap)
1322#endif
1323
1324#if AIC_DEBUG_REGISTERS
1325ahd_reg_print_t ahd_slvspltoutadr2_print;
1326#else
1327#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
1328 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
1329#endif
1330
1331#if AIC_DEBUG_REGISTERS
1332ahd_reg_print_t ahd_sgrxmsg3_print;
1333#else
1334#define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \
1335 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap)
1336#endif
1337
1338#if AIC_DEBUG_REGISTERS
1339ahd_reg_print_t ahd_slvspltoutadr3_print;
1340#else
1341#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
1342 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap)
1343#endif
1344
1345#if AIC_DEBUG_REGISTERS
1346ahd_reg_print_t ahd_sgseqbcnt_print;
1347#else
1348#define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \
1349 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap)
1350#endif
1351
1352#if AIC_DEBUG_REGISTERS
1353ahd_reg_print_t ahd_slvspltoutattr0_print;
1354#else
1355#define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \
1356 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap)
1357#endif
1358
1359#if AIC_DEBUG_REGISTERS
1360ahd_reg_print_t ahd_slvspltoutattr1_print;
1361#else
1362#define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \
1363 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap)
1364#endif
1365
1366#if AIC_DEBUG_REGISTERS
1367ahd_reg_print_t ahd_slvspltoutattr2_print;
1368#else
1369#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
1370 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
1371#endif
1372
1373#if AIC_DEBUG_REGISTERS
1374ahd_reg_print_t ahd_sgspltstat0_print; 821ahd_reg_print_t ahd_sgspltstat0_print;
1375#else 822#else
1376#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 823#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
@@ -1385,13 +832,6 @@ ahd_reg_print_t ahd_sgspltstat1_print;
1385#endif 832#endif
1386 833
1387#if AIC_DEBUG_REGISTERS 834#if AIC_DEBUG_REGISTERS
1388ahd_reg_print_t ahd_sfunct_print;
1389#else
1390#define ahd_sfunct_print(regvalue, cur_col, wrap) \
1391 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
1392#endif
1393
1394#if AIC_DEBUG_REGISTERS
1395ahd_reg_print_t ahd_df0pcistat_print; 835ahd_reg_print_t ahd_df0pcistat_print;
1396#else 836#else
1397#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 837#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
@@ -1406,41 +846,6 @@ ahd_reg_print_t ahd_reg0_print;
1406#endif 846#endif
1407 847
1408#if AIC_DEBUG_REGISTERS 848#if AIC_DEBUG_REGISTERS
1409ahd_reg_print_t ahd_df1pcistat_print;
1410#else
1411#define ahd_df1pcistat_print(regvalue, cur_col, wrap) \
1412 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap)
1413#endif
1414
1415#if AIC_DEBUG_REGISTERS
1416ahd_reg_print_t ahd_sgpcistat_print;
1417#else
1418#define ahd_sgpcistat_print(regvalue, cur_col, wrap) \
1419 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap)
1420#endif
1421
1422#if AIC_DEBUG_REGISTERS
1423ahd_reg_print_t ahd_reg1_print;
1424#else
1425#define ahd_reg1_print(regvalue, cur_col, wrap) \
1426 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap)
1427#endif
1428
1429#if AIC_DEBUG_REGISTERS
1430ahd_reg_print_t ahd_cmcpcistat_print;
1431#else
1432#define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \
1433 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap)
1434#endif
1435
1436#if AIC_DEBUG_REGISTERS
1437ahd_reg_print_t ahd_ovlypcistat_print;
1438#else
1439#define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \
1440 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap)
1441#endif
1442
1443#if AIC_DEBUG_REGISTERS
1444ahd_reg_print_t ahd_reg_isr_print; 849ahd_reg_print_t ahd_reg_isr_print;
1445#else 850#else
1446#define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 851#define ahd_reg_isr_print(regvalue, cur_col, wrap) \
@@ -1455,13 +860,6 @@ ahd_reg_print_t ahd_sg_state_print;
1455#endif 860#endif
1456 861
1457#if AIC_DEBUG_REGISTERS 862#if AIC_DEBUG_REGISTERS
1458ahd_reg_print_t ahd_msipcistat_print;
1459#else
1460#define ahd_msipcistat_print(regvalue, cur_col, wrap) \
1461 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap)
1462#endif
1463
1464#if AIC_DEBUG_REGISTERS
1465ahd_reg_print_t ahd_targpcistat_print; 863ahd_reg_print_t ahd_targpcistat_print;
1466#else 864#else
1467#define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 865#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
@@ -1469,13 +867,6 @@ ahd_reg_print_t ahd_targpcistat_print;
1469#endif 867#endif
1470 868
1471#if AIC_DEBUG_REGISTERS 869#if AIC_DEBUG_REGISTERS
1472ahd_reg_print_t ahd_data_count_odd_print;
1473#else
1474#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
1475 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
1476#endif
1477
1478#if AIC_DEBUG_REGISTERS
1479ahd_reg_print_t ahd_scbptr_print; 870ahd_reg_print_t ahd_scbptr_print;
1480#else 871#else
1481#define ahd_scbptr_print(regvalue, cur_col, wrap) \ 872#define ahd_scbptr_print(regvalue, cur_col, wrap) \
@@ -1483,13 +874,6 @@ ahd_reg_print_t ahd_scbptr_print;
1483#endif 874#endif
1484 875
1485#if AIC_DEBUG_REGISTERS 876#if AIC_DEBUG_REGISTERS
1486ahd_reg_print_t ahd_ccscbacnt_print;
1487#else
1488#define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \
1489 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap)
1490#endif
1491
1492#if AIC_DEBUG_REGISTERS
1493ahd_reg_print_t ahd_scbautoptr_print; 877ahd_reg_print_t ahd_scbautoptr_print;
1494#else 878#else
1495#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 879#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
@@ -1504,13 +888,6 @@ ahd_reg_print_t ahd_ccsgaddr_print;
1504#endif 888#endif
1505 889
1506#if AIC_DEBUG_REGISTERS 890#if AIC_DEBUG_REGISTERS
1507ahd_reg_print_t ahd_ccscbadr_bk_print;
1508#else
1509#define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \
1510 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap)
1511#endif
1512
1513#if AIC_DEBUG_REGISTERS
1514ahd_reg_print_t ahd_ccscbaddr_print; 891ahd_reg_print_t ahd_ccscbaddr_print;
1515#else 892#else
1516#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 893#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
@@ -1518,13 +895,6 @@ ahd_reg_print_t ahd_ccscbaddr_print;
1518#endif 895#endif
1519 896
1520#if AIC_DEBUG_REGISTERS 897#if AIC_DEBUG_REGISTERS
1521ahd_reg_print_t ahd_cmc_rambist_print;
1522#else
1523#define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \
1524 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap)
1525#endif
1526
1527#if AIC_DEBUG_REGISTERS
1528ahd_reg_print_t ahd_ccscbctl_print; 898ahd_reg_print_t ahd_ccscbctl_print;
1529#else 899#else
1530#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 900#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
@@ -1546,13 +916,6 @@ ahd_reg_print_t ahd_ccsgram_print;
1546#endif 916#endif
1547 917
1548#if AIC_DEBUG_REGISTERS 918#if AIC_DEBUG_REGISTERS
1549ahd_reg_print_t ahd_flexadr_print;
1550#else
1551#define ahd_flexadr_print(regvalue, cur_col, wrap) \
1552 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap)
1553#endif
1554
1555#if AIC_DEBUG_REGISTERS
1556ahd_reg_print_t ahd_ccscbram_print; 919ahd_reg_print_t ahd_ccscbram_print;
1557#else 920#else
1558#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 921#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
@@ -1560,27 +923,6 @@ ahd_reg_print_t ahd_ccscbram_print;
1560#endif 923#endif
1561 924
1562#if AIC_DEBUG_REGISTERS 925#if AIC_DEBUG_REGISTERS
1563ahd_reg_print_t ahd_flexcnt_print;
1564#else
1565#define ahd_flexcnt_print(regvalue, cur_col, wrap) \
1566 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap)
1567#endif
1568
1569#if AIC_DEBUG_REGISTERS
1570ahd_reg_print_t ahd_flexdmastat_print;
1571#else
1572#define ahd_flexdmastat_print(regvalue, cur_col, wrap) \
1573 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap)
1574#endif
1575
1576#if AIC_DEBUG_REGISTERS
1577ahd_reg_print_t ahd_flexdata_print;
1578#else
1579#define ahd_flexdata_print(regvalue, cur_col, wrap) \
1580 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap)
1581#endif
1582
1583#if AIC_DEBUG_REGISTERS
1584ahd_reg_print_t ahd_brddat_print; 926ahd_reg_print_t ahd_brddat_print;
1585#else 927#else
1586#define ahd_brddat_print(regvalue, cur_col, wrap) \ 928#define ahd_brddat_print(regvalue, cur_col, wrap) \
@@ -1623,27 +965,6 @@ ahd_reg_print_t ahd_seestat_print;
1623#endif 965#endif
1624 966
1625#if AIC_DEBUG_REGISTERS 967#if AIC_DEBUG_REGISTERS
1626ahd_reg_print_t ahd_scbcnt_print;
1627#else
1628#define ahd_scbcnt_print(regvalue, cur_col, wrap) \
1629 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap)
1630#endif
1631
1632#if AIC_DEBUG_REGISTERS
1633ahd_reg_print_t ahd_dfwaddr_print;
1634#else
1635#define ahd_dfwaddr_print(regvalue, cur_col, wrap) \
1636 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap)
1637#endif
1638
1639#if AIC_DEBUG_REGISTERS
1640ahd_reg_print_t ahd_dspfltrctl_print;
1641#else
1642#define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \
1643 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap)
1644#endif
1645
1646#if AIC_DEBUG_REGISTERS
1647ahd_reg_print_t ahd_dspdatactl_print; 968ahd_reg_print_t ahd_dspdatactl_print;
1648#else 969#else
1649#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 970#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
@@ -1651,27 +972,6 @@ ahd_reg_print_t ahd_dspdatactl_print;
1651#endif 972#endif
1652 973
1653#if AIC_DEBUG_REGISTERS 974#if AIC_DEBUG_REGISTERS
1654ahd_reg_print_t ahd_dfraddr_print;
1655#else
1656#define ahd_dfraddr_print(regvalue, cur_col, wrap) \
1657 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap)
1658#endif
1659
1660#if AIC_DEBUG_REGISTERS
1661ahd_reg_print_t ahd_dspreqctl_print;
1662#else
1663#define ahd_dspreqctl_print(regvalue, cur_col, wrap) \
1664 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap)
1665#endif
1666
1667#if AIC_DEBUG_REGISTERS
1668ahd_reg_print_t ahd_dspackctl_print;
1669#else
1670#define ahd_dspackctl_print(regvalue, cur_col, wrap) \
1671 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap)
1672#endif
1673
1674#if AIC_DEBUG_REGISTERS
1675ahd_reg_print_t ahd_dfdat_print; 975ahd_reg_print_t ahd_dfdat_print;
1676#else 976#else
1677#define ahd_dfdat_print(regvalue, cur_col, wrap) \ 977#define ahd_dfdat_print(regvalue, cur_col, wrap) \
@@ -1693,76 +993,6 @@ ahd_reg_print_t ahd_wrtbiasctl_print;
1693#endif 993#endif
1694 994
1695#if AIC_DEBUG_REGISTERS 995#if AIC_DEBUG_REGISTERS
1696ahd_reg_print_t ahd_rcvrbiosctl_print;
1697#else
1698#define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \
1699 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap)
1700#endif
1701
1702#if AIC_DEBUG_REGISTERS
1703ahd_reg_print_t ahd_wrtbiascalc_print;
1704#else
1705#define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \
1706 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap)
1707#endif
1708
1709#if AIC_DEBUG_REGISTERS
1710ahd_reg_print_t ahd_rcvrbiascalc_print;
1711#else
1712#define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \
1713 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap)
1714#endif
1715
1716#if AIC_DEBUG_REGISTERS
1717ahd_reg_print_t ahd_dfptrs_print;
1718#else
1719#define ahd_dfptrs_print(regvalue, cur_col, wrap) \
1720 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap)
1721#endif
1722
1723#if AIC_DEBUG_REGISTERS
1724ahd_reg_print_t ahd_skewcalc_print;
1725#else
1726#define ahd_skewcalc_print(regvalue, cur_col, wrap) \
1727 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap)
1728#endif
1729
1730#if AIC_DEBUG_REGISTERS
1731ahd_reg_print_t ahd_dfbkptr_print;
1732#else
1733#define ahd_dfbkptr_print(regvalue, cur_col, wrap) \
1734 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap)
1735#endif
1736
1737#if AIC_DEBUG_REGISTERS
1738ahd_reg_print_t ahd_dfdbctl_print;
1739#else
1740#define ahd_dfdbctl_print(regvalue, cur_col, wrap) \
1741 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap)
1742#endif
1743
1744#if AIC_DEBUG_REGISTERS
1745ahd_reg_print_t ahd_dfscnt_print;
1746#else
1747#define ahd_dfscnt_print(regvalue, cur_col, wrap) \
1748 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap)
1749#endif
1750
1751#if AIC_DEBUG_REGISTERS
1752ahd_reg_print_t ahd_dfbcnt_print;
1753#else
1754#define ahd_dfbcnt_print(regvalue, cur_col, wrap) \
1755 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap)
1756#endif
1757
1758#if AIC_DEBUG_REGISTERS
1759ahd_reg_print_t ahd_ovlyaddr_print;
1760#else
1761#define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \
1762 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap)
1763#endif
1764
1765#if AIC_DEBUG_REGISTERS
1766ahd_reg_print_t ahd_seqctl0_print; 996ahd_reg_print_t ahd_seqctl0_print;
1767#else 997#else
1768#define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 998#define ahd_seqctl0_print(regvalue, cur_col, wrap) \
@@ -1770,13 +1000,6 @@ ahd_reg_print_t ahd_seqctl0_print;
1770#endif 1000#endif
1771 1001
1772#if AIC_DEBUG_REGISTERS 1002#if AIC_DEBUG_REGISTERS
1773ahd_reg_print_t ahd_seqctl1_print;
1774#else
1775#define ahd_seqctl1_print(regvalue, cur_col, wrap) \
1776 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap)
1777#endif
1778
1779#if AIC_DEBUG_REGISTERS
1780ahd_reg_print_t ahd_flags_print; 1003ahd_reg_print_t ahd_flags_print;
1781#else 1004#else
1782#define ahd_flags_print(regvalue, cur_col, wrap) \ 1005#define ahd_flags_print(regvalue, cur_col, wrap) \
@@ -1826,20 +1049,6 @@ ahd_reg_print_t ahd_dindex_print;
1826#endif 1049#endif
1827 1050
1828#if AIC_DEBUG_REGISTERS 1051#if AIC_DEBUG_REGISTERS
1829ahd_reg_print_t ahd_brkaddr0_print;
1830#else
1831#define ahd_brkaddr0_print(regvalue, cur_col, wrap) \
1832 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap)
1833#endif
1834
1835#if AIC_DEBUG_REGISTERS
1836ahd_reg_print_t ahd_brkaddr1_print;
1837#else
1838#define ahd_brkaddr1_print(regvalue, cur_col, wrap) \
1839 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap)
1840#endif
1841
1842#if AIC_DEBUG_REGISTERS
1843ahd_reg_print_t ahd_allones_print; 1052ahd_reg_print_t ahd_allones_print;
1844#else 1053#else
1845#define ahd_allones_print(regvalue, cur_col, wrap) \ 1054#define ahd_allones_print(regvalue, cur_col, wrap) \
@@ -1875,13 +1084,6 @@ ahd_reg_print_t ahd_dindir_print;
1875#endif 1084#endif
1876 1085
1877#if AIC_DEBUG_REGISTERS 1086#if AIC_DEBUG_REGISTERS
1878ahd_reg_print_t ahd_function1_print;
1879#else
1880#define ahd_function1_print(regvalue, cur_col, wrap) \
1881 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap)
1882#endif
1883
1884#if AIC_DEBUG_REGISTERS
1885ahd_reg_print_t ahd_stack_print; 1087ahd_reg_print_t ahd_stack_print;
1886#else 1088#else
1887#define ahd_stack_print(regvalue, cur_col, wrap) \ 1089#define ahd_stack_print(regvalue, cur_col, wrap) \
@@ -1903,13 +1105,6 @@ ahd_reg_print_t ahd_curaddr_print;
1903#endif 1105#endif
1904 1106
1905#if AIC_DEBUG_REGISTERS 1107#if AIC_DEBUG_REGISTERS
1906ahd_reg_print_t ahd_lastaddr_print;
1907#else
1908#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
1909 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
1910#endif
1911
1912#if AIC_DEBUG_REGISTERS
1913ahd_reg_print_t ahd_intvec2_addr_print; 1108ahd_reg_print_t ahd_intvec2_addr_print;
1914#else 1109#else
1915#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1110#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
@@ -1931,24 +1126,17 @@ ahd_reg_print_t ahd_accum_save_print;
1931#endif 1126#endif
1932 1127
1933#if AIC_DEBUG_REGISTERS 1128#if AIC_DEBUG_REGISTERS
1934ahd_reg_print_t ahd_waiting_scb_tails_print; 1129ahd_reg_print_t ahd_sram_base_print;
1935#else
1936#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1937 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1938#endif
1939
1940#if AIC_DEBUG_REGISTERS
1941ahd_reg_print_t ahd_ahd_pci_config_base_print;
1942#else 1130#else
1943#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1131#define ahd_sram_base_print(regvalue, cur_col, wrap) \
1944 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1132 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1945#endif 1133#endif
1946 1134
1947#if AIC_DEBUG_REGISTERS 1135#if AIC_DEBUG_REGISTERS
1948ahd_reg_print_t ahd_sram_base_print; 1136ahd_reg_print_t ahd_waiting_scb_tails_print;
1949#else 1137#else
1950#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1138#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1951 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1139 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1952#endif 1140#endif
1953 1141
1954#if AIC_DEBUG_REGISTERS 1142#if AIC_DEBUG_REGISTERS
@@ -2218,17 +1406,17 @@ ahd_reg_print_t ahd_mk_message_scsiid_print;
2218#endif 1406#endif
2219 1407
2220#if AIC_DEBUG_REGISTERS 1408#if AIC_DEBUG_REGISTERS
2221ahd_reg_print_t ahd_scb_base_print; 1409ahd_reg_print_t ahd_scb_residual_datacnt_print;
2222#else 1410#else
2223#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 1411#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
2224 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 1412 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
2225#endif 1413#endif
2226 1414
2227#if AIC_DEBUG_REGISTERS 1415#if AIC_DEBUG_REGISTERS
2228ahd_reg_print_t ahd_scb_residual_datacnt_print; 1416ahd_reg_print_t ahd_scb_base_print;
2229#else 1417#else
2230#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 1418#define ahd_scb_base_print(regvalue, cur_col, wrap) \
2231 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 1419 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
2232#endif 1420#endif
2233 1421
2234#if AIC_DEBUG_REGISTERS 1422#if AIC_DEBUG_REGISTERS
@@ -2246,27 +1434,6 @@ ahd_reg_print_t ahd_scb_scsi_status_print;
2246#endif 1434#endif
2247 1435
2248#if AIC_DEBUG_REGISTERS 1436#if AIC_DEBUG_REGISTERS
2249ahd_reg_print_t ahd_scb_target_phases_print;
2250#else
2251#define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \
2252 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap)
2253#endif
2254
2255#if AIC_DEBUG_REGISTERS
2256ahd_reg_print_t ahd_scb_target_data_dir_print;
2257#else
2258#define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \
2259 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap)
2260#endif
2261
2262#if AIC_DEBUG_REGISTERS
2263ahd_reg_print_t ahd_scb_target_itag_print;
2264#else
2265#define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \
2266 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap)
2267#endif
2268
2269#if AIC_DEBUG_REGISTERS
2270ahd_reg_print_t ahd_scb_sense_busaddr_print; 1437ahd_reg_print_t ahd_scb_sense_busaddr_print;
2271#else 1438#else
2272#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 1439#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
@@ -2365,13 +1532,6 @@ ahd_reg_print_t ahd_scb_next2_print;
2365#endif 1532#endif
2366 1533
2367#if AIC_DEBUG_REGISTERS 1534#if AIC_DEBUG_REGISTERS
2368ahd_reg_print_t ahd_scb_spare_print;
2369#else
2370#define ahd_scb_spare_print(regvalue, cur_col, wrap) \
2371 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap)
2372#endif
2373
2374#if AIC_DEBUG_REGISTERS
2375ahd_reg_print_t ahd_scb_disconnected_lists_print; 1535ahd_reg_print_t ahd_scb_disconnected_lists_print;
2376#else 1536#else
2377#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 1537#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
@@ -2557,10 +1717,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2557 1717
2558#define SG_CACHE_PRE 0x1b 1718#define SG_CACHE_PRE 0x1b
2559 1719
2560#define LQIN 0x20
2561
2562#define TYPEPTR 0x20 1720#define TYPEPTR 0x20
2563 1721
1722#define LQIN 0x20
1723
2564#define TAGPTR 0x21 1724#define TAGPTR 0x21
2565 1725
2566#define LUNPTR 0x22 1726#define LUNPTR 0x22
@@ -2620,14 +1780,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2620#define SINGLECMD 0x02 1780#define SINGLECMD 0x02
2621#define ABORTPENDING 0x01 1781#define ABORTPENDING 0x01
2622 1782
2623#define SCSBIST0 0x39
2624#define GSBISTERR 0x40
2625#define GSBISTDONE 0x20
2626#define GSBISTRUN 0x10
2627#define OSBISTERR 0x04
2628#define OSBISTDONE 0x02
2629#define OSBISTRUN 0x01
2630
2631#define LQCTL2 0x39 1783#define LQCTL2 0x39
2632#define LQIRETRY 0x80 1784#define LQIRETRY 0x80
2633#define LQICONTINUE 0x40 1785#define LQICONTINUE 0x40
@@ -2638,10 +1790,13 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2638#define LQOTOIDLE 0x02 1790#define LQOTOIDLE 0x02
2639#define LQOPAUSE 0x01 1791#define LQOPAUSE 0x01
2640 1792
2641#define SCSBIST1 0x3a 1793#define SCSBIST0 0x39
2642#define NTBISTERR 0x04 1794#define GSBISTERR 0x40
2643#define NTBISTDONE 0x02 1795#define GSBISTDONE 0x20
2644#define NTBISTRUN 0x01 1796#define GSBISTRUN 0x10
1797#define OSBISTERR 0x04
1798#define OSBISTDONE 0x02
1799#define OSBISTRUN 0x01
2645 1800
2646#define SCSISEQ0 0x3a 1801#define SCSISEQ0 0x3a
2647#define TEMODEO 0x80 1802#define TEMODEO 0x80
@@ -2650,8 +1805,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2650#define FORCEBUSFREE 0x10 1805#define FORCEBUSFREE 0x10
2651#define SCSIRSTO 0x01 1806#define SCSIRSTO 0x01
2652 1807
1808#define SCSBIST1 0x3a
1809#define NTBISTERR 0x04
1810#define NTBISTDONE 0x02
1811#define NTBISTRUN 0x01
1812
2653#define SCSISEQ1 0x3b 1813#define SCSISEQ1 0x3b
2654 1814
1815#define BUSINITID 0x3c
1816
2655#define SXFRCTL0 0x3c 1817#define SXFRCTL0 0x3c
2656#define DFON 0x80 1818#define DFON 0x80
2657#define DFPEXP 0x40 1819#define DFPEXP 0x40
@@ -2660,8 +1822,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2660 1822
2661#define DLCOUNT 0x3c 1823#define DLCOUNT 0x3c
2662 1824
2663#define BUSINITID 0x3c
2664
2665#define SXFRCTL1 0x3d 1825#define SXFRCTL1 0x3d
2666#define BITBUCKET 0x80 1826#define BITBUCKET 0x80
2667#define ENSACHK 0x40 1827#define ENSACHK 0x40
@@ -2686,6 +1846,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2686#define CURRFIFO_1 0x01 1846#define CURRFIFO_1 0x01
2687#define CURRFIFO_0 0x00 1847#define CURRFIFO_0 0x00
2688 1848
1849#define MULTARGID 0x40
1850
2689#define SCSISIGO 0x40 1851#define SCSISIGO 0x40
2690#define CDO 0x80 1852#define CDO 0x80
2691#define IOO 0x40 1853#define IOO 0x40
@@ -2696,8 +1858,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2696#define REQO 0x02 1858#define REQO 0x02
2697#define ACKO 0x01 1859#define ACKO 0x01
2698 1860
2699#define MULTARGID 0x40
2700
2701#define SCSISIGI 0x41 1861#define SCSISIGI 0x41
2702#define ATNI 0x10 1862#define ATNI 0x10
2703#define SELI 0x08 1863#define SELI 0x08
@@ -2744,15 +1904,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2744#define ENAB20 0x04 1904#define ENAB20 0x04
2745#define SELWIDE 0x02 1905#define SELWIDE 0x02
2746 1906
2747#define CLRSINT0 0x4b
2748#define CLRSELDO 0x40
2749#define CLRSELDI 0x20
2750#define CLRSELINGO 0x10
2751#define CLRIOERR 0x08
2752#define CLROVERRUN 0x04
2753#define CLRSPIORDY 0x02
2754#define CLRARBDO 0x01
2755
2756#define SSTAT0 0x4b 1907#define SSTAT0 0x4b
2757#define TARGET 0x80 1908#define TARGET 0x80
2758#define SELDO 0x40 1909#define SELDO 0x40
@@ -2772,14 +1923,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2772#define ENSPIORDY 0x02 1923#define ENSPIORDY 0x02
2773#define ENARBDO 0x01 1924#define ENARBDO 0x01
2774 1925
2775#define CLRSINT1 0x4c 1926#define CLRSINT0 0x4b
2776#define CLRSELTIMEO 0x80 1927#define CLRSELDO 0x40
2777#define CLRATNO 0x40 1928#define CLRSELDI 0x20
2778#define CLRSCSIRSTI 0x20 1929#define CLRSELINGO 0x10
2779#define CLRBUSFREE 0x08 1930#define CLRIOERR 0x08
2780#define CLRSCSIPERR 0x04 1931#define CLROVERRUN 0x04
2781#define CLRSTRB2FAST 0x02 1932#define CLRSPIORDY 0x02
2782#define CLRREQINIT 0x01 1933#define CLRARBDO 0x01
2783 1934
2784#define SSTAT1 0x4c 1935#define SSTAT1 0x4c
2785#define SELTO 0x80 1936#define SELTO 0x80
@@ -2791,6 +1942,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2791#define STRB2FAST 0x02 1942#define STRB2FAST 0x02
2792#define REQINIT 0x01 1943#define REQINIT 0x01
2793 1944
1945#define CLRSINT1 0x4c
1946#define CLRSELTIMEO 0x80
1947#define CLRATNO 0x40
1948#define CLRSCSIRSTI 0x20
1949#define CLRBUSFREE 0x08
1950#define CLRSCSIPERR 0x04
1951#define CLRSTRB2FAST 0x02
1952#define CLRREQINIT 0x01
1953
2794#define SSTAT2 0x4d 1954#define SSTAT2 0x4d
2795#define BUSFREETIME 0xc0 1955#define BUSFREETIME 0xc0
2796#define NONPACKREQ 0x20 1956#define NONPACKREQ 0x20
@@ -2838,14 +1998,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2838#define LQIATNLQ 0x02 1998#define LQIATNLQ 0x02
2839#define LQIATNCMD 0x01 1999#define LQIATNCMD 0x01
2840 2000
2841#define CLRLQIINT0 0x50
2842#define CLRLQIATNQAS 0x20
2843#define CLRLQICRCT1 0x10
2844#define CLRLQICRCT2 0x08
2845#define CLRLQIBADLQT 0x04
2846#define CLRLQIATNLQ 0x02
2847#define CLRLQIATNCMD 0x01
2848
2849#define LQIMODE0 0x50 2001#define LQIMODE0 0x50
2850#define ENLQIATNQASK 0x20 2002#define ENLQIATNQASK 0x20
2851#define ENLQICRCT1 0x10 2003#define ENLQICRCT1 0x10
@@ -2854,6 +2006,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2854#define ENLQIATNLQ 0x02 2006#define ENLQIATNLQ 0x02
2855#define ENLQIATNCMD 0x01 2007#define ENLQIATNCMD 0x01
2856 2008
2009#define CLRLQIINT0 0x50
2010#define CLRLQIATNQAS 0x20
2011#define CLRLQICRCT1 0x10
2012#define CLRLQICRCT2 0x08
2013#define CLRLQIBADLQT 0x04
2014#define CLRLQIATNLQ 0x02
2015#define CLRLQIATNCMD 0x01
2016
2857#define LQIMODE1 0x51 2017#define LQIMODE1 0x51
2858#define ENLQIPHASE_LQ 0x80 2018#define ENLQIPHASE_LQ 0x80
2859#define ENLQIPHASE_NLQ 0x40 2019#define ENLQIPHASE_NLQ 0x40
@@ -2976,6 +2136,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2976 2136
2977#define LQOSCSCTL 0x5a 2137#define LQOSCSCTL 0x5a
2978#define LQOH2A_VERSION 0x80 2138#define LQOH2A_VERSION 0x80
2139#define LQOBUSETDLY 0x40
2140#define LQONOHOLDLACK 0x02
2979#define LQONOCHKOVER 0x01 2141#define LQONOCHKOVER 0x01
2980 2142
2981#define NEXTSCB 0x5a 2143#define NEXTSCB 0x5a
@@ -2998,8 +2160,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2998#define CFG4ICMD 0x02 2160#define CFG4ICMD 0x02
2999#define CFG4TCMD 0x01 2161#define CFG4TCMD 0x01
3000 2162
3001#define CURRSCB 0x5c
3002
3003#define SEQIMODE 0x5c 2163#define SEQIMODE 0x5c
3004#define ENCTXTDONE 0x40 2164#define ENCTXTDONE 0x40
3005#define ENSAVEPTRS 0x20 2165#define ENSAVEPTRS 0x20
@@ -3009,6 +2169,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3009#define ENCFG4ICMD 0x02 2169#define ENCFG4ICMD 0x02
3010#define ENCFG4TCMD 0x01 2170#define ENCFG4TCMD 0x01
3011 2171
2172#define CURRSCB 0x5c
2173
3012#define MDFFSTAT 0x5d 2174#define MDFFSTAT 0x5d
3013#define SHCNTNEGATIVE 0x40 2175#define SHCNTNEGATIVE 0x40
3014#define SHCNTMINUS1 0x20 2176#define SHCNTMINUS1 0x20
@@ -3023,29 +2185,29 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3023 2185
3024#define DFFTAG 0x5e 2186#define DFFTAG 0x5e
3025 2187
3026#define LASTSCB 0x5e
3027
3028#define SCSITEST 0x5e 2188#define SCSITEST 0x5e
3029#define CNTRTEST 0x08 2189#define CNTRTEST 0x08
3030#define SEL_TXPLL_DEBUG 0x04 2190#define SEL_TXPLL_DEBUG 0x04
3031 2191
2192#define LASTSCB 0x5e
2193
3032#define IOPDNCTL 0x5f 2194#define IOPDNCTL 0x5f
3033#define DISABLE_OE 0x80 2195#define DISABLE_OE 0x80
3034#define PDN_IDIST 0x04 2196#define PDN_IDIST 0x04
3035#define PDN_DIFFSENSE 0x01 2197#define PDN_DIFFSENSE 0x01
3036 2198
2199#define DGRPCRCI 0x60
2200
3037#define SHADDR 0x60 2201#define SHADDR 0x60
3038 2202
3039#define NEGOADDR 0x60 2203#define NEGOADDR 0x60
3040 2204
3041#define DGRPCRCI 0x60
3042
3043#define NEGPERIOD 0x61 2205#define NEGPERIOD 0x61
3044 2206
3045#define PACKCRCI 0x62
3046
3047#define NEGOFFSET 0x62 2207#define NEGOFFSET 0x62
3048 2208
2209#define PACKCRCI 0x62
2210
3049#define NEGPPROPTS 0x63 2211#define NEGPPROPTS 0x63
3050#define PPROPT_PACE 0x08 2212#define PPROPT_PACE 0x08
3051#define PPROPT_QAS 0x04 2213#define PPROPT_QAS 0x04
@@ -3066,6 +2228,7 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3066#define ANNEXDAT 0x66 2228#define ANNEXDAT 0x66
3067 2229
3068#define SCSCHKN 0x66 2230#define SCSCHKN 0x66
2231#define BIDICHKDIS 0x80
3069#define STSELSKIDDIS 0x40 2232#define STSELSKIDDIS 0x40
3070#define CURRFIFODEF 0x20 2233#define CURRFIFODEF 0x20
3071#define WIDERESEN 0x10 2234#define WIDERESEN 0x10
@@ -3090,6 +2253,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3090 2253
3091#define SELOID 0x6b 2254#define SELOID 0x6b
3092 2255
2256#define FAIRNESS 0x6c
2257
3093#define PLL400CTL0 0x6c 2258#define PLL400CTL0 0x6c
3094#define PLL_VCOSEL 0x80 2259#define PLL_VCOSEL 0x80
3095#define PLL_PWDN 0x40 2260#define PLL_PWDN 0x40
@@ -3099,8 +2264,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3099#define PLL_DLPF 0x02 2264#define PLL_DLPF 0x02
3100#define PLL_ENFBM 0x01 2265#define PLL_ENFBM 0x01
3101 2266
3102#define FAIRNESS 0x6c
3103
3104#define PLL400CTL1 0x6d 2267#define PLL400CTL1 0x6d
3105#define PLL_CNTEN 0x80 2268#define PLL_CNTEN 0x80
3106#define PLL_CNTCLR 0x40 2269#define PLL_CNTCLR 0x40
@@ -3112,25 +2275,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3112 2275
3113#define HADDR 0x70 2276#define HADDR 0x70
3114 2277
2278#define HODMAADR 0x70
2279
3115#define PLLDELAY 0x70 2280#define PLLDELAY 0x70
3116#define SPLIT_DROP_REQ 0x80 2281#define SPLIT_DROP_REQ 0x80
3117 2282
3118#define HODMAADR 0x70 2283#define HCNT 0x78
3119 2284
3120#define HODMACNT 0x78 2285#define HODMACNT 0x78
3121 2286
3122#define HCNT 0x78
3123
3124#define HODMAEN 0x7a 2287#define HODMAEN 0x7a
3125 2288
3126#define SCBHADDR 0x7c
3127
3128#define SGHADDR 0x7c 2289#define SGHADDR 0x7c
3129 2290
3130#define SCBHCNT 0x84 2291#define SCBHADDR 0x7c
3131 2292
3132#define SGHCNT 0x84 2293#define SGHCNT 0x84
3133 2294
2295#define SCBHCNT 0x84
2296
3134#define DFF_THRSH 0x88 2297#define DFF_THRSH 0x88
3135#define WR_DFTHRSH 0x70 2298#define WR_DFTHRSH 0x70
3136#define RD_DFTHRSH 0x07 2299#define RD_DFTHRSH 0x07
@@ -3163,6 +2326,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3163 2326
3164#define CMCRXMSG0 0x90 2327#define CMCRXMSG0 0x90
3165 2328
2329#define OVLYRXMSG0 0x90
2330
2331#define DCHRXMSG0 0x90
2332
3166#define ROENABLE 0x90 2333#define ROENABLE 0x90
3167#define MSIROEN 0x20 2334#define MSIROEN 0x20
3168#define OVLYROEN 0x10 2335#define OVLYROEN 0x10
@@ -3171,11 +2338,11 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3171#define DCH1ROEN 0x02 2338#define DCH1ROEN 0x02
3172#define DCH0ROEN 0x01 2339#define DCH0ROEN 0x01
3173 2340
3174#define OVLYRXMSG0 0x90 2341#define OVLYRXMSG1 0x91
3175 2342
3176#define DCHRXMSG0 0x90 2343#define CMCRXMSG1 0x91
3177 2344
3178#define OVLYRXMSG1 0x91 2345#define DCHRXMSG1 0x91
3179 2346
3180#define NSENABLE 0x91 2347#define NSENABLE 0x91
3181#define MSINSEN 0x20 2348#define MSINSEN 0x20
@@ -3185,10 +2352,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3185#define DCH1NSEN 0x02 2352#define DCH1NSEN 0x02
3186#define DCH0NSEN 0x01 2353#define DCH0NSEN 0x01
3187 2354
3188#define CMCRXMSG1 0x91
3189
3190#define DCHRXMSG1 0x91
3191
3192#define DCHRXMSG2 0x92 2355#define DCHRXMSG2 0x92
3193 2356
3194#define CMCRXMSG2 0x92 2357#define CMCRXMSG2 0x92
@@ -3212,24 +2375,24 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3212#define TSCSERREN 0x02 2375#define TSCSERREN 0x02
3213#define CMPABCDIS 0x01 2376#define CMPABCDIS 0x01
3214 2377
2378#define CMCSEQBCNT 0x94
2379
3215#define OVLYSEQBCNT 0x94 2380#define OVLYSEQBCNT 0x94
3216 2381
3217#define DCHSEQBCNT 0x94 2382#define DCHSEQBCNT 0x94
3218 2383
3219#define CMCSEQBCNT 0x94
3220
3221#define CMCSPLTSTAT0 0x96
3222
3223#define DCHSPLTSTAT0 0x96 2384#define DCHSPLTSTAT0 0x96
3224 2385
3225#define OVLYSPLTSTAT0 0x96 2386#define OVLYSPLTSTAT0 0x96
3226 2387
3227#define CMCSPLTSTAT1 0x97 2388#define CMCSPLTSTAT0 0x96
3228 2389
3229#define OVLYSPLTSTAT1 0x97 2390#define OVLYSPLTSTAT1 0x97
3230 2391
3231#define DCHSPLTSTAT1 0x97 2392#define DCHSPLTSTAT1 0x97
3232 2393
2394#define CMCSPLTSTAT1 0x97
2395
3233#define SGRXMSG0 0x98 2396#define SGRXMSG0 0x98
3234#define CDNUM 0xf8 2397#define CDNUM 0xf8
3235#define CFNUM 0x07 2398#define CFNUM 0x07
@@ -3257,18 +2420,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3257#define TAG_NUM 0x1f 2420#define TAG_NUM 0x1f
3258#define RLXORD 0x10 2421#define RLXORD 0x10
3259 2422
3260#define SGSEQBCNT 0x9c
3261
3262#define SLVSPLTOUTATTR0 0x9c 2423#define SLVSPLTOUTATTR0 0x9c
3263#define LOWER_BCNT 0xff 2424#define LOWER_BCNT 0xff
3264 2425
2426#define SGSEQBCNT 0x9c
2427
3265#define SLVSPLTOUTATTR1 0x9d 2428#define SLVSPLTOUTATTR1 0x9d
3266#define CMPLT_DNUM 0xf8 2429#define CMPLT_DNUM 0xf8
3267#define CMPLT_FNUM 0x07 2430#define CMPLT_FNUM 0x07
3268 2431
3269#define SLVSPLTOUTATTR2 0x9e
3270#define CMPLT_BNUM 0xff
3271
3272#define SGSPLTSTAT0 0x9e 2432#define SGSPLTSTAT0 0x9e
3273#define STAETERM 0x80 2433#define STAETERM 0x80
3274#define SCBCERR 0x40 2434#define SCBCERR 0x40
@@ -3279,6 +2439,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3279#define RXSCEMSG 0x02 2439#define RXSCEMSG 0x02
3280#define RXSPLTRSP 0x01 2440#define RXSPLTRSP 0x01
3281 2441
2442#define SLVSPLTOUTATTR2 0x9e
2443#define CMPLT_BNUM 0xff
2444
3282#define SGSPLTSTAT1 0x9f 2445#define SGSPLTSTAT1 0x9f
3283#define RXDATABUCKET 0x01 2446#define RXDATABUCKET 0x01
3284 2447
@@ -3334,10 +2497,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3334 2497
3335#define CCSGADDR 0xac 2498#define CCSGADDR 0xac
3336 2499
3337#define CCSCBADR_BK 0xac
3338
3339#define CCSCBADDR 0xac 2500#define CCSCBADDR 0xac
3340 2501
2502#define CCSCBADR_BK 0xac
2503
3341#define CMC_RAMBIST 0xad 2504#define CMC_RAMBIST 0xad
3342#define SG_ELEMENT_SIZE 0x80 2505#define SG_ELEMENT_SIZE 0x80
3343#define SCBRAMBIST_FAIL 0x40 2506#define SCBRAMBIST_FAIL 0x40
@@ -3391,9 +2554,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3391#define SEEDAT 0xbc 2554#define SEEDAT 0xbc
3392 2555
3393#define SEECTL 0xbe 2556#define SEECTL 0xbe
2557#define SEEOP_EWDS 0x40
3394#define SEEOP_WALL 0x40 2558#define SEEOP_WALL 0x40
3395#define SEEOP_EWEN 0x40 2559#define SEEOP_EWEN 0x40
3396#define SEEOP_EWDS 0x40
3397#define SEEOPCODE 0x70 2560#define SEEOPCODE 0x70
3398#define SEERST 0x02 2561#define SEERST 0x02
3399#define SEESTART 0x01 2562#define SEESTART 0x01
@@ -3410,25 +2573,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3410 2573
3411#define SCBCNT 0xbf 2574#define SCBCNT 0xbf
3412 2575
3413#define DFWADDR 0xc0
3414
3415#define DSPFLTRCTL 0xc0 2576#define DSPFLTRCTL 0xc0
3416#define FLTRDISABLE 0x20 2577#define FLTRDISABLE 0x20
3417#define EDGESENSE 0x10 2578#define EDGESENSE 0x10
3418#define DSPFCNTSEL 0x0f 2579#define DSPFCNTSEL 0x0f
3419 2580
2581#define DFWADDR 0xc0
2582
3420#define DSPDATACTL 0xc1 2583#define DSPDATACTL 0xc1
3421#define BYPASSENAB 0x80 2584#define BYPASSENAB 0x80
3422#define DESQDIS 0x10 2585#define DESQDIS 0x10
3423#define RCVROFFSTDIS 0x04 2586#define RCVROFFSTDIS 0x04
3424#define XMITOFFSTDIS 0x02 2587#define XMITOFFSTDIS 0x02
3425 2588
3426#define DFRADDR 0xc2
3427
3428#define DSPREQCTL 0xc2 2589#define DSPREQCTL 0xc2
3429#define MANREQCTL 0xc0 2590#define MANREQCTL 0xc0
3430#define MANREQDLY 0x3f 2591#define MANREQDLY 0x3f
3431 2592
2593#define DFRADDR 0xc2
2594
3432#define DSPACKCTL 0xc3 2595#define DSPACKCTL 0xc3
3433#define MANACKCTL 0xc0 2596#define MANACKCTL 0xc0
3434#define MANACKDLY 0x3f 2597#define MANACKDLY 0x3f
@@ -3449,14 +2612,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3449 2612
3450#define WRTBIASCALC 0xc7 2613#define WRTBIASCALC 0xc7
3451 2614
3452#define RCVRBIASCALC 0xc8
3453
3454#define DFPTRS 0xc8 2615#define DFPTRS 0xc8
3455 2616
3456#define SKEWCALC 0xc9 2617#define RCVRBIASCALC 0xc8
3457 2618
3458#define DFBKPTR 0xc9 2619#define DFBKPTR 0xc9
3459 2620
2621#define SKEWCALC 0xc9
2622
3460#define DFDBCTL 0xcb 2623#define DFDBCTL 0xcb
3461#define DFF_CIO_WR_RDY 0x20 2624#define DFF_CIO_WR_RDY 0x20
3462#define DFF_CIO_RD_RDY 0x10 2625#define DFF_CIO_RD_RDY 0x10
@@ -3541,12 +2704,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3541 2704
3542#define ACCUM_SAVE 0xfa 2705#define ACCUM_SAVE 0xfa
3543 2706
3544#define WAITING_SCB_TAILS 0x100
3545
3546#define AHD_PCI_CONFIG_BASE 0x100 2707#define AHD_PCI_CONFIG_BASE 0x100
3547 2708
3548#define SRAM_BASE 0x100 2709#define SRAM_BASE 0x100
3549 2710
2711#define WAITING_SCB_TAILS 0x100
2712
3550#define WAITING_TID_HEAD 0x120 2713#define WAITING_TID_HEAD 0x120
3551 2714
3552#define WAITING_TID_TAIL 0x122 2715#define WAITING_TID_TAIL 0x122
@@ -3575,8 +2738,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3575#define PRELOADEN 0x80 2738#define PRELOADEN 0x80
3576#define WIDEODD 0x40 2739#define WIDEODD 0x40
3577#define SCSIEN 0x20 2740#define SCSIEN 0x20
3578#define SDMAEN 0x10
3579#define SDMAENACK 0x10 2741#define SDMAENACK 0x10
2742#define SDMAEN 0x10
3580#define HDMAEN 0x08 2743#define HDMAEN 0x08
3581#define HDMAENACK 0x08 2744#define HDMAENACK 0x08
3582#define DIRECTION 0x04 2745#define DIRECTION 0x04
@@ -3674,12 +2837,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3674 2837
3675#define MK_MESSAGE_SCSIID 0x162 2838#define MK_MESSAGE_SCSIID 0x162
3676 2839
3677#define SCB_BASE 0x180
3678
3679#define SCB_RESIDUAL_DATACNT 0x180 2840#define SCB_RESIDUAL_DATACNT 0x180
3680#define SCB_CDB_STORE 0x180 2841#define SCB_CDB_STORE 0x180
3681#define SCB_HOST_CDB_PTR 0x180 2842#define SCB_HOST_CDB_PTR 0x180
3682 2843
2844#define SCB_BASE 0x180
2845
3683#define SCB_RESIDUAL_SGPTR 0x184 2846#define SCB_RESIDUAL_SGPTR 0x184
3684#define SG_ADDR_MASK 0xf8 2847#define SG_ADDR_MASK 0xf8
3685#define SG_OVERRUN_RESID 0x02 2848#define SG_OVERRUN_RESID 0x02
@@ -3747,6 +2910,17 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3747#define SCB_DISCONNECTED_LISTS 0x1b8 2910#define SCB_DISCONNECTED_LISTS 0x1b8
3748 2911
3749 2912
2913#define CMD_GROUP_CODE_SHIFT 0x05
2914#define STIMESEL_MIN 0x18
2915#define STIMESEL_SHIFT 0x03
2916#define INVALID_ADDR 0x80
2917#define AHD_PRECOMP_MASK 0x07
2918#define TARGET_DATA_IN 0x01
2919#define CCSCBADDR_MAX 0x80
2920#define NUMDSPS 0x14
2921#define SEEOP_EWEN_ADDR 0xc0
2922#define AHD_ANNEXCOL_PER_DEV0 0x04
2923#define DST_MODE_SHIFT 0x04
3750#define AHD_TIMER_MAX_US 0x18ffe7 2924#define AHD_TIMER_MAX_US 0x18ffe7
3751#define AHD_TIMER_MAX_TICKS 0xffff 2925#define AHD_TIMER_MAX_TICKS 0xffff
3752#define AHD_SENSE_BUFSIZE 0x100 2926#define AHD_SENSE_BUFSIZE 0x100
@@ -3781,43 +2955,32 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3781#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 2955#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
3782#define NVRAM_SCB_OFFSET 0x2c 2956#define NVRAM_SCB_OFFSET 0x2c
3783#define STATUS_PKT_SENSE 0xff 2957#define STATUS_PKT_SENSE 0xff
3784#define CMD_GROUP_CODE_SHIFT 0x05
3785#define MAX_OFFSET_PACED_BUG 0x7f 2958#define MAX_OFFSET_PACED_BUG 0x7f
3786#define STIMESEL_BUG_ADJ 0x08 2959#define STIMESEL_BUG_ADJ 0x08
3787#define STIMESEL_MIN 0x18
3788#define STIMESEL_SHIFT 0x03
3789#define CCSGRAM_MAXSEGS 0x10 2960#define CCSGRAM_MAXSEGS 0x10
3790#define INVALID_ADDR 0x80
3791#define SEEOP_ERAL_ADDR 0x80 2961#define SEEOP_ERAL_ADDR 0x80
3792#define AHD_SLEWRATE_DEF_REVB 0x08 2962#define AHD_SLEWRATE_DEF_REVB 0x08
3793#define AHD_PRECOMP_CUTBACK_17 0x04 2963#define AHD_PRECOMP_CUTBACK_17 0x04
3794#define AHD_PRECOMP_MASK 0x07
3795#define SRC_MODE_SHIFT 0x00 2964#define SRC_MODE_SHIFT 0x00
3796#define PKT_OVERRUN_BUFSIZE 0x200 2965#define PKT_OVERRUN_BUFSIZE 0x200
3797#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 2966#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
3798#define TARGET_DATA_IN 0x01
3799#define HOST_MSG 0xff 2967#define HOST_MSG 0xff
3800#define MAX_OFFSET 0xfe 2968#define MAX_OFFSET 0xfe
3801#define BUS_16_BIT 0x01 2969#define BUS_16_BIT 0x01
3802#define CCSCBADDR_MAX 0x80
3803#define NUMDSPS 0x14
3804#define SEEOP_EWEN_ADDR 0xc0
3805#define AHD_ANNEXCOL_PER_DEV0 0x04
3806#define DST_MODE_SHIFT 0x04
3807 2970
3808 2971
3809/* Downloaded Constant Definitions */ 2972/* Downloaded Constant Definitions */
2973#define SG_SIZEOF 0x04
2974#define SG_PREFETCH_ALIGN_MASK 0x02
2975#define SG_PREFETCH_CNT_LIMIT 0x01
3810#define CACHELINE_MASK 0x07 2976#define CACHELINE_MASK 0x07
3811#define SCB_TRANSFER_SIZE 0x06 2977#define SCB_TRANSFER_SIZE 0x06
3812#define PKT_OVERRUN_BUFOFFSET 0x05 2978#define PKT_OVERRUN_BUFOFFSET 0x05
3813#define SG_SIZEOF 0x04
3814#define SG_PREFETCH_ADDR_MASK 0x03 2979#define SG_PREFETCH_ADDR_MASK 0x03
3815#define SG_PREFETCH_ALIGN_MASK 0x02
3816#define SG_PREFETCH_CNT_LIMIT 0x01
3817#define SG_PREFETCH_CNT 0x00 2980#define SG_PREFETCH_CNT 0x00
3818#define DOWNLOAD_CONST_COUNT 0x08 2981#define DOWNLOAD_CONST_COUNT 0x08
3819 2982
3820 2983
3821/* Exported Labels */ 2984/* Exported Labels */
3822#define LABEL_seq_isr 0x28f
3823#define LABEL_timer_isr 0x28b 2985#define LABEL_timer_isr 0x28b
2986#define LABEL_seq_isr 0x28f
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
index db38a61a8cb4..c4c8a96bf5a3 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
@@ -8,7 +8,7 @@
8 8
9#include "aic79xx_osm.h" 9#include "aic79xx_osm.h"
10 10
11static ahd_reg_parse_entry_t MODE_PTR_parse_table[] = { 11static const ahd_reg_parse_entry_t MODE_PTR_parse_table[] = {
12 { "SRC_MODE", 0x07, 0x07 }, 12 { "SRC_MODE", 0x07, 0x07 },
13 { "DST_MODE", 0x70, 0x70 } 13 { "DST_MODE", 0x70, 0x70 }
14}; 14};
@@ -20,7 +20,7 @@ ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
20 0x00, regvalue, cur_col, wrap)); 20 0x00, regvalue, cur_col, wrap));
21} 21}
22 22
23static ahd_reg_parse_entry_t INTSTAT_parse_table[] = { 23static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
24 { "SPLTINT", 0x01, 0x01 }, 24 { "SPLTINT", 0x01, 0x01 },
25 { "CMDCMPLT", 0x02, 0x02 }, 25 { "CMDCMPLT", 0x02, 0x02 },
26 { "SEQINT", 0x04, 0x04 }, 26 { "SEQINT", 0x04, 0x04 },
@@ -39,7 +39,7 @@ ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
39 0x01, regvalue, cur_col, wrap)); 39 0x01, regvalue, cur_col, wrap));
40} 40}
41 41
42static ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = { 42static const ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = {
43 { "NO_SEQINT", 0x00, 0xff }, 43 { "NO_SEQINT", 0x00, 0xff },
44 { "BAD_PHASE", 0x01, 0xff }, 44 { "BAD_PHASE", 0x01, 0xff },
45 { "SEND_REJECT", 0x02, 0xff }, 45 { "SEND_REJECT", 0x02, 0xff },
@@ -76,7 +76,7 @@ ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap)
76 0x02, regvalue, cur_col, wrap)); 76 0x02, regvalue, cur_col, wrap));
77} 77}
78 78
79static ahd_reg_parse_entry_t CLRINT_parse_table[] = { 79static const ahd_reg_parse_entry_t CLRINT_parse_table[] = {
80 { "CLRSPLTINT", 0x01, 0x01 }, 80 { "CLRSPLTINT", 0x01, 0x01 },
81 { "CLRCMDINT", 0x02, 0x02 }, 81 { "CLRCMDINT", 0x02, 0x02 },
82 { "CLRSEQINT", 0x04, 0x04 }, 82 { "CLRSEQINT", 0x04, 0x04 },
@@ -94,7 +94,7 @@ ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
94 0x03, regvalue, cur_col, wrap)); 94 0x03, regvalue, cur_col, wrap));
95} 95}
96 96
97static ahd_reg_parse_entry_t ERROR_parse_table[] = { 97static const ahd_reg_parse_entry_t ERROR_parse_table[] = {
98 { "DSCTMOUT", 0x02, 0x02 }, 98 { "DSCTMOUT", 0x02, 0x02 },
99 { "ILLOPCODE", 0x04, 0x04 }, 99 { "ILLOPCODE", 0x04, 0x04 },
100 { "SQPARERR", 0x08, 0x08 }, 100 { "SQPARERR", 0x08, 0x08 },
@@ -111,24 +111,7 @@ ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
111 0x04, regvalue, cur_col, wrap)); 111 0x04, regvalue, cur_col, wrap));
112} 112}
113 113
114static ahd_reg_parse_entry_t CLRERR_parse_table[] = { 114static const ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
115 { "CLRDSCTMOUT", 0x02, 0x02 },
116 { "CLRILLOPCODE", 0x04, 0x04 },
117 { "CLRSQPARERR", 0x08, 0x08 },
118 { "CLRDPARERR", 0x10, 0x10 },
119 { "CLRMPARERR", 0x20, 0x20 },
120 { "CLRCIOACCESFAIL", 0x40, 0x40 },
121 { "CLRCIOPARERR", 0x80, 0x80 }
122};
123
124int
125ahd_clrerr_print(u_int regvalue, u_int *cur_col, u_int wrap)
126{
127 return (ahd_print_register(CLRERR_parse_table, 7, "CLRERR",
128 0x04, regvalue, cur_col, wrap));
129}
130
131static ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
132 { "CHIPRST", 0x01, 0x01 }, 115 { "CHIPRST", 0x01, 0x01 },
133 { "CHIPRSTACK", 0x01, 0x01 }, 116 { "CHIPRSTACK", 0x01, 0x01 },
134 { "INTEN", 0x02, 0x02 }, 117 { "INTEN", 0x02, 0x02 },
@@ -160,7 +143,7 @@ ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
160 0x08, regvalue, cur_col, wrap)); 143 0x08, regvalue, cur_col, wrap));
161} 144}
162 145
163static ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 146static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
164 { "ENINT_COALESCE", 0x40, 0x40 }, 147 { "ENINT_COALESCE", 0x40, 0x40 },
165 { "HOST_TQINPOS", 0x80, 0x80 } 148 { "HOST_TQINPOS", 0x80, 0x80 }
166}; 149};
@@ -172,7 +155,7 @@ ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
172 0x0b, regvalue, cur_col, wrap)); 155 0x0b, regvalue, cur_col, wrap));
173} 156}
174 157
175static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = { 158static const ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
176 { "SEQ_SPLTINT", 0x01, 0x01 }, 159 { "SEQ_SPLTINT", 0x01, 0x01 },
177 { "SEQ_PCIINT", 0x02, 0x02 }, 160 { "SEQ_PCIINT", 0x02, 0x02 },
178 { "SEQ_SCSIINT", 0x04, 0x04 }, 161 { "SEQ_SCSIINT", 0x04, 0x04 },
@@ -187,7 +170,7 @@ ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
187 0x0c, regvalue, cur_col, wrap)); 170 0x0c, regvalue, cur_col, wrap));
188} 171}
189 172
190static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = { 173static const ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
191 { "CLRSEQ_SPLTINT", 0x01, 0x01 }, 174 { "CLRSEQ_SPLTINT", 0x01, 0x01 },
192 { "CLRSEQ_PCIINT", 0x02, 0x02 }, 175 { "CLRSEQ_PCIINT", 0x02, 0x02 },
193 { "CLRSEQ_SCSIINT", 0x04, 0x04 }, 176 { "CLRSEQ_SCSIINT", 0x04, 0x04 },
@@ -230,7 +213,7 @@ ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
230 0x14, regvalue, cur_col, wrap)); 213 0x14, regvalue, cur_col, wrap));
231} 214}
232 215
233static ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 216static const ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
234 { "SCB_QSIZE_4", 0x00, 0x0f }, 217 { "SCB_QSIZE_4", 0x00, 0x0f },
235 { "SCB_QSIZE_8", 0x01, 0x0f }, 218 { "SCB_QSIZE_8", 0x01, 0x0f },
236 { "SCB_QSIZE_16", 0x02, 0x0f }, 219 { "SCB_QSIZE_16", 0x02, 0x0f },
@@ -258,7 +241,7 @@ ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
258 0x16, regvalue, cur_col, wrap)); 241 0x16, regvalue, cur_col, wrap));
259} 242}
260 243
261static ahd_reg_parse_entry_t INTCTL_parse_table[] = { 244static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
262 { "SPLTINTEN", 0x01, 0x01 }, 245 { "SPLTINTEN", 0x01, 0x01 },
263 { "SEQINTEN", 0x02, 0x02 }, 246 { "SEQINTEN", 0x02, 0x02 },
264 { "SCSIINTEN", 0x04, 0x04 }, 247 { "SCSIINTEN", 0x04, 0x04 },
@@ -276,7 +259,7 @@ ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
276 0x18, regvalue, cur_col, wrap)); 259 0x18, regvalue, cur_col, wrap));
277} 260}
278 261
279static ahd_reg_parse_entry_t DFCNTRL_parse_table[] = { 262static const ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
280 { "DIRECTIONEN", 0x01, 0x01 }, 263 { "DIRECTIONEN", 0x01, 0x01 },
281 { "FIFOFLUSH", 0x02, 0x02 }, 264 { "FIFOFLUSH", 0x02, 0x02 },
282 { "FIFOFLUSHACK", 0x02, 0x02 }, 265 { "FIFOFLUSHACK", 0x02, 0x02 },
@@ -297,7 +280,7 @@ ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
297 0x19, regvalue, cur_col, wrap)); 280 0x19, regvalue, cur_col, wrap));
298} 281}
299 282
300static ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = { 283static const ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
301 { "CIOPARCKEN", 0x01, 0x01 }, 284 { "CIOPARCKEN", 0x01, 0x01 },
302 { "DISABLE_TWATE", 0x02, 0x02 }, 285 { "DISABLE_TWATE", 0x02, 0x02 },
303 { "EXTREQLCK", 0x10, 0x10 }, 286 { "EXTREQLCK", 0x10, 0x10 },
@@ -313,7 +296,7 @@ ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
313 0x19, regvalue, cur_col, wrap)); 296 0x19, regvalue, cur_col, wrap));
314} 297}
315 298
316static ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { 299static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
317 { "FIFOEMP", 0x01, 0x01 }, 300 { "FIFOEMP", 0x01, 0x01 },
318 { "FIFOFULL", 0x02, 0x02 }, 301 { "FIFOFULL", 0x02, 0x02 },
319 { "DFTHRESH", 0x04, 0x04 }, 302 { "DFTHRESH", 0x04, 0x04 },
@@ -330,7 +313,7 @@ ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
330 0x1a, regvalue, cur_col, wrap)); 313 0x1a, regvalue, cur_col, wrap));
331} 314}
332 315
333static ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 316static const ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
334 { "LAST_SEG_DONE", 0x01, 0x01 }, 317 { "LAST_SEG_DONE", 0x01, 0x01 },
335 { "LAST_SEG", 0x02, 0x02 }, 318 { "LAST_SEG", 0x02, 0x02 },
336 { "ODD_SEG", 0x04, 0x04 }, 319 { "ODD_SEG", 0x04, 0x04 },
@@ -344,20 +327,7 @@ ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
344 0x1b, regvalue, cur_col, wrap)); 327 0x1b, regvalue, cur_col, wrap));
345} 328}
346 329
347static ahd_reg_parse_entry_t ARBCTL_parse_table[] = { 330static const ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
348 { "USE_TIME", 0x07, 0x07 },
349 { "RETRY_SWEN", 0x08, 0x08 },
350 { "RESET_HARB", 0x80, 0x80 }
351};
352
353int
354ahd_arbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
355{
356 return (ahd_print_register(ARBCTL_parse_table, 3, "ARBCTL",
357 0x1b, regvalue, cur_col, wrap));
358}
359
360static ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
361 { "LAST_SEG", 0x02, 0x02 }, 331 { "LAST_SEG", 0x02, 0x02 },
362 { "ODD_SEG", 0x04, 0x04 }, 332 { "ODD_SEG", 0x04, 0x04 },
363 { "SG_ADDR_MASK", 0xf8, 0xf8 } 333 { "SG_ADDR_MASK", 0xf8, 0xf8 }
@@ -378,20 +348,6 @@ ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap)
378} 348}
379 349
380int 350int
381ahd_typeptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
382{
383 return (ahd_print_register(NULL, 0, "TYPEPTR",
384 0x20, regvalue, cur_col, wrap));
385}
386
387int
388ahd_tagptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
389{
390 return (ahd_print_register(NULL, 0, "TAGPTR",
391 0x21, regvalue, cur_col, wrap));
392}
393
394int
395ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 351ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
396{ 352{
397 return (ahd_print_register(NULL, 0, "LUNPTR", 353 return (ahd_print_register(NULL, 0, "LUNPTR",
@@ -399,20 +355,6 @@ ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
399} 355}
400 356
401int 357int
402ahd_datalenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
403{
404 return (ahd_print_register(NULL, 0, "DATALENPTR",
405 0x23, regvalue, cur_col, wrap));
406}
407
408int
409ahd_statlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
410{
411 return (ahd_print_register(NULL, 0, "STATLENPTR",
412 0x24, regvalue, cur_col, wrap));
413}
414
415int
416ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 358ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
417{ 359{
418 return (ahd_print_register(NULL, 0, "CMDLENPTR", 360 return (ahd_print_register(NULL, 0, "CMDLENPTR",
@@ -448,13 +390,6 @@ ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
448} 390}
449 391
450int 392int
451ahd_idptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
452{
453 return (ahd_print_register(NULL, 0, "IDPTR",
454 0x2a, regvalue, cur_col, wrap));
455}
456
457int
458ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 393ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
459{ 394{
460 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR", 395 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR",
@@ -468,28 +403,7 @@ ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
468 0x2c, regvalue, cur_col, wrap)); 403 0x2c, regvalue, cur_col, wrap));
469} 404}
470 405
471int 406static const ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
472ahd_maxcmdbytes_print(u_int regvalue, u_int *cur_col, u_int wrap)
473{
474 return (ahd_print_register(NULL, 0, "MAXCMDBYTES",
475 0x2d, regvalue, cur_col, wrap));
476}
477
478int
479ahd_maxcmd2rcv_print(u_int regvalue, u_int *cur_col, u_int wrap)
480{
481 return (ahd_print_register(NULL, 0, "MAXCMD2RCV",
482 0x2e, regvalue, cur_col, wrap));
483}
484
485int
486ahd_shortthresh_print(u_int regvalue, u_int *cur_col, u_int wrap)
487{
488 return (ahd_print_register(NULL, 0, "SHORTTHRESH",
489 0x2f, regvalue, cur_col, wrap));
490}
491
492static ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
493 { "ILUNLEN", 0x0f, 0x0f }, 407 { "ILUNLEN", 0x0f, 0x0f },
494 { "TLUNLEN", 0xf0, 0xf0 } 408 { "TLUNLEN", 0xf0, 0xf0 }
495}; 409};
@@ -522,49 +436,7 @@ ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
522 0x33, regvalue, cur_col, wrap)); 436 0x33, regvalue, cur_col, wrap));
523} 437}
524 438
525int 439static const ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
526ahd_lqrsvd01_print(u_int regvalue, u_int *cur_col, u_int wrap)
527{
528 return (ahd_print_register(NULL, 0, "LQRSVD01",
529 0x34, regvalue, cur_col, wrap));
530}
531
532int
533ahd_lqrsvd16_print(u_int regvalue, u_int *cur_col, u_int wrap)
534{
535 return (ahd_print_register(NULL, 0, "LQRSVD16",
536 0x35, regvalue, cur_col, wrap));
537}
538
539int
540ahd_lqrsvd17_print(u_int regvalue, u_int *cur_col, u_int wrap)
541{
542 return (ahd_print_register(NULL, 0, "LQRSVD17",
543 0x36, regvalue, cur_col, wrap));
544}
545
546int
547ahd_cmdrsvd0_print(u_int regvalue, u_int *cur_col, u_int wrap)
548{
549 return (ahd_print_register(NULL, 0, "CMDRSVD0",
550 0x37, regvalue, cur_col, wrap));
551}
552
553static ahd_reg_parse_entry_t LQCTL0_parse_table[] = {
554 { "LQ0INITGCLT", 0x03, 0x03 },
555 { "LQ0TARGCLT", 0x0c, 0x0c },
556 { "LQIINITGCLT", 0x30, 0x30 },
557 { "LQITARGCLT", 0xc0, 0xc0 }
558};
559
560int
561ahd_lqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
562{
563 return (ahd_print_register(LQCTL0_parse_table, 4, "LQCTL0",
564 0x38, regvalue, cur_col, wrap));
565}
566
567static ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
568 { "ABORTPENDING", 0x01, 0x01 }, 440 { "ABORTPENDING", 0x01, 0x01 },
569 { "SINGLECMD", 0x02, 0x02 }, 441 { "SINGLECMD", 0x02, 0x02 },
570 { "PCI2PCI", 0x04, 0x04 } 442 { "PCI2PCI", 0x04, 0x04 }
@@ -577,23 +449,7 @@ ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
577 0x38, regvalue, cur_col, wrap)); 449 0x38, regvalue, cur_col, wrap));
578} 450}
579 451
580static ahd_reg_parse_entry_t SCSBIST0_parse_table[] = { 452static const ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
581 { "OSBISTRUN", 0x01, 0x01 },
582 { "OSBISTDONE", 0x02, 0x02 },
583 { "OSBISTERR", 0x04, 0x04 },
584 { "GSBISTRUN", 0x10, 0x10 },
585 { "GSBISTDONE", 0x20, 0x20 },
586 { "GSBISTERR", 0x40, 0x40 }
587};
588
589int
590ahd_scsbist0_print(u_int regvalue, u_int *cur_col, u_int wrap)
591{
592 return (ahd_print_register(SCSBIST0_parse_table, 6, "SCSBIST0",
593 0x39, regvalue, cur_col, wrap));
594}
595
596static ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
597 { "LQOPAUSE", 0x01, 0x01 }, 453 { "LQOPAUSE", 0x01, 0x01 },
598 { "LQOTOIDLE", 0x02, 0x02 }, 454 { "LQOTOIDLE", 0x02, 0x02 },
599 { "LQOCONTINUE", 0x04, 0x04 }, 455 { "LQOCONTINUE", 0x04, 0x04 },
@@ -611,20 +467,7 @@ ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
611 0x39, regvalue, cur_col, wrap)); 467 0x39, regvalue, cur_col, wrap));
612} 468}
613 469
614static ahd_reg_parse_entry_t SCSBIST1_parse_table[] = { 470static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
615 { "NTBISTRUN", 0x01, 0x01 },
616 { "NTBISTDONE", 0x02, 0x02 },
617 { "NTBISTERR", 0x04, 0x04 }
618};
619
620int
621ahd_scsbist1_print(u_int regvalue, u_int *cur_col, u_int wrap)
622{
623 return (ahd_print_register(SCSBIST1_parse_table, 3, "SCSBIST1",
624 0x3a, regvalue, cur_col, wrap));
625}
626
627static ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
628 { "SCSIRSTO", 0x01, 0x01 }, 471 { "SCSIRSTO", 0x01, 0x01 },
629 { "FORCEBUSFREE", 0x10, 0x10 }, 472 { "FORCEBUSFREE", 0x10, 0x10 },
630 { "ENARBO", 0x20, 0x20 }, 473 { "ENARBO", 0x20, 0x20 },
@@ -639,7 +482,7 @@ ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
639 0x3a, regvalue, cur_col, wrap)); 482 0x3a, regvalue, cur_col, wrap));
640} 483}
641 484
642static ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = { 485static const ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
643 { "ALTSTIM", 0x01, 0x01 }, 486 { "ALTSTIM", 0x01, 0x01 },
644 { "ENAUTOATNP", 0x02, 0x02 }, 487 { "ENAUTOATNP", 0x02, 0x02 },
645 { "MANUALP", 0x0c, 0x0c }, 488 { "MANUALP", 0x0c, 0x0c },
@@ -655,7 +498,7 @@ ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
655 0x3b, regvalue, cur_col, wrap)); 498 0x3b, regvalue, cur_col, wrap));
656} 499}
657 500
658static ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = { 501static const ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = {
659 { "SPIOEN", 0x08, 0x08 }, 502 { "SPIOEN", 0x08, 0x08 },
660 { "BIOSCANCELEN", 0x10, 0x10 }, 503 { "BIOSCANCELEN", 0x10, 0x10 },
661 { "DFPEXP", 0x40, 0x40 }, 504 { "DFPEXP", 0x40, 0x40 },
@@ -669,21 +512,7 @@ ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
669 0x3c, regvalue, cur_col, wrap)); 512 0x3c, regvalue, cur_col, wrap));
670} 513}
671 514
672int 515static const ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
673ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
674{
675 return (ahd_print_register(NULL, 0, "DLCOUNT",
676 0x3c, regvalue, cur_col, wrap));
677}
678
679int
680ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
681{
682 return (ahd_print_register(NULL, 0, "BUSINITID",
683 0x3c, regvalue, cur_col, wrap));
684}
685
686static ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
687 { "STPWEN", 0x01, 0x01 }, 516 { "STPWEN", 0x01, 0x01 },
688 { "ACTNEGEN", 0x02, 0x02 }, 517 { "ACTNEGEN", 0x02, 0x02 },
689 { "ENSTIMER", 0x04, 0x04 }, 518 { "ENSTIMER", 0x04, 0x04 },
@@ -700,27 +529,7 @@ ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
700 0x3d, regvalue, cur_col, wrap)); 529 0x3d, regvalue, cur_col, wrap));
701} 530}
702 531
703int 532static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
704ahd_bustargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
705{
706 return (ahd_print_register(NULL, 0, "BUSTARGID",
707 0x3e, regvalue, cur_col, wrap));
708}
709
710static ahd_reg_parse_entry_t SXFRCTL2_parse_table[] = {
711 { "ASU", 0x07, 0x07 },
712 { "CMDDMAEN", 0x08, 0x08 },
713 { "AUTORSTDIS", 0x10, 0x10 }
714};
715
716int
717ahd_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
718{
719 return (ahd_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
720 0x3e, regvalue, cur_col, wrap));
721}
722
723static ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
724 { "CURRFIFO_0", 0x00, 0x03 }, 533 { "CURRFIFO_0", 0x00, 0x03 },
725 { "CURRFIFO_1", 0x01, 0x03 }, 534 { "CURRFIFO_1", 0x01, 0x03 },
726 { "CURRFIFO_NONE", 0x03, 0x03 }, 535 { "CURRFIFO_NONE", 0x03, 0x03 },
@@ -736,7 +545,14 @@ ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
736 0x3f, regvalue, cur_col, wrap)); 545 0x3f, regvalue, cur_col, wrap));
737} 546}
738 547
739static ahd_reg_parse_entry_t SCSISIGO_parse_table[] = { 548int
549ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
550{
551 return (ahd_print_register(NULL, 0, "MULTARGID",
552 0x40, regvalue, cur_col, wrap));
553}
554
555static const ahd_reg_parse_entry_t SCSISIGO_parse_table[] = {
740 { "P_DATAOUT", 0x00, 0xe0 }, 556 { "P_DATAOUT", 0x00, 0xe0 },
741 { "P_DATAOUT_DT", 0x20, 0xe0 }, 557 { "P_DATAOUT_DT", 0x20, 0xe0 },
742 { "P_DATAIN", 0x40, 0xe0 }, 558 { "P_DATAIN", 0x40, 0xe0 },
@@ -763,14 +579,7 @@ ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
763 0x40, regvalue, cur_col, wrap)); 579 0x40, regvalue, cur_col, wrap));
764} 580}
765 581
766int 582static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
767ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
768{
769 return (ahd_print_register(NULL, 0, "MULTARGID",
770 0x40, regvalue, cur_col, wrap));
771}
772
773static ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
774 { "P_DATAOUT", 0x00, 0xe0 }, 583 { "P_DATAOUT", 0x00, 0xe0 },
775 { "P_DATAOUT_DT", 0x20, 0xe0 }, 584 { "P_DATAOUT_DT", 0x20, 0xe0 },
776 { "P_DATAIN", 0x40, 0xe0 }, 585 { "P_DATAIN", 0x40, 0xe0 },
@@ -797,7 +606,7 @@ ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
797 0x41, regvalue, cur_col, wrap)); 606 0x41, regvalue, cur_col, wrap));
798} 607}
799 608
800static ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = { 609static const ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
801 { "DATA_OUT_PHASE", 0x01, 0x03 }, 610 { "DATA_OUT_PHASE", 0x01, 0x03 },
802 { "DATA_IN_PHASE", 0x02, 0x03 }, 611 { "DATA_IN_PHASE", 0x02, 0x03 },
803 { "DATA_PHASE_MASK", 0x03, 0x03 }, 612 { "DATA_PHASE_MASK", 0x03, 0x03 },
@@ -815,13 +624,6 @@ ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
815} 624}
816 625
817int 626int
818ahd_scsidat0_img_print(u_int regvalue, u_int *cur_col, u_int wrap)
819{
820 return (ahd_print_register(NULL, 0, "SCSIDAT0_IMG",
821 0x43, regvalue, cur_col, wrap));
822}
823
824int
825ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap) 627ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap)
826{ 628{
827 return (ahd_print_register(NULL, 0, "SCSIDAT", 629 return (ahd_print_register(NULL, 0, "SCSIDAT",
@@ -835,7 +637,7 @@ ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
835 0x46, regvalue, cur_col, wrap)); 637 0x46, regvalue, cur_col, wrap));
836} 638}
837 639
838static ahd_reg_parse_entry_t TARGIDIN_parse_table[] = { 640static const ahd_reg_parse_entry_t TARGIDIN_parse_table[] = {
839 { "TARGID", 0x0f, 0x0f }, 641 { "TARGID", 0x0f, 0x0f },
840 { "CLKOUT", 0x80, 0x80 } 642 { "CLKOUT", 0x80, 0x80 }
841}; 643};
@@ -847,7 +649,7 @@ ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap)
847 0x48, regvalue, cur_col, wrap)); 649 0x48, regvalue, cur_col, wrap));
848} 650}
849 651
850static ahd_reg_parse_entry_t SELID_parse_table[] = { 652static const ahd_reg_parse_entry_t SELID_parse_table[] = {
851 { "ONEBIT", 0x08, 0x08 }, 653 { "ONEBIT", 0x08, 0x08 },
852 { "SELID_MASK", 0xf0, 0xf0 } 654 { "SELID_MASK", 0xf0, 0xf0 }
853}; 655};
@@ -859,7 +661,7 @@ ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
859 0x49, regvalue, cur_col, wrap)); 661 0x49, regvalue, cur_col, wrap));
860} 662}
861 663
862static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = { 664static const ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
863 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 665 { "AUTO_MSGOUT_DE", 0x02, 0x02 },
864 { "ENDGFORMCHK", 0x04, 0x04 }, 666 { "ENDGFORMCHK", 0x04, 0x04 },
865 { "BUSFREEREV", 0x10, 0x10 }, 667 { "BUSFREEREV", 0x10, 0x10 },
@@ -876,7 +678,7 @@ ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
876 0x4a, regvalue, cur_col, wrap)); 678 0x4a, regvalue, cur_col, wrap));
877} 679}
878 680
879static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = { 681static const ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
880 { "SELWIDE", 0x02, 0x02 }, 682 { "SELWIDE", 0x02, 0x02 },
881 { "ENAB20", 0x04, 0x04 }, 683 { "ENAB20", 0x04, 0x04 },
882 { "ENAB40", 0x08, 0x08 }, 684 { "ENAB40", 0x08, 0x08 },
@@ -891,24 +693,7 @@ ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
891 0x4a, regvalue, cur_col, wrap)); 693 0x4a, regvalue, cur_col, wrap));
892} 694}
893 695
894static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = { 696static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
895 { "CLRARBDO", 0x01, 0x01 },
896 { "CLRSPIORDY", 0x02, 0x02 },
897 { "CLROVERRUN", 0x04, 0x04 },
898 { "CLRIOERR", 0x08, 0x08 },
899 { "CLRSELINGO", 0x10, 0x10 },
900 { "CLRSELDI", 0x20, 0x20 },
901 { "CLRSELDO", 0x40, 0x40 }
902};
903
904int
905ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
906{
907 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
908 0x4b, regvalue, cur_col, wrap));
909}
910
911static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
912 { "ARBDO", 0x01, 0x01 }, 697 { "ARBDO", 0x01, 0x01 },
913 { "SPIORDY", 0x02, 0x02 }, 698 { "SPIORDY", 0x02, 0x02 },
914 { "OVERRUN", 0x04, 0x04 }, 699 { "OVERRUN", 0x04, 0x04 },
@@ -926,7 +711,7 @@ ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
926 0x4b, regvalue, cur_col, wrap)); 711 0x4b, regvalue, cur_col, wrap));
927} 712}
928 713
929static ahd_reg_parse_entry_t SIMODE0_parse_table[] = { 714static const ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
930 { "ENARBDO", 0x01, 0x01 }, 715 { "ENARBDO", 0x01, 0x01 },
931 { "ENSPIORDY", 0x02, 0x02 }, 716 { "ENSPIORDY", 0x02, 0x02 },
932 { "ENOVERRUN", 0x04, 0x04 }, 717 { "ENOVERRUN", 0x04, 0x04 },
@@ -943,24 +728,24 @@ ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
943 0x4b, regvalue, cur_col, wrap)); 728 0x4b, regvalue, cur_col, wrap));
944} 729}
945 730
946static ahd_reg_parse_entry_t CLRSINT1_parse_table[] = { 731static const ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
947 { "CLRREQINIT", 0x01, 0x01 }, 732 { "CLRARBDO", 0x01, 0x01 },
948 { "CLRSTRB2FAST", 0x02, 0x02 }, 733 { "CLRSPIORDY", 0x02, 0x02 },
949 { "CLRSCSIPERR", 0x04, 0x04 }, 734 { "CLROVERRUN", 0x04, 0x04 },
950 { "CLRBUSFREE", 0x08, 0x08 }, 735 { "CLRIOERR", 0x08, 0x08 },
951 { "CLRSCSIRSTI", 0x20, 0x20 }, 736 { "CLRSELINGO", 0x10, 0x10 },
952 { "CLRATNO", 0x40, 0x40 }, 737 { "CLRSELDI", 0x20, 0x20 },
953 { "CLRSELTIMEO", 0x80, 0x80 } 738 { "CLRSELDO", 0x40, 0x40 }
954}; 739};
955 740
956int 741int
957ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 742ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
958{ 743{
959 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", 744 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
960 0x4c, regvalue, cur_col, wrap)); 745 0x4b, regvalue, cur_col, wrap));
961} 746}
962 747
963static ahd_reg_parse_entry_t SSTAT1_parse_table[] = { 748static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
964 { "REQINIT", 0x01, 0x01 }, 749 { "REQINIT", 0x01, 0x01 },
965 { "STRB2FAST", 0x02, 0x02 }, 750 { "STRB2FAST", 0x02, 0x02 },
966 { "SCSIPERR", 0x04, 0x04 }, 751 { "SCSIPERR", 0x04, 0x04 },
@@ -978,7 +763,24 @@ ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
978 0x4c, regvalue, cur_col, wrap)); 763 0x4c, regvalue, cur_col, wrap));
979} 764}
980 765
981static ahd_reg_parse_entry_t SSTAT2_parse_table[] = { 766static const ahd_reg_parse_entry_t CLRSINT1_parse_table[] = {
767 { "CLRREQINIT", 0x01, 0x01 },
768 { "CLRSTRB2FAST", 0x02, 0x02 },
769 { "CLRSCSIPERR", 0x04, 0x04 },
770 { "CLRBUSFREE", 0x08, 0x08 },
771 { "CLRSCSIRSTI", 0x20, 0x20 },
772 { "CLRATNO", 0x40, 0x40 },
773 { "CLRSELTIMEO", 0x80, 0x80 }
774};
775
776int
777ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
778{
779 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
780 0x4c, regvalue, cur_col, wrap));
781}
782
783static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
982 { "BUSFREE_LQO", 0x40, 0xc0 }, 784 { "BUSFREE_LQO", 0x40, 0xc0 },
983 { "BUSFREE_DFF0", 0x80, 0xc0 }, 785 { "BUSFREE_DFF0", 0x80, 0xc0 },
984 { "BUSFREE_DFF1", 0xc0, 0xc0 }, 786 { "BUSFREE_DFF1", 0xc0, 0xc0 },
@@ -998,20 +800,7 @@ ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
998 0x4d, regvalue, cur_col, wrap)); 800 0x4d, regvalue, cur_col, wrap));
999} 801}
1000 802
1001static ahd_reg_parse_entry_t SIMODE2_parse_table[] = { 803static const ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
1002 { "ENDMADONE", 0x01, 0x01 },
1003 { "ENSDONE", 0x02, 0x02 },
1004 { "ENWIDE_RES", 0x04, 0x04 }
1005};
1006
1007int
1008ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1009{
1010 return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
1011 0x4d, regvalue, cur_col, wrap));
1012}
1013
1014static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
1015 { "CLRDMADONE", 0x01, 0x01 }, 804 { "CLRDMADONE", 0x01, 0x01 },
1016 { "CLRSDONE", 0x02, 0x02 }, 805 { "CLRSDONE", 0x02, 0x02 },
1017 { "CLRWIDE_RES", 0x04, 0x04 }, 806 { "CLRWIDE_RES", 0x04, 0x04 },
@@ -1025,7 +814,7 @@ ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1025 0x4d, regvalue, cur_col, wrap)); 814 0x4d, regvalue, cur_col, wrap));
1026} 815}
1027 816
1028static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { 817static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
1029 { "DTERR", 0x01, 0x01 }, 818 { "DTERR", 0x01, 0x01 },
1030 { "DGFORMERR", 0x02, 0x02 }, 819 { "DGFORMERR", 0x02, 0x02 },
1031 { "CRCERR", 0x04, 0x04 }, 820 { "CRCERR", 0x04, 0x04 },
@@ -1064,7 +853,7 @@ ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap)
1064 0x4f, regvalue, cur_col, wrap)); 853 0x4f, regvalue, cur_col, wrap));
1065} 854}
1066 855
1067static ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { 856static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
1068 { "LQIATNCMD", 0x01, 0x01 }, 857 { "LQIATNCMD", 0x01, 0x01 },
1069 { "LQIATNLQ", 0x02, 0x02 }, 858 { "LQIATNLQ", 0x02, 0x02 },
1070 { "LQIBADLQT", 0x04, 0x04 }, 859 { "LQIBADLQT", 0x04, 0x04 },
@@ -1080,23 +869,7 @@ ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1080 0x50, regvalue, cur_col, wrap)); 869 0x50, regvalue, cur_col, wrap));
1081} 870}
1082 871
1083static ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = { 872static const ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
1084 { "CLRLQIATNCMD", 0x01, 0x01 },
1085 { "CLRLQIATNLQ", 0x02, 0x02 },
1086 { "CLRLQIBADLQT", 0x04, 0x04 },
1087 { "CLRLQICRCT2", 0x08, 0x08 },
1088 { "CLRLQICRCT1", 0x10, 0x10 },
1089 { "CLRLQIATNQAS", 0x20, 0x20 }
1090};
1091
1092int
1093ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1094{
1095 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
1096 0x50, regvalue, cur_col, wrap));
1097}
1098
1099static ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
1100 { "ENLQIATNCMD", 0x01, 0x01 }, 873 { "ENLQIATNCMD", 0x01, 0x01 },
1101 { "ENLQIATNLQ", 0x02, 0x02 }, 874 { "ENLQIATNLQ", 0x02, 0x02 },
1102 { "ENLQIBADLQT", 0x04, 0x04 }, 875 { "ENLQIBADLQT", 0x04, 0x04 },
@@ -1112,7 +885,23 @@ ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1112 0x50, regvalue, cur_col, wrap)); 885 0x50, regvalue, cur_col, wrap));
1113} 886}
1114 887
1115static ahd_reg_parse_entry_t LQIMODE1_parse_table[] = { 888static const ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = {
889 { "CLRLQIATNCMD", 0x01, 0x01 },
890 { "CLRLQIATNLQ", 0x02, 0x02 },
891 { "CLRLQIBADLQT", 0x04, 0x04 },
892 { "CLRLQICRCT2", 0x08, 0x08 },
893 { "CLRLQICRCT1", 0x10, 0x10 },
894 { "CLRLQIATNQAS", 0x20, 0x20 }
895};
896
897int
898ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
899{
900 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
901 0x50, regvalue, cur_col, wrap));
902}
903
904static const ahd_reg_parse_entry_t LQIMODE1_parse_table[] = {
1116 { "ENLQIOVERI_NLQ", 0x01, 0x01 }, 905 { "ENLQIOVERI_NLQ", 0x01, 0x01 },
1117 { "ENLQIOVERI_LQ", 0x02, 0x02 }, 906 { "ENLQIOVERI_LQ", 0x02, 0x02 },
1118 { "ENLQIBADLQI", 0x04, 0x04 }, 907 { "ENLQIBADLQI", 0x04, 0x04 },
@@ -1130,7 +919,7 @@ ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1130 0x51, regvalue, cur_col, wrap)); 919 0x51, regvalue, cur_col, wrap));
1131} 920}
1132 921
1133static ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { 922static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
1134 { "LQIOVERI_NLQ", 0x01, 0x01 }, 923 { "LQIOVERI_NLQ", 0x01, 0x01 },
1135 { "LQIOVERI_LQ", 0x02, 0x02 }, 924 { "LQIOVERI_LQ", 0x02, 0x02 },
1136 { "LQIBADLQI", 0x04, 0x04 }, 925 { "LQIBADLQI", 0x04, 0x04 },
@@ -1148,7 +937,7 @@ ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1148 0x51, regvalue, cur_col, wrap)); 937 0x51, regvalue, cur_col, wrap));
1149} 938}
1150 939
1151static ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = { 940static const ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = {
1152 { "CLRLQIOVERI_NLQ", 0x01, 0x01 }, 941 { "CLRLQIOVERI_NLQ", 0x01, 0x01 },
1153 { "CLRLQIOVERI_LQ", 0x02, 0x02 }, 942 { "CLRLQIOVERI_LQ", 0x02, 0x02 },
1154 { "CLRLQIBADLQI", 0x04, 0x04 }, 943 { "CLRLQIBADLQI", 0x04, 0x04 },
@@ -1166,7 +955,7 @@ ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1166 0x51, regvalue, cur_col, wrap)); 955 0x51, regvalue, cur_col, wrap));
1167} 956}
1168 957
1169static ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { 958static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
1170 { "LQIGSAVAIL", 0x01, 0x01 }, 959 { "LQIGSAVAIL", 0x01, 0x01 },
1171 { "LQISTOPCMD", 0x02, 0x02 }, 960 { "LQISTOPCMD", 0x02, 0x02 },
1172 { "LQISTOPLQ", 0x04, 0x04 }, 961 { "LQISTOPLQ", 0x04, 0x04 },
@@ -1184,7 +973,7 @@ ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1184 0x52, regvalue, cur_col, wrap)); 973 0x52, regvalue, cur_col, wrap));
1185} 974}
1186 975
1187static ahd_reg_parse_entry_t SSTAT3_parse_table[] = { 976static const ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
1188 { "OSRAMPERR", 0x01, 0x01 }, 977 { "OSRAMPERR", 0x01, 0x01 },
1189 { "NTRAMPERR", 0x02, 0x02 } 978 { "NTRAMPERR", 0x02, 0x02 }
1190}; 979};
@@ -1196,7 +985,7 @@ ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1196 0x53, regvalue, cur_col, wrap)); 985 0x53, regvalue, cur_col, wrap));
1197} 986}
1198 987
1199static ahd_reg_parse_entry_t SIMODE3_parse_table[] = { 988static const ahd_reg_parse_entry_t SIMODE3_parse_table[] = {
1200 { "ENOSRAMPERR", 0x01, 0x01 }, 989 { "ENOSRAMPERR", 0x01, 0x01 },
1201 { "ENNTRAMPERR", 0x02, 0x02 } 990 { "ENNTRAMPERR", 0x02, 0x02 }
1202}; 991};
@@ -1208,7 +997,7 @@ ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1208 0x53, regvalue, cur_col, wrap)); 997 0x53, regvalue, cur_col, wrap));
1209} 998}
1210 999
1211static ahd_reg_parse_entry_t CLRSINT3_parse_table[] = { 1000static const ahd_reg_parse_entry_t CLRSINT3_parse_table[] = {
1212 { "CLROSRAMPERR", 0x01, 0x01 }, 1001 { "CLROSRAMPERR", 0x01, 0x01 },
1213 { "CLRNTRAMPERR", 0x02, 0x02 } 1002 { "CLRNTRAMPERR", 0x02, 0x02 }
1214}; 1003};
@@ -1220,7 +1009,7 @@ ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1220 0x53, regvalue, cur_col, wrap)); 1009 0x53, regvalue, cur_col, wrap));
1221} 1010}
1222 1011
1223static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { 1012static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
1224 { "LQOTCRC", 0x01, 0x01 }, 1013 { "LQOTCRC", 0x01, 0x01 },
1225 { "LQOATNPKT", 0x02, 0x02 }, 1014 { "LQOATNPKT", 0x02, 0x02 },
1226 { "LQOATNLQ", 0x04, 0x04 }, 1015 { "LQOATNLQ", 0x04, 0x04 },
@@ -1235,7 +1024,7 @@ ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1235 0x54, regvalue, cur_col, wrap)); 1024 0x54, regvalue, cur_col, wrap));
1236} 1025}
1237 1026
1238static ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = { 1027static const ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = {
1239 { "CLRLQOTCRC", 0x01, 0x01 }, 1028 { "CLRLQOTCRC", 0x01, 0x01 },
1240 { "CLRLQOATNPKT", 0x02, 0x02 }, 1029 { "CLRLQOATNPKT", 0x02, 0x02 },
1241 { "CLRLQOATNLQ", 0x04, 0x04 }, 1030 { "CLRLQOATNLQ", 0x04, 0x04 },
@@ -1250,7 +1039,7 @@ ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1250 0x54, regvalue, cur_col, wrap)); 1039 0x54, regvalue, cur_col, wrap));
1251} 1040}
1252 1041
1253static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = { 1042static const ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
1254 { "ENLQOTCRC", 0x01, 0x01 }, 1043 { "ENLQOTCRC", 0x01, 0x01 },
1255 { "ENLQOATNPKT", 0x02, 0x02 }, 1044 { "ENLQOATNPKT", 0x02, 0x02 },
1256 { "ENLQOATNLQ", 0x04, 0x04 }, 1045 { "ENLQOATNLQ", 0x04, 0x04 },
@@ -1265,7 +1054,7 @@ ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1265 0x54, regvalue, cur_col, wrap)); 1054 0x54, regvalue, cur_col, wrap));
1266} 1055}
1267 1056
1268static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = { 1057static const ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
1269 { "ENLQOPHACHGINPKT", 0x01, 0x01 }, 1058 { "ENLQOPHACHGINPKT", 0x01, 0x01 },
1270 { "ENLQOBUSFREE", 0x02, 0x02 }, 1059 { "ENLQOBUSFREE", 0x02, 0x02 },
1271 { "ENLQOBADQAS", 0x04, 0x04 }, 1060 { "ENLQOBADQAS", 0x04, 0x04 },
@@ -1280,7 +1069,7 @@ ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1280 0x55, regvalue, cur_col, wrap)); 1069 0x55, regvalue, cur_col, wrap));
1281} 1070}
1282 1071
1283static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { 1072static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
1284 { "LQOPHACHGINPKT", 0x01, 0x01 }, 1073 { "LQOPHACHGINPKT", 0x01, 0x01 },
1285 { "LQOBUSFREE", 0x02, 0x02 }, 1074 { "LQOBUSFREE", 0x02, 0x02 },
1286 { "LQOBADQAS", 0x04, 0x04 }, 1075 { "LQOBADQAS", 0x04, 0x04 },
@@ -1295,7 +1084,7 @@ ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1295 0x55, regvalue, cur_col, wrap)); 1084 0x55, regvalue, cur_col, wrap));
1296} 1085}
1297 1086
1298static ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = { 1087static const ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = {
1299 { "CLRLQOPHACHGINPKT", 0x01, 0x01 }, 1088 { "CLRLQOPHACHGINPKT", 0x01, 0x01 },
1300 { "CLRLQOBUSFREE", 0x02, 0x02 }, 1089 { "CLRLQOBUSFREE", 0x02, 0x02 },
1301 { "CLRLQOBADQAS", 0x04, 0x04 }, 1090 { "CLRLQOBADQAS", 0x04, 0x04 },
@@ -1310,7 +1099,7 @@ ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1310 0x55, regvalue, cur_col, wrap)); 1099 0x55, regvalue, cur_col, wrap));
1311} 1100}
1312 1101
1313static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { 1102static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
1314 { "LQOSTOP0", 0x01, 0x01 }, 1103 { "LQOSTOP0", 0x01, 0x01 },
1315 { "LQOPHACHGOUTPKT", 0x02, 0x02 }, 1104 { "LQOPHACHGOUTPKT", 0x02, 0x02 },
1316 { "LQOWAITFIFO", 0x10, 0x10 }, 1105 { "LQOWAITFIFO", 0x10, 0x10 },
@@ -1331,7 +1120,7 @@ ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1331 0x56, regvalue, cur_col, wrap)); 1120 0x56, regvalue, cur_col, wrap));
1332} 1121}
1333 1122
1334static ahd_reg_parse_entry_t SIMODE1_parse_table[] = { 1123static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
1335 { "ENREQINIT", 0x01, 0x01 }, 1124 { "ENREQINIT", 0x01, 0x01 },
1336 { "ENSTRB2FAST", 0x02, 0x02 }, 1125 { "ENSTRB2FAST", 0x02, 0x02 },
1337 { "ENSCSIPERR", 0x04, 0x04 }, 1126 { "ENSCSIPERR", 0x04, 0x04 },
@@ -1356,7 +1145,7 @@ ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1356 0x58, regvalue, cur_col, wrap)); 1145 0x58, regvalue, cur_col, wrap));
1357} 1146}
1358 1147
1359static ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { 1148static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
1360 { "RSTCHN", 0x01, 0x01 }, 1149 { "RSTCHN", 0x01, 0x01 },
1361 { "CLRCHN", 0x02, 0x02 }, 1150 { "CLRCHN", 0x02, 0x02 },
1362 { "CLRSHCNT", 0x04, 0x04 }, 1151 { "CLRSHCNT", 0x04, 0x04 },
@@ -1370,15 +1159,17 @@ ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1370 0x5a, regvalue, cur_col, wrap)); 1159 0x5a, regvalue, cur_col, wrap));
1371} 1160}
1372 1161
1373static ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = { 1162static const ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = {
1374 { "LQONOCHKOVER", 0x01, 0x01 }, 1163 { "LQONOCHKOVER", 0x01, 0x01 },
1164 { "LQONOHOLDLACK", 0x02, 0x02 },
1165 { "LQOBUSETDLY", 0x40, 0x40 },
1375 { "LQOH2A_VERSION", 0x80, 0x80 } 1166 { "LQOH2A_VERSION", 0x80, 0x80 }
1376}; 1167};
1377 1168
1378int 1169int
1379ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1170ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1380{ 1171{
1381 return (ahd_print_register(LQOSCSCTL_parse_table, 2, "LQOSCSCTL", 1172 return (ahd_print_register(LQOSCSCTL_parse_table, 4, "LQOSCSCTL",
1382 0x5a, regvalue, cur_col, wrap)); 1173 0x5a, regvalue, cur_col, wrap));
1383} 1174}
1384 1175
@@ -1389,7 +1180,7 @@ ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1389 0x5a, regvalue, cur_col, wrap)); 1180 0x5a, regvalue, cur_col, wrap));
1390} 1181}
1391 1182
1392static ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = { 1183static const ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = {
1393 { "CLRCFG4TCMD", 0x01, 0x01 }, 1184 { "CLRCFG4TCMD", 0x01, 0x01 },
1394 { "CLRCFG4ICMD", 0x02, 0x02 }, 1185 { "CLRCFG4ICMD", 0x02, 0x02 },
1395 { "CLRCFG4TSTAT", 0x04, 0x04 }, 1186 { "CLRCFG4TSTAT", 0x04, 0x04 },
@@ -1406,7 +1197,7 @@ ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
1406 0x5b, regvalue, cur_col, wrap)); 1197 0x5b, regvalue, cur_col, wrap));
1407} 1198}
1408 1199
1409static ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { 1200static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
1410 { "CFG4TCMD", 0x01, 0x01 }, 1201 { "CFG4TCMD", 0x01, 0x01 },
1411 { "CFG4ICMD", 0x02, 0x02 }, 1202 { "CFG4ICMD", 0x02, 0x02 },
1412 { "CFG4TSTAT", 0x04, 0x04 }, 1203 { "CFG4TSTAT", 0x04, 0x04 },
@@ -1423,14 +1214,7 @@ ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
1423 0x5b, regvalue, cur_col, wrap)); 1214 0x5b, regvalue, cur_col, wrap));
1424} 1215}
1425 1216
1426int 1217static const ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
1427ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1428{
1429 return (ahd_print_register(NULL, 0, "CURRSCB",
1430 0x5c, regvalue, cur_col, wrap));
1431}
1432
1433static ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
1434 { "ENCFG4TCMD", 0x01, 0x01 }, 1218 { "ENCFG4TCMD", 0x01, 0x01 },
1435 { "ENCFG4ICMD", 0x02, 0x02 }, 1219 { "ENCFG4ICMD", 0x02, 0x02 },
1436 { "ENCFG4TSTAT", 0x04, 0x04 }, 1220 { "ENCFG4TSTAT", 0x04, 0x04 },
@@ -1447,7 +1231,14 @@ ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
1447 0x5c, regvalue, cur_col, wrap)); 1231 0x5c, regvalue, cur_col, wrap));
1448} 1232}
1449 1233
1450static ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { 1234int
1235ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1236{
1237 return (ahd_print_register(NULL, 0, "CURRSCB",
1238 0x5c, regvalue, cur_col, wrap));
1239}
1240
1241static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
1451 { "FIFOFREE", 0x01, 0x01 }, 1242 { "FIFOFREE", 0x01, 0x01 },
1452 { "DATAINFIFO", 0x02, 0x02 }, 1243 { "DATAINFIFO", 0x02, 0x02 },
1453 { "DLZERO", 0x04, 0x04 }, 1244 { "DLZERO", 0x04, 0x04 },
@@ -1464,24 +1255,6 @@ ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1464 0x5d, regvalue, cur_col, wrap)); 1255 0x5d, regvalue, cur_col, wrap));
1465} 1256}
1466 1257
1467static ahd_reg_parse_entry_t CRCCONTROL_parse_table[] = {
1468 { "CRCVALCHKEN", 0x40, 0x40 }
1469};
1470
1471int
1472ahd_crccontrol_print(u_int regvalue, u_int *cur_col, u_int wrap)
1473{
1474 return (ahd_print_register(CRCCONTROL_parse_table, 1, "CRCCONTROL",
1475 0x5d, regvalue, cur_col, wrap));
1476}
1477
1478int
1479ahd_dfftag_print(u_int regvalue, u_int *cur_col, u_int wrap)
1480{
1481 return (ahd_print_register(NULL, 0, "DFFTAG",
1482 0x5e, regvalue, cur_col, wrap));
1483}
1484
1485int 1258int
1486ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1259ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1487{ 1260{
@@ -1489,31 +1262,6 @@ ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1489 0x5e, regvalue, cur_col, wrap)); 1262 0x5e, regvalue, cur_col, wrap));
1490} 1263}
1491 1264
1492static ahd_reg_parse_entry_t SCSITEST_parse_table[] = {
1493 { "SEL_TXPLL_DEBUG", 0x04, 0x04 },
1494 { "CNTRTEST", 0x08, 0x08 }
1495};
1496
1497int
1498ahd_scsitest_print(u_int regvalue, u_int *cur_col, u_int wrap)
1499{
1500 return (ahd_print_register(SCSITEST_parse_table, 2, "SCSITEST",
1501 0x5e, regvalue, cur_col, wrap));
1502}
1503
1504static ahd_reg_parse_entry_t IOPDNCTL_parse_table[] = {
1505 { "PDN_DIFFSENSE", 0x01, 0x01 },
1506 { "PDN_IDIST", 0x04, 0x04 },
1507 { "DISABLE_OE", 0x80, 0x80 }
1508};
1509
1510int
1511ahd_iopdnctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1512{
1513 return (ahd_print_register(IOPDNCTL_parse_table, 3, "IOPDNCTL",
1514 0x5f, regvalue, cur_col, wrap));
1515}
1516
1517int 1265int
1518ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1266ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1519{ 1267{
@@ -1529,13 +1277,6 @@ ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1529} 1277}
1530 1278
1531int 1279int
1532ahd_dgrpcrci_print(u_int regvalue, u_int *cur_col, u_int wrap)
1533{
1534 return (ahd_print_register(NULL, 0, "DGRPCRCI",
1535 0x60, regvalue, cur_col, wrap));
1536}
1537
1538int
1539ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap) 1280ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
1540{ 1281{
1541 return (ahd_print_register(NULL, 0, "NEGPERIOD", 1282 return (ahd_print_register(NULL, 0, "NEGPERIOD",
@@ -1543,20 +1284,13 @@ ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
1543} 1284}
1544 1285
1545int 1286int
1546ahd_packcrci_print(u_int regvalue, u_int *cur_col, u_int wrap)
1547{
1548 return (ahd_print_register(NULL, 0, "PACKCRCI",
1549 0x62, regvalue, cur_col, wrap));
1550}
1551
1552int
1553ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap) 1287ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
1554{ 1288{
1555 return (ahd_print_register(NULL, 0, "NEGOFFSET", 1289 return (ahd_print_register(NULL, 0, "NEGOFFSET",
1556 0x62, regvalue, cur_col, wrap)); 1290 0x62, regvalue, cur_col, wrap));
1557} 1291}
1558 1292
1559static ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = { 1293static const ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = {
1560 { "PPROPT_IUT", 0x01, 0x01 }, 1294 { "PPROPT_IUT", 0x01, 0x01 },
1561 { "PPROPT_DT", 0x02, 0x02 }, 1295 { "PPROPT_DT", 0x02, 0x02 },
1562 { "PPROPT_QAS", 0x04, 0x04 }, 1296 { "PPROPT_QAS", 0x04, 0x04 },
@@ -1570,7 +1304,7 @@ ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap)
1570 0x63, regvalue, cur_col, wrap)); 1304 0x63, regvalue, cur_col, wrap));
1571} 1305}
1572 1306
1573static ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = { 1307static const ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = {
1574 { "WIDEXFER", 0x01, 0x01 }, 1308 { "WIDEXFER", 0x01, 0x01 },
1575 { "ENAUTOATNO", 0x02, 0x02 }, 1309 { "ENAUTOATNO", 0x02, 0x02 },
1576 { "ENAUTOATNI", 0x04, 0x04 }, 1310 { "ENAUTOATNI", 0x04, 0x04 },
@@ -1601,20 +1335,21 @@ ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1601 0x66, regvalue, cur_col, wrap)); 1335 0x66, regvalue, cur_col, wrap));
1602} 1336}
1603 1337
1604static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = { 1338static const ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
1605 { "LSTSGCLRDIS", 0x01, 0x01 }, 1339 { "LSTSGCLRDIS", 0x01, 0x01 },
1606 { "SHVALIDSTDIS", 0x02, 0x02 }, 1340 { "SHVALIDSTDIS", 0x02, 0x02 },
1607 { "DFFACTCLR", 0x04, 0x04 }, 1341 { "DFFACTCLR", 0x04, 0x04 },
1608 { "SDONEMSKDIS", 0x08, 0x08 }, 1342 { "SDONEMSKDIS", 0x08, 0x08 },
1609 { "WIDERESEN", 0x10, 0x10 }, 1343 { "WIDERESEN", 0x10, 0x10 },
1610 { "CURRFIFODEF", 0x20, 0x20 }, 1344 { "CURRFIFODEF", 0x20, 0x20 },
1611 { "STSELSKIDDIS", 0x40, 0x40 } 1345 { "STSELSKIDDIS", 0x40, 0x40 },
1346 { "BIDICHKDIS", 0x80, 0x80 }
1612}; 1347};
1613 1348
1614int 1349int
1615ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap) 1350ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
1616{ 1351{
1617 return (ahd_print_register(SCSCHKN_parse_table, 7, "SCSCHKN", 1352 return (ahd_print_register(SCSCHKN_parse_table, 8, "SCSCHKN",
1618 0x66, regvalue, cur_col, wrap)); 1353 0x66, regvalue, cur_col, wrap));
1619} 1354}
1620 1355
@@ -1625,23 +1360,6 @@ ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1625 0x67, regvalue, cur_col, wrap)); 1360 0x67, regvalue, cur_col, wrap));
1626} 1361}
1627 1362
1628static ahd_reg_parse_entry_t PLL960CTL0_parse_table[] = {
1629 { "PLL_ENFBM", 0x01, 0x01 },
1630 { "PLL_DLPF", 0x02, 0x02 },
1631 { "PLL_ENLPF", 0x04, 0x04 },
1632 { "PLL_ENLUD", 0x08, 0x08 },
1633 { "PLL_NS", 0x30, 0x30 },
1634 { "PLL_PWDN", 0x40, 0x40 },
1635 { "PLL_VCOSEL", 0x80, 0x80 }
1636};
1637
1638int
1639ahd_pll960ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1640{
1641 return (ahd_print_register(PLL960CTL0_parse_table, 7, "PLL960CTL0",
1642 0x68, regvalue, cur_col, wrap));
1643}
1644
1645int 1363int
1646ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1364ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1647{ 1365{
@@ -1656,33 +1374,6 @@ ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1656 0x69, regvalue, cur_col, wrap)); 1374 0x69, regvalue, cur_col, wrap));
1657} 1375}
1658 1376
1659static ahd_reg_parse_entry_t PLL960CTL1_parse_table[] = {
1660 { "PLL_RST", 0x01, 0x01 },
1661 { "PLL_CNTCLR", 0x40, 0x40 },
1662 { "PLL_CNTEN", 0x80, 0x80 }
1663};
1664
1665int
1666ahd_pll960ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1667{
1668 return (ahd_print_register(PLL960CTL1_parse_table, 3, "PLL960CTL1",
1669 0x69, regvalue, cur_col, wrap));
1670}
1671
1672int
1673ahd_pll960cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1674{
1675 return (ahd_print_register(NULL, 0, "PLL960CNT0",
1676 0x6a, regvalue, cur_col, wrap));
1677}
1678
1679int
1680ahd_xsig_print(u_int regvalue, u_int *cur_col, u_int wrap)
1681{
1682 return (ahd_print_register(NULL, 0, "XSIG",
1683 0x6a, regvalue, cur_col, wrap));
1684}
1685
1686int 1377int
1687ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1378ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1688{ 1379{
@@ -1690,57 +1381,6 @@ ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1690 0x6b, regvalue, cur_col, wrap)); 1381 0x6b, regvalue, cur_col, wrap));
1691} 1382}
1692 1383
1693static ahd_reg_parse_entry_t PLL400CTL0_parse_table[] = {
1694 { "PLL_ENFBM", 0x01, 0x01 },
1695 { "PLL_DLPF", 0x02, 0x02 },
1696 { "PLL_ENLPF", 0x04, 0x04 },
1697 { "PLL_ENLUD", 0x08, 0x08 },
1698 { "PLL_NS", 0x30, 0x30 },
1699 { "PLL_PWDN", 0x40, 0x40 },
1700 { "PLL_VCOSEL", 0x80, 0x80 }
1701};
1702
1703int
1704ahd_pll400ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1705{
1706 return (ahd_print_register(PLL400CTL0_parse_table, 7, "PLL400CTL0",
1707 0x6c, regvalue, cur_col, wrap));
1708}
1709
1710int
1711ahd_fairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
1712{
1713 return (ahd_print_register(NULL, 0, "FAIRNESS",
1714 0x6c, regvalue, cur_col, wrap));
1715}
1716
1717static ahd_reg_parse_entry_t PLL400CTL1_parse_table[] = {
1718 { "PLL_RST", 0x01, 0x01 },
1719 { "PLL_CNTCLR", 0x40, 0x40 },
1720 { "PLL_CNTEN", 0x80, 0x80 }
1721};
1722
1723int
1724ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1725{
1726 return (ahd_print_register(PLL400CTL1_parse_table, 3, "PLL400CTL1",
1727 0x6d, regvalue, cur_col, wrap));
1728}
1729
1730int
1731ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
1732{
1733 return (ahd_print_register(NULL, 0, "UNFAIRNESS",
1734 0x6e, regvalue, cur_col, wrap));
1735}
1736
1737int
1738ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1739{
1740 return (ahd_print_register(NULL, 0, "PLL400CNT0",
1741 0x6e, regvalue, cur_col, wrap));
1742}
1743
1744int 1384int
1745ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1385ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1746{ 1386{
@@ -1748,31 +1388,6 @@ ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1748 0x70, regvalue, cur_col, wrap)); 1388 0x70, regvalue, cur_col, wrap));
1749} 1389}
1750 1390
1751static ahd_reg_parse_entry_t PLLDELAY_parse_table[] = {
1752 { "SPLIT_DROP_REQ", 0x80, 0x80 }
1753};
1754
1755int
1756ahd_plldelay_print(u_int regvalue, u_int *cur_col, u_int wrap)
1757{
1758 return (ahd_print_register(PLLDELAY_parse_table, 1, "PLLDELAY",
1759 0x70, regvalue, cur_col, wrap));
1760}
1761
1762int
1763ahd_hodmaadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1764{
1765 return (ahd_print_register(NULL, 0, "HODMAADR",
1766 0x70, regvalue, cur_col, wrap));
1767}
1768
1769int
1770ahd_hodmacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1771{
1772 return (ahd_print_register(NULL, 0, "HODMACNT",
1773 0x78, regvalue, cur_col, wrap));
1774}
1775
1776int 1391int
1777ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1392ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1778{ 1393{
@@ -1781,10 +1396,10 @@ ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1781} 1396}
1782 1397
1783int 1398int
1784ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap) 1399ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1785{ 1400{
1786 return (ahd_print_register(NULL, 0, "HODMAEN", 1401 return (ahd_print_register(NULL, 0, "SGHADDR",
1787 0x7a, regvalue, cur_col, wrap)); 1402 0x7c, regvalue, cur_col, wrap));
1788} 1403}
1789 1404
1790int 1405int
@@ -1795,10 +1410,10 @@ ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1795} 1410}
1796 1411
1797int 1412int
1798ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1413ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1799{ 1414{
1800 return (ahd_print_register(NULL, 0, "SGHADDR", 1415 return (ahd_print_register(NULL, 0, "SGHCNT",
1801 0x7c, regvalue, cur_col, wrap)); 1416 0x84, regvalue, cur_col, wrap));
1802} 1417}
1803 1418
1804int 1419int
@@ -1808,14 +1423,7 @@ ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1808 0x84, regvalue, cur_col, wrap)); 1423 0x84, regvalue, cur_col, wrap));
1809} 1424}
1810 1425
1811int 1426static const ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1812ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1813{
1814 return (ahd_print_register(NULL, 0, "SGHCNT",
1815 0x84, regvalue, cur_col, wrap));
1816}
1817
1818static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1819 { "WR_DFTHRSH_MIN", 0x00, 0x70 }, 1427 { "WR_DFTHRSH_MIN", 0x00, 0x70 },
1820 { "RD_DFTHRSH_MIN", 0x00, 0x07 }, 1428 { "RD_DFTHRSH_MIN", 0x00, 0x07 },
1821 { "RD_DFTHRSH_25", 0x01, 0x07 }, 1429 { "RD_DFTHRSH_25", 0x01, 0x07 },
@@ -1843,209 +1451,7 @@ ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1843 0x88, regvalue, cur_col, wrap)); 1451 0x88, regvalue, cur_col, wrap));
1844} 1452}
1845 1453
1846int 1454static const ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
1847ahd_romaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1848{
1849 return (ahd_print_register(NULL, 0, "ROMADDR",
1850 0x8a, regvalue, cur_col, wrap));
1851}
1852
1853static ahd_reg_parse_entry_t ROMCNTRL_parse_table[] = {
1854 { "RDY", 0x01, 0x01 },
1855 { "REPEAT", 0x02, 0x02 },
1856 { "ROMSPD", 0x18, 0x18 },
1857 { "ROMOP", 0xe0, 0xe0 }
1858};
1859
1860int
1861ahd_romcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1862{
1863 return (ahd_print_register(ROMCNTRL_parse_table, 4, "ROMCNTRL",
1864 0x8d, regvalue, cur_col, wrap));
1865}
1866
1867int
1868ahd_romdata_print(u_int regvalue, u_int *cur_col, u_int wrap)
1869{
1870 return (ahd_print_register(NULL, 0, "ROMDATA",
1871 0x8e, regvalue, cur_col, wrap));
1872}
1873
1874static ahd_reg_parse_entry_t CMCRXMSG0_parse_table[] = {
1875 { "CFNUM", 0x07, 0x07 },
1876 { "CDNUM", 0xf8, 0xf8 }
1877};
1878
1879int
1880ahd_cmcrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1881{
1882 return (ahd_print_register(CMCRXMSG0_parse_table, 2, "CMCRXMSG0",
1883 0x90, regvalue, cur_col, wrap));
1884}
1885
1886static ahd_reg_parse_entry_t ROENABLE_parse_table[] = {
1887 { "DCH0ROEN", 0x01, 0x01 },
1888 { "DCH1ROEN", 0x02, 0x02 },
1889 { "SGROEN", 0x04, 0x04 },
1890 { "CMCROEN", 0x08, 0x08 },
1891 { "OVLYROEN", 0x10, 0x10 },
1892 { "MSIROEN", 0x20, 0x20 }
1893};
1894
1895int
1896ahd_roenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
1897{
1898 return (ahd_print_register(ROENABLE_parse_table, 6, "ROENABLE",
1899 0x90, regvalue, cur_col, wrap));
1900}
1901
1902static ahd_reg_parse_entry_t OVLYRXMSG0_parse_table[] = {
1903 { "CFNUM", 0x07, 0x07 },
1904 { "CDNUM", 0xf8, 0xf8 }
1905};
1906
1907int
1908ahd_ovlyrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1909{
1910 return (ahd_print_register(OVLYRXMSG0_parse_table, 2, "OVLYRXMSG0",
1911 0x90, regvalue, cur_col, wrap));
1912}
1913
1914static ahd_reg_parse_entry_t DCHRXMSG0_parse_table[] = {
1915 { "CFNUM", 0x07, 0x07 },
1916 { "CDNUM", 0xf8, 0xf8 }
1917};
1918
1919int
1920ahd_dchrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1921{
1922 return (ahd_print_register(DCHRXMSG0_parse_table, 2, "DCHRXMSG0",
1923 0x90, regvalue, cur_col, wrap));
1924}
1925
1926static ahd_reg_parse_entry_t OVLYRXMSG1_parse_table[] = {
1927 { "CBNUM", 0xff, 0xff }
1928};
1929
1930int
1931ahd_ovlyrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1932{
1933 return (ahd_print_register(OVLYRXMSG1_parse_table, 1, "OVLYRXMSG1",
1934 0x91, regvalue, cur_col, wrap));
1935}
1936
1937static ahd_reg_parse_entry_t NSENABLE_parse_table[] = {
1938 { "DCH0NSEN", 0x01, 0x01 },
1939 { "DCH1NSEN", 0x02, 0x02 },
1940 { "SGNSEN", 0x04, 0x04 },
1941 { "CMCNSEN", 0x08, 0x08 },
1942 { "OVLYNSEN", 0x10, 0x10 },
1943 { "MSINSEN", 0x20, 0x20 }
1944};
1945
1946int
1947ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
1948{
1949 return (ahd_print_register(NSENABLE_parse_table, 6, "NSENABLE",
1950 0x91, regvalue, cur_col, wrap));
1951}
1952
1953static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = {
1954 { "CBNUM", 0xff, 0xff }
1955};
1956
1957int
1958ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1959{
1960 return (ahd_print_register(CMCRXMSG1_parse_table, 1, "CMCRXMSG1",
1961 0x91, regvalue, cur_col, wrap));
1962}
1963
1964static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
1965 { "CBNUM", 0xff, 0xff }
1966};
1967
1968int
1969ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1970{
1971 return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
1972 0x91, regvalue, cur_col, wrap));
1973}
1974
1975static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = {
1976 { "MINDEX", 0xff, 0xff }
1977};
1978
1979int
1980ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1981{
1982 return (ahd_print_register(DCHRXMSG2_parse_table, 1, "DCHRXMSG2",
1983 0x92, regvalue, cur_col, wrap));
1984}
1985
1986static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = {
1987 { "MINDEX", 0xff, 0xff }
1988};
1989
1990int
1991ahd_cmcrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1992{
1993 return (ahd_print_register(CMCRXMSG2_parse_table, 1, "CMCRXMSG2",
1994 0x92, regvalue, cur_col, wrap));
1995}
1996
1997int
1998ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap)
1999{
2000 return (ahd_print_register(NULL, 0, "OST",
2001 0x92, regvalue, cur_col, wrap));
2002}
2003
2004static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
2005 { "MINDEX", 0xff, 0xff }
2006};
2007
2008int
2009ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2010{
2011 return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
2012 0x92, regvalue, cur_col, wrap));
2013}
2014
2015static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = {
2016 { "MCLASS", 0x0f, 0x0f }
2017};
2018
2019int
2020ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2021{
2022 return (ahd_print_register(DCHRXMSG3_parse_table, 1, "DCHRXMSG3",
2023 0x93, regvalue, cur_col, wrap));
2024}
2025
2026static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
2027 { "MCLASS", 0x0f, 0x0f }
2028};
2029
2030int
2031ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2032{
2033 return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
2034 0x93, regvalue, cur_col, wrap));
2035}
2036
2037static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = {
2038 { "MCLASS", 0x0f, 0x0f }
2039};
2040
2041int
2042ahd_cmcrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2043{
2044 return (ahd_print_register(CMCRXMSG3_parse_table, 1, "CMCRXMSG3",
2045 0x93, regvalue, cur_col, wrap));
2046}
2047
2048static ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
2049 { "CMPABCDIS", 0x01, 0x01 }, 1455 { "CMPABCDIS", 0x01, 0x01 },
2050 { "TSCSERREN", 0x02, 0x02 }, 1456 { "TSCSERREN", 0x02, 0x02 },
2051 { "SRSPDPEEN", 0x04, 0x04 }, 1457 { "SRSPDPEEN", 0x04, 0x04 },
@@ -2062,46 +1468,7 @@ ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2062 0x93, regvalue, cur_col, wrap)); 1468 0x93, regvalue, cur_col, wrap));
2063} 1469}
2064 1470
2065int 1471static const ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
2066ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2067{
2068 return (ahd_print_register(NULL, 0, "OVLYSEQBCNT",
2069 0x94, regvalue, cur_col, wrap));
2070}
2071
2072int
2073ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2074{
2075 return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
2076 0x94, regvalue, cur_col, wrap));
2077}
2078
2079int
2080ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2081{
2082 return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
2083 0x94, regvalue, cur_col, wrap));
2084}
2085
2086static ahd_reg_parse_entry_t CMCSPLTSTAT0_parse_table[] = {
2087 { "RXSPLTRSP", 0x01, 0x01 },
2088 { "RXSCEMSG", 0x02, 0x02 },
2089 { "RXOVRUN", 0x04, 0x04 },
2090 { "CNTNOTCMPLT", 0x08, 0x08 },
2091 { "SCDATBUCKET", 0x10, 0x10 },
2092 { "SCADERR", 0x20, 0x20 },
2093 { "SCBCERR", 0x40, 0x40 },
2094 { "STAETERM", 0x80, 0x80 }
2095};
2096
2097int
2098ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2099{
2100 return (ahd_print_register(CMCSPLTSTAT0_parse_table, 8, "CMCSPLTSTAT0",
2101 0x96, regvalue, cur_col, wrap));
2102}
2103
2104static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
2105 { "RXSPLTRSP", 0x01, 0x01 }, 1472 { "RXSPLTRSP", 0x01, 0x01 },
2106 { "RXSCEMSG", 0x02, 0x02 }, 1473 { "RXSCEMSG", 0x02, 0x02 },
2107 { "RXOVRUN", 0x04, 0x04 }, 1474 { "RXOVRUN", 0x04, 0x04 },
@@ -2119,47 +1486,7 @@ ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2119 0x96, regvalue, cur_col, wrap)); 1486 0x96, regvalue, cur_col, wrap));
2120} 1487}
2121 1488
2122static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = { 1489static const ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
2123 { "RXSPLTRSP", 0x01, 0x01 },
2124 { "RXSCEMSG", 0x02, 0x02 },
2125 { "RXOVRUN", 0x04, 0x04 },
2126 { "CNTNOTCMPLT", 0x08, 0x08 },
2127 { "SCDATBUCKET", 0x10, 0x10 },
2128 { "SCADERR", 0x20, 0x20 },
2129 { "SCBCERR", 0x40, 0x40 },
2130 { "STAETERM", 0x80, 0x80 }
2131};
2132
2133int
2134ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2135{
2136 return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
2137 0x96, regvalue, cur_col, wrap));
2138}
2139
2140static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = {
2141 { "RXDATABUCKET", 0x01, 0x01 }
2142};
2143
2144int
2145ahd_cmcspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2146{
2147 return (ahd_print_register(CMCSPLTSTAT1_parse_table, 1, "CMCSPLTSTAT1",
2148 0x97, regvalue, cur_col, wrap));
2149}
2150
2151static ahd_reg_parse_entry_t OVLYSPLTSTAT1_parse_table[] = {
2152 { "RXDATABUCKET", 0x01, 0x01 }
2153};
2154
2155int
2156ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2157{
2158 return (ahd_print_register(OVLYSPLTSTAT1_parse_table, 1, "OVLYSPLTSTAT1",
2159 0x97, regvalue, cur_col, wrap));
2160}
2161
2162static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
2163 { "RXDATABUCKET", 0x01, 0x01 } 1490 { "RXDATABUCKET", 0x01, 0x01 }
2164}; 1491};
2165 1492
@@ -2170,139 +1497,7 @@ ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2170 0x97, regvalue, cur_col, wrap)); 1497 0x97, regvalue, cur_col, wrap));
2171} 1498}
2172 1499
2173static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = { 1500static const ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
2174 { "CFNUM", 0x07, 0x07 },
2175 { "CDNUM", 0xf8, 0xf8 }
2176};
2177
2178int
2179ahd_sgrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2180{
2181 return (ahd_print_register(SGRXMSG0_parse_table, 2, "SGRXMSG0",
2182 0x98, regvalue, cur_col, wrap));
2183}
2184
2185static ahd_reg_parse_entry_t SLVSPLTOUTADR0_parse_table[] = {
2186 { "LOWER_ADDR", 0x7f, 0x7f }
2187};
2188
2189int
2190ahd_slvspltoutadr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2191{
2192 return (ahd_print_register(SLVSPLTOUTADR0_parse_table, 1, "SLVSPLTOUTADR0",
2193 0x98, regvalue, cur_col, wrap));
2194}
2195
2196static ahd_reg_parse_entry_t SGRXMSG1_parse_table[] = {
2197 { "CBNUM", 0xff, 0xff }
2198};
2199
2200int
2201ahd_sgrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2202{
2203 return (ahd_print_register(SGRXMSG1_parse_table, 1, "SGRXMSG1",
2204 0x99, regvalue, cur_col, wrap));
2205}
2206
2207static ahd_reg_parse_entry_t SLVSPLTOUTADR1_parse_table[] = {
2208 { "REQ_FNUM", 0x07, 0x07 },
2209 { "REQ_DNUM", 0xf8, 0xf8 }
2210};
2211
2212int
2213ahd_slvspltoutadr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2214{
2215 return (ahd_print_register(SLVSPLTOUTADR1_parse_table, 2, "SLVSPLTOUTADR1",
2216 0x99, regvalue, cur_col, wrap));
2217}
2218
2219static ahd_reg_parse_entry_t SGRXMSG2_parse_table[] = {
2220 { "MINDEX", 0xff, 0xff }
2221};
2222
2223int
2224ahd_sgrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2225{
2226 return (ahd_print_register(SGRXMSG2_parse_table, 1, "SGRXMSG2",
2227 0x9a, regvalue, cur_col, wrap));
2228}
2229
2230static ahd_reg_parse_entry_t SLVSPLTOUTADR2_parse_table[] = {
2231 { "REQ_BNUM", 0xff, 0xff }
2232};
2233
2234int
2235ahd_slvspltoutadr2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2236{
2237 return (ahd_print_register(SLVSPLTOUTADR2_parse_table, 1, "SLVSPLTOUTADR2",
2238 0x9a, regvalue, cur_col, wrap));
2239}
2240
2241static ahd_reg_parse_entry_t SGRXMSG3_parse_table[] = {
2242 { "MCLASS", 0x0f, 0x0f }
2243};
2244
2245int
2246ahd_sgrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2247{
2248 return (ahd_print_register(SGRXMSG3_parse_table, 1, "SGRXMSG3",
2249 0x9b, regvalue, cur_col, wrap));
2250}
2251
2252static ahd_reg_parse_entry_t SLVSPLTOUTADR3_parse_table[] = {
2253 { "RLXORD", 0x10, 0x10 },
2254 { "TAG_NUM", 0x1f, 0x1f }
2255};
2256
2257int
2258ahd_slvspltoutadr3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2259{
2260 return (ahd_print_register(SLVSPLTOUTADR3_parse_table, 2, "SLVSPLTOUTADR3",
2261 0x9b, regvalue, cur_col, wrap));
2262}
2263
2264int
2265ahd_sgseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2266{
2267 return (ahd_print_register(NULL, 0, "SGSEQBCNT",
2268 0x9c, regvalue, cur_col, wrap));
2269}
2270
2271static ahd_reg_parse_entry_t SLVSPLTOUTATTR0_parse_table[] = {
2272 { "LOWER_BCNT", 0xff, 0xff }
2273};
2274
2275int
2276ahd_slvspltoutattr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2277{
2278 return (ahd_print_register(SLVSPLTOUTATTR0_parse_table, 1, "SLVSPLTOUTATTR0",
2279 0x9c, regvalue, cur_col, wrap));
2280}
2281
2282static ahd_reg_parse_entry_t SLVSPLTOUTATTR1_parse_table[] = {
2283 { "CMPLT_FNUM", 0x07, 0x07 },
2284 { "CMPLT_DNUM", 0xf8, 0xf8 }
2285};
2286
2287int
2288ahd_slvspltoutattr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2289{
2290 return (ahd_print_register(SLVSPLTOUTATTR1_parse_table, 2, "SLVSPLTOUTATTR1",
2291 0x9d, regvalue, cur_col, wrap));
2292}
2293
2294static ahd_reg_parse_entry_t SLVSPLTOUTATTR2_parse_table[] = {
2295 { "CMPLT_BNUM", 0xff, 0xff }
2296};
2297
2298int
2299ahd_slvspltoutattr2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2300{
2301 return (ahd_print_register(SLVSPLTOUTATTR2_parse_table, 1, "SLVSPLTOUTATTR2",
2302 0x9e, regvalue, cur_col, wrap));
2303}
2304
2305static ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
2306 { "RXSPLTRSP", 0x01, 0x01 }, 1501 { "RXSPLTRSP", 0x01, 0x01 },
2307 { "RXSCEMSG", 0x02, 0x02 }, 1502 { "RXSCEMSG", 0x02, 0x02 },
2308 { "RXOVRUN", 0x04, 0x04 }, 1503 { "RXOVRUN", 0x04, 0x04 },
@@ -2320,7 +1515,7 @@ ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2320 0x9e, regvalue, cur_col, wrap)); 1515 0x9e, regvalue, cur_col, wrap));
2321} 1516}
2322 1517
2323static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = { 1518static const ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
2324 { "RXDATABUCKET", 0x01, 0x01 } 1519 { "RXDATABUCKET", 0x01, 0x01 }
2325}; 1520};
2326 1521
@@ -2331,19 +1526,7 @@ ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2331 0x9f, regvalue, cur_col, wrap)); 1526 0x9f, regvalue, cur_col, wrap));
2332} 1527}
2333 1528
2334static ahd_reg_parse_entry_t SFUNCT_parse_table[] = { 1529static const ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
2335 { "TEST_NUM", 0x0f, 0x0f },
2336 { "TEST_GROUP", 0xf0, 0xf0 }
2337};
2338
2339int
2340ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
2341{
2342 return (ahd_print_register(SFUNCT_parse_table, 2, "SFUNCT",
2343 0x9f, regvalue, cur_col, wrap));
2344}
2345
2346static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
2347 { "DPR", 0x01, 0x01 }, 1530 { "DPR", 0x01, 0x01 },
2348 { "TWATERR", 0x02, 0x02 }, 1531 { "TWATERR", 0x02, 0x02 },
2349 { "RDPERR", 0x04, 0x04 }, 1532 { "RDPERR", 0x04, 0x04 },
@@ -2368,83 +1551,6 @@ ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2368 0xa0, regvalue, cur_col, wrap)); 1551 0xa0, regvalue, cur_col, wrap));
2369} 1552}
2370 1553
2371static ahd_reg_parse_entry_t DF1PCISTAT_parse_table[] = {
2372 { "DPR", 0x01, 0x01 },
2373 { "TWATERR", 0x02, 0x02 },
2374 { "RDPERR", 0x04, 0x04 },
2375 { "SCAAPERR", 0x08, 0x08 },
2376 { "RTA", 0x10, 0x10 },
2377 { "RMA", 0x20, 0x20 },
2378 { "SSE", 0x40, 0x40 },
2379 { "DPE", 0x80, 0x80 }
2380};
2381
2382int
2383ahd_df1pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2384{
2385 return (ahd_print_register(DF1PCISTAT_parse_table, 8, "DF1PCISTAT",
2386 0xa1, regvalue, cur_col, wrap));
2387}
2388
2389static ahd_reg_parse_entry_t SGPCISTAT_parse_table[] = {
2390 { "DPR", 0x01, 0x01 },
2391 { "RDPERR", 0x04, 0x04 },
2392 { "SCAAPERR", 0x08, 0x08 },
2393 { "RTA", 0x10, 0x10 },
2394 { "RMA", 0x20, 0x20 },
2395 { "SSE", 0x40, 0x40 },
2396 { "DPE", 0x80, 0x80 }
2397};
2398
2399int
2400ahd_sgpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2401{
2402 return (ahd_print_register(SGPCISTAT_parse_table, 7, "SGPCISTAT",
2403 0xa2, regvalue, cur_col, wrap));
2404}
2405
2406int
2407ahd_reg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2408{
2409 return (ahd_print_register(NULL, 0, "REG1",
2410 0xa2, regvalue, cur_col, wrap));
2411}
2412
2413static ahd_reg_parse_entry_t CMCPCISTAT_parse_table[] = {
2414 { "DPR", 0x01, 0x01 },
2415 { "TWATERR", 0x02, 0x02 },
2416 { "RDPERR", 0x04, 0x04 },
2417 { "SCAAPERR", 0x08, 0x08 },
2418 { "RTA", 0x10, 0x10 },
2419 { "RMA", 0x20, 0x20 },
2420 { "SSE", 0x40, 0x40 },
2421 { "DPE", 0x80, 0x80 }
2422};
2423
2424int
2425ahd_cmcpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2426{
2427 return (ahd_print_register(CMCPCISTAT_parse_table, 8, "CMCPCISTAT",
2428 0xa3, regvalue, cur_col, wrap));
2429}
2430
2431static ahd_reg_parse_entry_t OVLYPCISTAT_parse_table[] = {
2432 { "DPR", 0x01, 0x01 },
2433 { "RDPERR", 0x04, 0x04 },
2434 { "SCAAPERR", 0x08, 0x08 },
2435 { "RTA", 0x10, 0x10 },
2436 { "RMA", 0x20, 0x20 },
2437 { "SSE", 0x40, 0x40 },
2438 { "DPE", 0x80, 0x80 }
2439};
2440
2441int
2442ahd_ovlypcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2443{
2444 return (ahd_print_register(OVLYPCISTAT_parse_table, 7, "OVLYPCISTAT",
2445 0xa4, regvalue, cur_col, wrap));
2446}
2447
2448int 1554int
2449ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1555ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2450{ 1556{
@@ -2452,7 +1558,7 @@ ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2452 0xa4, regvalue, cur_col, wrap)); 1558 0xa4, regvalue, cur_col, wrap));
2453} 1559}
2454 1560
2455static ahd_reg_parse_entry_t SG_STATE_parse_table[] = { 1561static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
2456 { "SEGS_AVAIL", 0x01, 0x01 }, 1562 { "SEGS_AVAIL", 0x01, 0x01 },
2457 { "LOADING_NEEDED", 0x02, 0x02 }, 1563 { "LOADING_NEEDED", 0x02, 0x02 },
2458 { "FETCH_INPROG", 0x04, 0x04 } 1564 { "FETCH_INPROG", 0x04, 0x04 }
@@ -2465,23 +1571,7 @@ ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
2465 0xa6, regvalue, cur_col, wrap)); 1571 0xa6, regvalue, cur_col, wrap));
2466} 1572}
2467 1573
2468static ahd_reg_parse_entry_t MSIPCISTAT_parse_table[] = { 1574static const ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
2469 { "DPR", 0x01, 0x01 },
2470 { "TWATERR", 0x02, 0x02 },
2471 { "CLRPENDMSI", 0x08, 0x08 },
2472 { "RTA", 0x10, 0x10 },
2473 { "RMA", 0x20, 0x20 },
2474 { "SSE", 0x40, 0x40 }
2475};
2476
2477int
2478ahd_msipcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2479{
2480 return (ahd_print_register(MSIPCISTAT_parse_table, 6, "MSIPCISTAT",
2481 0xa6, regvalue, cur_col, wrap));
2482}
2483
2484static ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
2485 { "TWATERR", 0x02, 0x02 }, 1575 { "TWATERR", 0x02, 0x02 },
2486 { "STA", 0x08, 0x08 }, 1576 { "STA", 0x08, 0x08 },
2487 { "SSE", 0x40, 0x40 }, 1577 { "SSE", 0x40, 0x40 },
@@ -2496,27 +1586,13 @@ ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2496} 1586}
2497 1587
2498int 1588int
2499ahd_data_count_odd_print(u_int regvalue, u_int *cur_col, u_int wrap)
2500{
2501 return (ahd_print_register(NULL, 0, "DATA_COUNT_ODD",
2502 0xa7, regvalue, cur_col, wrap));
2503}
2504
2505int
2506ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1589ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2507{ 1590{
2508 return (ahd_print_register(NULL, 0, "SCBPTR", 1591 return (ahd_print_register(NULL, 0, "SCBPTR",
2509 0xa8, regvalue, cur_col, wrap)); 1592 0xa8, regvalue, cur_col, wrap));
2510} 1593}
2511 1594
2512int 1595static const ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
2513ahd_ccscbacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2514{
2515 return (ahd_print_register(NULL, 0, "CCSCBACNT",
2516 0xab, regvalue, cur_col, wrap));
2517}
2518
2519static ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
2520 { "SCBPTR_OFF", 0x07, 0x07 }, 1596 { "SCBPTR_OFF", 0x07, 0x07 },
2521 { "SCBPTR_ADDR", 0x38, 0x38 }, 1597 { "SCBPTR_ADDR", 0x38, 0x38 },
2522 { "AUSCBPTR_EN", 0x80, 0x80 } 1598 { "AUSCBPTR_EN", 0x80, 0x80 }
@@ -2537,36 +1613,13 @@ ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2537} 1613}
2538 1614
2539int 1615int
2540ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
2541{
2542 return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
2543 0xac, regvalue, cur_col, wrap));
2544}
2545
2546int
2547ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1616ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2548{ 1617{
2549 return (ahd_print_register(NULL, 0, "CCSCBADDR", 1618 return (ahd_print_register(NULL, 0, "CCSCBADDR",
2550 0xac, regvalue, cur_col, wrap)); 1619 0xac, regvalue, cur_col, wrap));
2551} 1620}
2552 1621
2553static ahd_reg_parse_entry_t CMC_RAMBIST_parse_table[] = { 1622static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
2554 { "CMC_BUFFER_BIST_EN", 0x01, 0x01 },
2555 { "CMC_BUFFER_BIST_FAIL",0x02, 0x02 },
2556 { "SG_BIST_EN", 0x10, 0x10 },
2557 { "SG_BIST_FAIL", 0x20, 0x20 },
2558 { "SCBRAMBIST_FAIL", 0x40, 0x40 },
2559 { "SG_ELEMENT_SIZE", 0x80, 0x80 }
2560};
2561
2562int
2563ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap)
2564{
2565 return (ahd_print_register(CMC_RAMBIST_parse_table, 6, "CMC_RAMBIST",
2566 0xad, regvalue, cur_col, wrap));
2567}
2568
2569static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
2570 { "CCSCBRESET", 0x01, 0x01 }, 1623 { "CCSCBRESET", 0x01, 0x01 },
2571 { "CCSCBDIR", 0x04, 0x04 }, 1624 { "CCSCBDIR", 0x04, 0x04 },
2572 { "CCSCBEN", 0x08, 0x08 }, 1625 { "CCSCBEN", 0x08, 0x08 },
@@ -2582,7 +1635,7 @@ ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2582 0xad, regvalue, cur_col, wrap)); 1635 0xad, regvalue, cur_col, wrap));
2583} 1636}
2584 1637
2585static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = { 1638static const ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
2586 { "CCSGRESET", 0x01, 0x01 }, 1639 { "CCSGRESET", 0x01, 0x01 },
2587 { "SG_FETCH_REQ", 0x02, 0x02 }, 1640 { "SG_FETCH_REQ", 0x02, 0x02 },
2588 { "CCSGENACK", 0x08, 0x08 }, 1641 { "CCSGENACK", 0x08, 0x08 },
@@ -2606,13 +1659,6 @@ ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
2606} 1659}
2607 1660
2608int 1661int
2609ahd_flexadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2610{
2611 return (ahd_print_register(NULL, 0, "FLEXADR",
2612 0xb0, regvalue, cur_col, wrap));
2613}
2614
2615int
2616ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) 1662ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
2617{ 1663{
2618 return (ahd_print_register(NULL, 0, "CCSCBRAM", 1664 return (ahd_print_register(NULL, 0, "CCSCBRAM",
@@ -2620,39 +1666,13 @@ ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
2620} 1666}
2621 1667
2622int 1668int
2623ahd_flexcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2624{
2625 return (ahd_print_register(NULL, 0, "FLEXCNT",
2626 0xb3, regvalue, cur_col, wrap));
2627}
2628
2629static ahd_reg_parse_entry_t FLEXDMASTAT_parse_table[] = {
2630 { "FLEXDMADONE", 0x01, 0x01 },
2631 { "FLEXDMAERR", 0x02, 0x02 }
2632};
2633
2634int
2635ahd_flexdmastat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2636{
2637 return (ahd_print_register(FLEXDMASTAT_parse_table, 2, "FLEXDMASTAT",
2638 0xb5, regvalue, cur_col, wrap));
2639}
2640
2641int
2642ahd_flexdata_print(u_int regvalue, u_int *cur_col, u_int wrap)
2643{
2644 return (ahd_print_register(NULL, 0, "FLEXDATA",
2645 0xb6, regvalue, cur_col, wrap));
2646}
2647
2648int
2649ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1669ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2650{ 1670{
2651 return (ahd_print_register(NULL, 0, "BRDDAT", 1671 return (ahd_print_register(NULL, 0, "BRDDAT",
2652 0xb8, regvalue, cur_col, wrap)); 1672 0xb8, regvalue, cur_col, wrap));
2653} 1673}
2654 1674
2655static ahd_reg_parse_entry_t BRDCTL_parse_table[] = { 1675static const ahd_reg_parse_entry_t BRDCTL_parse_table[] = {
2656 { "BRDSTB", 0x01, 0x01 }, 1676 { "BRDSTB", 0x01, 0x01 },
2657 { "BRDRW", 0x02, 0x02 }, 1677 { "BRDRW", 0x02, 0x02 },
2658 { "BRDEN", 0x04, 0x04 }, 1678 { "BRDEN", 0x04, 0x04 },
@@ -2682,7 +1702,7 @@ ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2682 0xbc, regvalue, cur_col, wrap)); 1702 0xbc, regvalue, cur_col, wrap));
2683} 1703}
2684 1704
2685static ahd_reg_parse_entry_t SEECTL_parse_table[] = { 1705static const ahd_reg_parse_entry_t SEECTL_parse_table[] = {
2686 { "SEEOP_ERAL", 0x40, 0x70 }, 1706 { "SEEOP_ERAL", 0x40, 0x70 },
2687 { "SEEOP_WRITE", 0x50, 0x70 }, 1707 { "SEEOP_WRITE", 0x50, 0x70 },
2688 { "SEEOP_READ", 0x60, 0x70 }, 1708 { "SEEOP_READ", 0x60, 0x70 },
@@ -2702,7 +1722,7 @@ ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2702 0xbe, regvalue, cur_col, wrap)); 1722 0xbe, regvalue, cur_col, wrap));
2703} 1723}
2704 1724
2705static ahd_reg_parse_entry_t SEESTAT_parse_table[] = { 1725static const ahd_reg_parse_entry_t SEESTAT_parse_table[] = {
2706 { "SEESTART", 0x01, 0x01 }, 1726 { "SEESTART", 0x01, 0x01 },
2707 { "SEEBUSY", 0x02, 0x02 }, 1727 { "SEEBUSY", 0x02, 0x02 },
2708 { "SEEARBACK", 0x04, 0x04 }, 1728 { "SEEARBACK", 0x04, 0x04 },
@@ -2718,34 +1738,7 @@ ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2718 0xbe, regvalue, cur_col, wrap)); 1738 0xbe, regvalue, cur_col, wrap));
2719} 1739}
2720 1740
2721int 1741static const ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
2722ahd_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2723{
2724 return (ahd_print_register(NULL, 0, "SCBCNT",
2725 0xbf, regvalue, cur_col, wrap));
2726}
2727
2728int
2729ahd_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2730{
2731 return (ahd_print_register(NULL, 0, "DFWADDR",
2732 0xc0, regvalue, cur_col, wrap));
2733}
2734
2735static ahd_reg_parse_entry_t DSPFLTRCTL_parse_table[] = {
2736 { "DSPFCNTSEL", 0x0f, 0x0f },
2737 { "EDGESENSE", 0x10, 0x10 },
2738 { "FLTRDISABLE", 0x20, 0x20 }
2739};
2740
2741int
2742ahd_dspfltrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2743{
2744 return (ahd_print_register(DSPFLTRCTL_parse_table, 3, "DSPFLTRCTL",
2745 0xc0, regvalue, cur_col, wrap));
2746}
2747
2748static ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
2749 { "XMITOFFSTDIS", 0x02, 0x02 }, 1742 { "XMITOFFSTDIS", 0x02, 0x02 },
2750 { "RCVROFFSTDIS", 0x04, 0x04 }, 1743 { "RCVROFFSTDIS", 0x04, 0x04 },
2751 { "DESQDIS", 0x10, 0x10 }, 1744 { "DESQDIS", 0x10, 0x10 },
@@ -2760,44 +1753,13 @@ ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2760} 1753}
2761 1754
2762int 1755int
2763ahd_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2764{
2765 return (ahd_print_register(NULL, 0, "DFRADDR",
2766 0xc2, regvalue, cur_col, wrap));
2767}
2768
2769static ahd_reg_parse_entry_t DSPREQCTL_parse_table[] = {
2770 { "MANREQDLY", 0x3f, 0x3f },
2771 { "MANREQCTL", 0xc0, 0xc0 }
2772};
2773
2774int
2775ahd_dspreqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2776{
2777 return (ahd_print_register(DSPREQCTL_parse_table, 2, "DSPREQCTL",
2778 0xc2, regvalue, cur_col, wrap));
2779}
2780
2781static ahd_reg_parse_entry_t DSPACKCTL_parse_table[] = {
2782 { "MANACKDLY", 0x3f, 0x3f },
2783 { "MANACKCTL", 0xc0, 0xc0 }
2784};
2785
2786int
2787ahd_dspackctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2788{
2789 return (ahd_print_register(DSPACKCTL_parse_table, 2, "DSPACKCTL",
2790 0xc3, regvalue, cur_col, wrap));
2791}
2792
2793int
2794ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1756ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2795{ 1757{
2796 return (ahd_print_register(NULL, 0, "DFDAT", 1758 return (ahd_print_register(NULL, 0, "DFDAT",
2797 0xc4, regvalue, cur_col, wrap)); 1759 0xc4, regvalue, cur_col, wrap));
2798} 1760}
2799 1761
2800static ahd_reg_parse_entry_t DSPSELECT_parse_table[] = { 1762static const ahd_reg_parse_entry_t DSPSELECT_parse_table[] = {
2801 { "DSPSEL", 0x1f, 0x1f }, 1763 { "DSPSEL", 0x1f, 0x1f },
2802 { "AUTOINCEN", 0x80, 0x80 } 1764 { "AUTOINCEN", 0x80, 0x80 }
2803}; 1765};
@@ -2809,7 +1771,7 @@ ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap)
2809 0xc4, regvalue, cur_col, wrap)); 1771 0xc4, regvalue, cur_col, wrap));
2810} 1772}
2811 1773
2812static ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = { 1774static const ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = {
2813 { "XMITMANVAL", 0x3f, 0x3f }, 1775 { "XMITMANVAL", 0x3f, 0x3f },
2814 { "AUTOXBCDIS", 0x80, 0x80 } 1776 { "AUTOXBCDIS", 0x80, 0x80 }
2815}; 1777};
@@ -2821,91 +1783,7 @@ ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2821 0xc5, regvalue, cur_col, wrap)); 1783 0xc5, regvalue, cur_col, wrap));
2822} 1784}
2823 1785
2824static ahd_reg_parse_entry_t RCVRBIOSCTL_parse_table[] = { 1786static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
2825 { "RCVRMANVAL", 0x3f, 0x3f },
2826 { "AUTORBCDIS", 0x80, 0x80 }
2827};
2828
2829int
2830ahd_rcvrbiosctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2831{
2832 return (ahd_print_register(RCVRBIOSCTL_parse_table, 2, "RCVRBIOSCTL",
2833 0xc6, regvalue, cur_col, wrap));
2834}
2835
2836int
2837ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
2838{
2839 return (ahd_print_register(NULL, 0, "WRTBIASCALC",
2840 0xc7, regvalue, cur_col, wrap));
2841}
2842
2843int
2844ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
2845{
2846 return (ahd_print_register(NULL, 0, "RCVRBIASCALC",
2847 0xc8, regvalue, cur_col, wrap));
2848}
2849
2850int
2851ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
2852{
2853 return (ahd_print_register(NULL, 0, "DFPTRS",
2854 0xc8, regvalue, cur_col, wrap));
2855}
2856
2857int
2858ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
2859{
2860 return (ahd_print_register(NULL, 0, "SKEWCALC",
2861 0xc9, regvalue, cur_col, wrap));
2862}
2863
2864int
2865ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2866{
2867 return (ahd_print_register(NULL, 0, "DFBKPTR",
2868 0xc9, regvalue, cur_col, wrap));
2869}
2870
2871static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = {
2872 { "DFF_RAMBIST_EN", 0x01, 0x01 },
2873 { "DFF_RAMBIST_DONE", 0x02, 0x02 },
2874 { "DFF_RAMBIST_FAIL", 0x04, 0x04 },
2875 { "DFF_DIR_ERR", 0x08, 0x08 },
2876 { "DFF_CIO_RD_RDY", 0x10, 0x10 },
2877 { "DFF_CIO_WR_RDY", 0x20, 0x20 }
2878};
2879
2880int
2881ahd_dfdbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2882{
2883 return (ahd_print_register(DFDBCTL_parse_table, 6, "DFDBCTL",
2884 0xcb, regvalue, cur_col, wrap));
2885}
2886
2887int
2888ahd_dfscnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2889{
2890 return (ahd_print_register(NULL, 0, "DFSCNT",
2891 0xcc, regvalue, cur_col, wrap));
2892}
2893
2894int
2895ahd_dfbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2896{
2897 return (ahd_print_register(NULL, 0, "DFBCNT",
2898 0xce, regvalue, cur_col, wrap));
2899}
2900
2901int
2902ahd_ovlyaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2903{
2904 return (ahd_print_register(NULL, 0, "OVLYADDR",
2905 0xd4, regvalue, cur_col, wrap));
2906}
2907
2908static ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
2909 { "LOADRAM", 0x01, 0x01 }, 1787 { "LOADRAM", 0x01, 0x01 },
2910 { "SEQRESET", 0x02, 0x02 }, 1788 { "SEQRESET", 0x02, 0x02 },
2911 { "STEP", 0x04, 0x04 }, 1789 { "STEP", 0x04, 0x04 },
@@ -2923,21 +1801,7 @@ ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2923 0xd6, regvalue, cur_col, wrap)); 1801 0xd6, regvalue, cur_col, wrap));
2924} 1802}
2925 1803
2926static ahd_reg_parse_entry_t SEQCTL1_parse_table[] = { 1804static const ahd_reg_parse_entry_t FLAGS_parse_table[] = {
2927 { "RAMBIST_EN", 0x01, 0x01 },
2928 { "RAMBIST_FAIL", 0x02, 0x02 },
2929 { "RAMBIST_DONE", 0x04, 0x04 },
2930 { "OVRLAY_DATA_CHK", 0x08, 0x08 }
2931};
2932
2933int
2934ahd_seqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2935{
2936 return (ahd_print_register(SEQCTL1_parse_table, 4, "SEQCTL1",
2937 0xd7, regvalue, cur_col, wrap));
2938}
2939
2940static ahd_reg_parse_entry_t FLAGS_parse_table[] = {
2941 { "CARRY", 0x01, 0x01 }, 1805 { "CARRY", 0x01, 0x01 },
2942 { "ZERO", 0x02, 0x02 } 1806 { "ZERO", 0x02, 0x02 }
2943}; 1807};
@@ -2949,7 +1813,7 @@ ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
2949 0xd8, regvalue, cur_col, wrap)); 1813 0xd8, regvalue, cur_col, wrap));
2950} 1814}
2951 1815
2952static ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { 1816static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
2953 { "IRET", 0x01, 0x01 }, 1817 { "IRET", 0x01, 0x01 },
2954 { "INTMASK1", 0x02, 0x02 }, 1818 { "INTMASK1", 0x02, 0x02 },
2955 { "INTMASK2", 0x04, 0x04 }, 1819 { "INTMASK2", 0x04, 0x04 },
@@ -3002,24 +1866,6 @@ ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
3002} 1866}
3003 1867
3004int 1868int
3005ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
3006{
3007 return (ahd_print_register(NULL, 0, "BRKADDR0",
3008 0xe6, regvalue, cur_col, wrap));
3009}
3010
3011static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = {
3012 { "BRKDIS", 0x80, 0x80 }
3013};
3014
3015int
3016ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
3017{
3018 return (ahd_print_register(BRKADDR1_parse_table, 1, "BRKADDR1",
3019 0xe6, regvalue, cur_col, wrap));
3020}
3021
3022int
3023ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) 1869ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
3024{ 1870{
3025 return (ahd_print_register(NULL, 0, "ALLONES", 1871 return (ahd_print_register(NULL, 0, "ALLONES",
@@ -3055,13 +1901,6 @@ ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
3055} 1901}
3056 1902
3057int 1903int
3058ahd_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
3059{
3060 return (ahd_print_register(NULL, 0, "FUNCTION1",
3061 0xf0, regvalue, cur_col, wrap));
3062}
3063
3064int
3065ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 1904ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
3066{ 1905{
3067 return (ahd_print_register(NULL, 0, "STACK", 1906 return (ahd_print_register(NULL, 0, "STACK",
@@ -3083,13 +1922,6 @@ ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3083} 1922}
3084 1923
3085int 1924int
3086ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3087{
3088 return (ahd_print_register(NULL, 0, "LASTADDR",
3089 0xf6, regvalue, cur_col, wrap));
3090}
3091
3092int
3093ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1925ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3094{ 1926{
3095 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR", 1927 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
@@ -3111,23 +1943,16 @@ ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap)
3111} 1943}
3112 1944
3113int 1945int
3114ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap) 1946ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
3115{
3116 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
3117 0x100, regvalue, cur_col, wrap));
3118}
3119
3120int
3121ahd_ahd_pci_config_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
3122{ 1947{
3123 return (ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 1948 return (ahd_print_register(NULL, 0, "SRAM_BASE",
3124 0x100, regvalue, cur_col, wrap)); 1949 0x100, regvalue, cur_col, wrap));
3125} 1950}
3126 1951
3127int 1952int
3128ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 1953ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap)
3129{ 1954{
3130 return (ahd_print_register(NULL, 0, "SRAM_BASE", 1955 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
3131 0x100, regvalue, cur_col, wrap)); 1956 0x100, regvalue, cur_col, wrap));
3132} 1957}
3133 1958
@@ -3215,7 +2040,7 @@ ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
3215 0x137, regvalue, cur_col, wrap)); 2040 0x137, regvalue, cur_col, wrap));
3216} 2041}
3217 2042
3218static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = { 2043static const ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
3219 { "FIFORESET", 0x01, 0x01 }, 2044 { "FIFORESET", 0x01, 0x01 },
3220 { "FIFOFLUSH", 0x02, 0x02 }, 2045 { "FIFOFLUSH", 0x02, 0x02 },
3221 { "DIRECTION", 0x04, 0x04 }, 2046 { "DIRECTION", 0x04, 0x04 },
@@ -3235,7 +2060,7 @@ ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
3235 0x138, regvalue, cur_col, wrap)); 2060 0x138, regvalue, cur_col, wrap));
3236} 2061}
3237 2062
3238static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 2063static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
3239 { "NO_DISCONNECT", 0x01, 0x01 }, 2064 { "NO_DISCONNECT", 0x01, 0x01 },
3240 { "SPHASE_PENDING", 0x02, 0x02 }, 2065 { "SPHASE_PENDING", 0x02, 0x02 },
3241 { "DPHASE_PENDING", 0x04, 0x04 }, 2066 { "DPHASE_PENDING", 0x04, 0x04 },
@@ -3268,7 +2093,7 @@ ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
3268 0x13b, regvalue, cur_col, wrap)); 2093 0x13b, regvalue, cur_col, wrap));
3269} 2094}
3270 2095
3271static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { 2096static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
3272 { "P_DATAOUT", 0x00, 0xe0 }, 2097 { "P_DATAOUT", 0x00, 0xe0 },
3273 { "P_DATAOUT_DT", 0x20, 0xe0 }, 2098 { "P_DATAOUT_DT", 0x20, 0xe0 },
3274 { "P_DATAIN", 0x40, 0xe0 }, 2099 { "P_DATAIN", 0x40, 0xe0 },
@@ -3326,7 +2151,7 @@ ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3326 0x144, regvalue, cur_col, wrap)); 2151 0x144, regvalue, cur_col, wrap));
3327} 2152}
3328 2153
3329static ahd_reg_parse_entry_t ARG_1_parse_table[] = { 2154static const ahd_reg_parse_entry_t ARG_1_parse_table[] = {
3330 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 }, 2155 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 },
3331 { "CONT_MSG_LOOP_READ", 0x03, 0x03 }, 2156 { "CONT_MSG_LOOP_READ", 0x03, 0x03 },
3332 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 }, 2157 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 },
@@ -3358,7 +2183,7 @@ ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
3358 0x14a, regvalue, cur_col, wrap)); 2183 0x14a, regvalue, cur_col, wrap));
3359} 2184}
3360 2185
3361static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 2186static const ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
3362 { "ALTSTIM", 0x01, 0x01 }, 2187 { "ALTSTIM", 0x01, 0x01 },
3363 { "ENAUTOATNP", 0x02, 0x02 }, 2188 { "ENAUTOATNP", 0x02, 0x02 },
3364 { "MANUALP", 0x0c, 0x0c }, 2189 { "MANUALP", 0x0c, 0x0c },
@@ -3381,7 +2206,7 @@ ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
3381 0x14c, regvalue, cur_col, wrap)); 2206 0x14c, regvalue, cur_col, wrap));
3382} 2207}
3383 2208
3384static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 2209static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
3385 { "PENDING_MK_MESSAGE", 0x01, 0x01 }, 2210 { "PENDING_MK_MESSAGE", 0x01, 0x01 },
3386 { "TARGET_MSG_PENDING", 0x02, 0x02 }, 2211 { "TARGET_MSG_PENDING", 0x02, 0x02 },
3387 { "SELECTOUT_QFROZEN", 0x04, 0x04 } 2212 { "SELECTOUT_QFROZEN", 0x04, 0x04 }
@@ -3465,20 +2290,20 @@ ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
3465} 2290}
3466 2291
3467int 2292int
3468ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 2293ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
3469{ 2294{
3470 return (ahd_print_register(NULL, 0, "SCB_BASE", 2295 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT",
3471 0x180, regvalue, cur_col, wrap)); 2296 0x180, regvalue, cur_col, wrap));
3472} 2297}
3473 2298
3474int 2299int
3475ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2300ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
3476{ 2301{
3477 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 2302 return (ahd_print_register(NULL, 0, "SCB_BASE",
3478 0x180, regvalue, cur_col, wrap)); 2303 0x180, regvalue, cur_col, wrap));
3479} 2304}
3480 2305
3481static ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = { 2306static const ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = {
3482 { "SG_LIST_NULL", 0x01, 0x01 }, 2307 { "SG_LIST_NULL", 0x01, 0x01 },
3483 { "SG_OVERRUN_RESID", 0x02, 0x02 }, 2308 { "SG_OVERRUN_RESID", 0x02, 0x02 },
3484 { "SG_ADDR_MASK", 0xf8, 0xf8 } 2309 { "SG_ADDR_MASK", 0xf8, 0xf8 }
@@ -3499,27 +2324,6 @@ ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
3499} 2324}
3500 2325
3501int 2326int
3502ahd_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
3503{
3504 return (ahd_print_register(NULL, 0, "SCB_TARGET_PHASES",
3505 0x189, regvalue, cur_col, wrap));
3506}
3507
3508int
3509ahd_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
3510{
3511 return (ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
3512 0x18a, regvalue, cur_col, wrap));
3513}
3514
3515int
3516ahd_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
3517{
3518 return (ahd_print_register(NULL, 0, "SCB_TARGET_ITAG",
3519 0x18b, regvalue, cur_col, wrap));
3520}
3521
3522int
3523ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2327ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3524{ 2328{
3525 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 2329 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR",
@@ -3533,7 +2337,7 @@ ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
3533 0x190, regvalue, cur_col, wrap)); 2337 0x190, regvalue, cur_col, wrap));
3534} 2338}
3535 2339
3536static ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 2340static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
3537 { "SCB_TAG_TYPE", 0x03, 0x03 }, 2341 { "SCB_TAG_TYPE", 0x03, 0x03 },
3538 { "DISCONNECTED", 0x04, 0x04 }, 2342 { "DISCONNECTED", 0x04, 0x04 },
3539 { "STATUS_RCVD", 0x08, 0x08 }, 2343 { "STATUS_RCVD", 0x08, 0x08 },
@@ -3550,7 +2354,7 @@ ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
3550 0x192, regvalue, cur_col, wrap)); 2354 0x192, regvalue, cur_col, wrap));
3551} 2355}
3552 2356
3553static ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 2357static const ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
3554 { "OID", 0x0f, 0x0f }, 2358 { "OID", 0x0f, 0x0f },
3555 { "TID", 0xf0, 0xf0 } 2359 { "TID", 0xf0, 0xf0 }
3556}; 2360};
@@ -3562,7 +2366,7 @@ ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
3562 0x193, regvalue, cur_col, wrap)); 2366 0x193, regvalue, cur_col, wrap));
3563} 2367}
3564 2368
3565static ahd_reg_parse_entry_t SCB_LUN_parse_table[] = { 2369static const ahd_reg_parse_entry_t SCB_LUN_parse_table[] = {
3566 { "LID", 0xff, 0xff } 2370 { "LID", 0xff, 0xff }
3567}; 2371};
3568 2372
@@ -3573,7 +2377,7 @@ ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
3573 0x194, regvalue, cur_col, wrap)); 2377 0x194, regvalue, cur_col, wrap));
3574} 2378}
3575 2379
3576static ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = { 2380static const ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = {
3577 { "SCB_XFERLEN_ODD", 0x01, 0x01 } 2381 { "SCB_XFERLEN_ODD", 0x01, 0x01 }
3578}; 2382};
3579 2383
@@ -3584,7 +2388,7 @@ ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap)
3584 0x195, regvalue, cur_col, wrap)); 2388 0x195, regvalue, cur_col, wrap));
3585} 2389}
3586 2390
3587static ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = { 2391static const ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = {
3588 { "SCB_CDB_LEN_PTR", 0x80, 0x80 } 2392 { "SCB_CDB_LEN_PTR", 0x80, 0x80 }
3589}; 2393};
3590 2394
@@ -3609,7 +2413,7 @@ ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3609 0x198, regvalue, cur_col, wrap)); 2413 0x198, regvalue, cur_col, wrap));
3610} 2414}
3611 2415
3612static ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 2416static const ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
3613 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }, 2417 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f },
3614 { "SG_LAST_SEG", 0x80, 0x80 } 2418 { "SG_LAST_SEG", 0x80, 0x80 }
3615}; 2419};
@@ -3621,7 +2425,7 @@ ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
3621 0x1a0, regvalue, cur_col, wrap)); 2425 0x1a0, regvalue, cur_col, wrap));
3622} 2426}
3623 2427
3624static ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 2428static const ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
3625 { "SG_LIST_NULL", 0x01, 0x01 }, 2429 { "SG_LIST_NULL", 0x01, 0x01 },
3626 { "SG_FULL_RESID", 0x02, 0x02 }, 2430 { "SG_FULL_RESID", 0x02, 0x02 },
3627 { "SG_STATUS_VALID", 0x04, 0x04 } 2431 { "SG_STATUS_VALID", 0x04, 0x04 }
@@ -3656,13 +2460,6 @@ ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap)
3656} 2460}
3657 2461
3658int 2462int
3659ahd_scb_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
3660{
3661 return (ahd_print_register(NULL, 0, "SCB_SPARE",
3662 0x1b0, regvalue, cur_col, wrap));
3663}
3664
3665int
3666ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap) 2463ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap)
3667{ 2464{
3668 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 2465 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS",
diff --git a/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped b/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped
index 11bed07e90b7..4b51e232392f 100644
--- a/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped
@@ -5,7 +5,7 @@
5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $ 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
7 */ 7 */
8static uint8_t seqprog[] = { 8static const uint8_t seqprog[] = {
9 0xff, 0x02, 0x06, 0x78, 9 0xff, 0x02, 0x06, 0x78,
10 0x00, 0xea, 0x6e, 0x59, 10 0x00, 0xea, 0x6e, 0x59,
11 0x01, 0xea, 0x04, 0x30, 11 0x01, 0xea, 0x04, 0x30,
@@ -1027,7 +1027,7 @@ ahd_patch0_func(struct ahd_softc *ahd)
1027 return (0); 1027 return (0);
1028} 1028}
1029 1029
1030static struct patch { 1030static const struct patch {
1031 ahd_patch_func_t *patch_func; 1031 ahd_patch_func_t *patch_func;
1032 uint32_t begin :10, 1032 uint32_t begin :10,
1033 skip_instr :10, 1033 skip_instr :10,
@@ -1166,7 +1166,7 @@ static struct patch {
1166 { ahd_patch23_func, 815, 11, 1 } 1166 { ahd_patch23_func, 815, 11, 1 }
1167}; 1167};
1168 1168
1169static struct cs { 1169static const struct cs {
1170 uint16_t begin; 1170 uint16_t begin;
1171 uint16_t end; 1171 uint16_t end;
1172} critical_sections[] = { 1172} critical_sections[] = {
diff --git a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
index 88bfd767c51c..309a562b009e 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
+++ b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
@@ -8,7 +8,7 @@
8 8
9#include "aic7xxx_osm.h" 9#include "aic7xxx_osm.h"
10 10
11static ahc_reg_parse_entry_t SCSISEQ_parse_table[] = { 11static const ahc_reg_parse_entry_t SCSISEQ_parse_table[] = {
12 { "SCSIRSTO", 0x01, 0x01 }, 12 { "SCSIRSTO", 0x01, 0x01 },
13 { "ENAUTOATNP", 0x02, 0x02 }, 13 { "ENAUTOATNP", 0x02, 0x02 },
14 { "ENAUTOATNI", 0x04, 0x04 }, 14 { "ENAUTOATNI", 0x04, 0x04 },
@@ -26,7 +26,7 @@ ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap)
26 0x00, regvalue, cur_col, wrap)); 26 0x00, regvalue, cur_col, wrap));
27} 27}
28 28
29static ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = { 29static const ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = {
30 { "CLRCHN", 0x02, 0x02 }, 30 { "CLRCHN", 0x02, 0x02 },
31 { "SCAMEN", 0x04, 0x04 }, 31 { "SCAMEN", 0x04, 0x04 },
32 { "SPIOEN", 0x08, 0x08 }, 32 { "SPIOEN", 0x08, 0x08 },
@@ -43,7 +43,7 @@ ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
43 0x01, regvalue, cur_col, wrap)); 43 0x01, regvalue, cur_col, wrap));
44} 44}
45 45
46static ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = { 46static const ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = {
47 { "STPWEN", 0x01, 0x01 }, 47 { "STPWEN", 0x01, 0x01 },
48 { "ACTNEGEN", 0x02, 0x02 }, 48 { "ACTNEGEN", 0x02, 0x02 },
49 { "ENSTIMER", 0x04, 0x04 }, 49 { "ENSTIMER", 0x04, 0x04 },
@@ -60,7 +60,7 @@ ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
60 0x02, regvalue, cur_col, wrap)); 60 0x02, regvalue, cur_col, wrap));
61} 61}
62 62
63static ahc_reg_parse_entry_t SCSISIGO_parse_table[] = { 63static const ahc_reg_parse_entry_t SCSISIGO_parse_table[] = {
64 { "ACKO", 0x01, 0x01 }, 64 { "ACKO", 0x01, 0x01 },
65 { "REQO", 0x02, 0x02 }, 65 { "REQO", 0x02, 0x02 },
66 { "BSYO", 0x04, 0x04 }, 66 { "BSYO", 0x04, 0x04 },
@@ -85,7 +85,7 @@ ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
85 0x03, regvalue, cur_col, wrap)); 85 0x03, regvalue, cur_col, wrap));
86} 86}
87 87
88static ahc_reg_parse_entry_t SCSISIGI_parse_table[] = { 88static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
89 { "ACKI", 0x01, 0x01 }, 89 { "ACKI", 0x01, 0x01 },
90 { "REQI", 0x02, 0x02 }, 90 { "REQI", 0x02, 0x02 },
91 { "BSYI", 0x04, 0x04 }, 91 { "BSYI", 0x04, 0x04 },
@@ -112,7 +112,7 @@ ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
112 0x03, regvalue, cur_col, wrap)); 112 0x03, regvalue, cur_col, wrap));
113} 113}
114 114
115static ahc_reg_parse_entry_t SCSIRATE_parse_table[] = { 115static const ahc_reg_parse_entry_t SCSIRATE_parse_table[] = {
116 { "SINGLE_EDGE", 0x10, 0x10 }, 116 { "SINGLE_EDGE", 0x10, 0x10 },
117 { "ENABLE_CRC", 0x40, 0x40 }, 117 { "ENABLE_CRC", 0x40, 0x40 },
118 { "WIDEXFER", 0x80, 0x80 }, 118 { "WIDEXFER", 0x80, 0x80 },
@@ -128,7 +128,7 @@ ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
128 0x04, regvalue, cur_col, wrap)); 128 0x04, regvalue, cur_col, wrap));
129} 129}
130 130
131static ahc_reg_parse_entry_t SCSIID_parse_table[] = { 131static const ahc_reg_parse_entry_t SCSIID_parse_table[] = {
132 { "TWIN_CHNLB", 0x80, 0x80 }, 132 { "TWIN_CHNLB", 0x80, 0x80 },
133 { "OID", 0x0f, 0x0f }, 133 { "OID", 0x0f, 0x0f },
134 { "TWIN_TID", 0x70, 0x70 }, 134 { "TWIN_TID", 0x70, 0x70 },
@@ -151,20 +151,13 @@ ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap)
151} 151}
152 152
153int 153int
154ahc_scsidath_print(u_int regvalue, u_int *cur_col, u_int wrap)
155{
156 return (ahc_print_register(NULL, 0, "SCSIDATH",
157 0x07, regvalue, cur_col, wrap));
158}
159
160int
161ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 154ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
162{ 155{
163 return (ahc_print_register(NULL, 0, "STCNT", 156 return (ahc_print_register(NULL, 0, "STCNT",
164 0x08, regvalue, cur_col, wrap)); 157 0x08, regvalue, cur_col, wrap));
165} 158}
166 159
167static ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = { 160static const ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = {
168 { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 }, 161 { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 },
169 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 162 { "AUTO_MSGOUT_DE", 0x02, 0x02 },
170 { "SCSIDATL_IMGEN", 0x04, 0x04 }, 163 { "SCSIDATL_IMGEN", 0x04, 0x04 },
@@ -190,7 +183,7 @@ ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
190 0x0a, regvalue, cur_col, wrap)); 183 0x0a, regvalue, cur_col, wrap));
191} 184}
192 185
193static ahc_reg_parse_entry_t CLRSINT0_parse_table[] = { 186static const ahc_reg_parse_entry_t CLRSINT0_parse_table[] = {
194 { "CLRSPIORDY", 0x02, 0x02 }, 187 { "CLRSPIORDY", 0x02, 0x02 },
195 { "CLRSWRAP", 0x08, 0x08 }, 188 { "CLRSWRAP", 0x08, 0x08 },
196 { "CLRIOERR", 0x08, 0x08 }, 189 { "CLRIOERR", 0x08, 0x08 },
@@ -206,7 +199,7 @@ ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
206 0x0b, regvalue, cur_col, wrap)); 199 0x0b, regvalue, cur_col, wrap));
207} 200}
208 201
209static ahc_reg_parse_entry_t SSTAT0_parse_table[] = { 202static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
210 { "DMADONE", 0x01, 0x01 }, 203 { "DMADONE", 0x01, 0x01 },
211 { "SPIORDY", 0x02, 0x02 }, 204 { "SPIORDY", 0x02, 0x02 },
212 { "SDONE", 0x04, 0x04 }, 205 { "SDONE", 0x04, 0x04 },
@@ -225,7 +218,7 @@ ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
225 0x0b, regvalue, cur_col, wrap)); 218 0x0b, regvalue, cur_col, wrap));
226} 219}
227 220
228static ahc_reg_parse_entry_t CLRSINT1_parse_table[] = { 221static const ahc_reg_parse_entry_t CLRSINT1_parse_table[] = {
229 { "CLRREQINIT", 0x01, 0x01 }, 222 { "CLRREQINIT", 0x01, 0x01 },
230 { "CLRPHASECHG", 0x02, 0x02 }, 223 { "CLRPHASECHG", 0x02, 0x02 },
231 { "CLRSCSIPERR", 0x04, 0x04 }, 224 { "CLRSCSIPERR", 0x04, 0x04 },
@@ -242,7 +235,7 @@ ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
242 0x0c, regvalue, cur_col, wrap)); 235 0x0c, regvalue, cur_col, wrap));
243} 236}
244 237
245static ahc_reg_parse_entry_t SSTAT1_parse_table[] = { 238static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
246 { "REQINIT", 0x01, 0x01 }, 239 { "REQINIT", 0x01, 0x01 },
247 { "PHASECHG", 0x02, 0x02 }, 240 { "PHASECHG", 0x02, 0x02 },
248 { "SCSIPERR", 0x04, 0x04 }, 241 { "SCSIPERR", 0x04, 0x04 },
@@ -260,7 +253,7 @@ ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
260 0x0c, regvalue, cur_col, wrap)); 253 0x0c, regvalue, cur_col, wrap));
261} 254}
262 255
263static ahc_reg_parse_entry_t SSTAT2_parse_table[] = { 256static const ahc_reg_parse_entry_t SSTAT2_parse_table[] = {
264 { "DUAL_EDGE_ERR", 0x01, 0x01 }, 257 { "DUAL_EDGE_ERR", 0x01, 0x01 },
265 { "CRCREQERR", 0x02, 0x02 }, 258 { "CRCREQERR", 0x02, 0x02 },
266 { "CRCENDERR", 0x04, 0x04 }, 259 { "CRCENDERR", 0x04, 0x04 },
@@ -278,7 +271,7 @@ ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
278 0x0d, regvalue, cur_col, wrap)); 271 0x0d, regvalue, cur_col, wrap));
279} 272}
280 273
281static ahc_reg_parse_entry_t SSTAT3_parse_table[] = { 274static const ahc_reg_parse_entry_t SSTAT3_parse_table[] = {
282 { "OFFCNT", 0x0f, 0x0f }, 275 { "OFFCNT", 0x0f, 0x0f },
283 { "U2OFFCNT", 0x7f, 0x7f }, 276 { "U2OFFCNT", 0x7f, 0x7f },
284 { "SCSICNT", 0xf0, 0xf0 } 277 { "SCSICNT", 0xf0, 0xf0 }
@@ -291,7 +284,7 @@ ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
291 0x0e, regvalue, cur_col, wrap)); 284 0x0e, regvalue, cur_col, wrap));
292} 285}
293 286
294static ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = { 287static const ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = {
295 { "OID", 0x0f, 0x0f }, 288 { "OID", 0x0f, 0x0f },
296 { "TID", 0xf0, 0xf0 } 289 { "TID", 0xf0, 0xf0 }
297}; 290};
@@ -303,7 +296,7 @@ ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap)
303 0x0f, regvalue, cur_col, wrap)); 296 0x0f, regvalue, cur_col, wrap));
304} 297}
305 298
306static ahc_reg_parse_entry_t SIMODE0_parse_table[] = { 299static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
307 { "ENDMADONE", 0x01, 0x01 }, 300 { "ENDMADONE", 0x01, 0x01 },
308 { "ENSPIORDY", 0x02, 0x02 }, 301 { "ENSPIORDY", 0x02, 0x02 },
309 { "ENSDONE", 0x04, 0x04 }, 302 { "ENSDONE", 0x04, 0x04 },
@@ -321,7 +314,7 @@ ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
321 0x10, regvalue, cur_col, wrap)); 314 0x10, regvalue, cur_col, wrap));
322} 315}
323 316
324static ahc_reg_parse_entry_t SIMODE1_parse_table[] = { 317static const ahc_reg_parse_entry_t SIMODE1_parse_table[] = {
325 { "ENREQINIT", 0x01, 0x01 }, 318 { "ENREQINIT", 0x01, 0x01 },
326 { "ENPHASECHG", 0x02, 0x02 }, 319 { "ENPHASECHG", 0x02, 0x02 },
327 { "ENSCSIPERR", 0x04, 0x04 }, 320 { "ENSCSIPERR", 0x04, 0x04 },
@@ -347,33 +340,13 @@ ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
347} 340}
348 341
349int 342int
350ahc_scsibush_print(u_int regvalue, u_int *cur_col, u_int wrap)
351{
352 return (ahc_print_register(NULL, 0, "SCSIBUSH",
353 0x13, regvalue, cur_col, wrap));
354}
355
356static ahc_reg_parse_entry_t SXFRCTL2_parse_table[] = {
357 { "CMDDMAEN", 0x08, 0x08 },
358 { "AUTORSTDIS", 0x10, 0x10 },
359 { "ASYNC_SETUP", 0x07, 0x07 }
360};
361
362int
363ahc_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
364{
365 return (ahc_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
366 0x13, regvalue, cur_col, wrap));
367}
368
369int
370ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 343ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
371{ 344{
372 return (ahc_print_register(NULL, 0, "SHADDR", 345 return (ahc_print_register(NULL, 0, "SHADDR",
373 0x14, regvalue, cur_col, wrap)); 346 0x14, regvalue, cur_col, wrap));
374} 347}
375 348
376static ahc_reg_parse_entry_t SELTIMER_parse_table[] = { 349static const ahc_reg_parse_entry_t SELTIMER_parse_table[] = {
377 { "STAGE1", 0x01, 0x01 }, 350 { "STAGE1", 0x01, 0x01 },
378 { "STAGE2", 0x02, 0x02 }, 351 { "STAGE2", 0x02, 0x02 },
379 { "STAGE3", 0x04, 0x04 }, 352 { "STAGE3", 0x04, 0x04 },
@@ -389,7 +362,7 @@ ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
389 0x18, regvalue, cur_col, wrap)); 362 0x18, regvalue, cur_col, wrap));
390} 363}
391 364
392static ahc_reg_parse_entry_t SELID_parse_table[] = { 365static const ahc_reg_parse_entry_t SELID_parse_table[] = {
393 { "ONEBIT", 0x08, 0x08 }, 366 { "ONEBIT", 0x08, 0x08 },
394 { "SELID_MASK", 0xf0, 0xf0 } 367 { "SELID_MASK", 0xf0, 0xf0 }
395}; 368};
@@ -401,21 +374,6 @@ ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
401 0x19, regvalue, cur_col, wrap)); 374 0x19, regvalue, cur_col, wrap));
402} 375}
403 376
404static ahc_reg_parse_entry_t SCAMCTL_parse_table[] = {
405 { "DFLTTID", 0x10, 0x10 },
406 { "ALTSTIM", 0x20, 0x20 },
407 { "CLRSCAMSELID", 0x40, 0x40 },
408 { "ENSCAMSELO", 0x80, 0x80 },
409 { "SCAMLVL", 0x03, 0x03 }
410};
411
412int
413ahc_scamctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
414{
415 return (ahc_print_register(SCAMCTL_parse_table, 5, "SCAMCTL",
416 0x1a, regvalue, cur_col, wrap));
417}
418
419int 377int
420ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap) 378ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
421{ 379{
@@ -423,7 +381,7 @@ ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
423 0x1b, regvalue, cur_col, wrap)); 381 0x1b, regvalue, cur_col, wrap));
424} 382}
425 383
426static ahc_reg_parse_entry_t SPIOCAP_parse_table[] = { 384static const ahc_reg_parse_entry_t SPIOCAP_parse_table[] = {
427 { "SSPIOCPS", 0x01, 0x01 }, 385 { "SSPIOCPS", 0x01, 0x01 },
428 { "ROM", 0x02, 0x02 }, 386 { "ROM", 0x02, 0x02 },
429 { "EEPROM", 0x04, 0x04 }, 387 { "EEPROM", 0x04, 0x04 },
@@ -441,7 +399,7 @@ ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap)
441 0x1b, regvalue, cur_col, wrap)); 399 0x1b, regvalue, cur_col, wrap));
442} 400}
443 401
444static ahc_reg_parse_entry_t BRDCTL_parse_table[] = { 402static const ahc_reg_parse_entry_t BRDCTL_parse_table[] = {
445 { "BRDCTL0", 0x01, 0x01 }, 403 { "BRDCTL0", 0x01, 0x01 },
446 { "BRDSTB_ULTRA2", 0x01, 0x01 }, 404 { "BRDSTB_ULTRA2", 0x01, 0x01 },
447 { "BRDCTL1", 0x02, 0x02 }, 405 { "BRDCTL1", 0x02, 0x02 },
@@ -464,7 +422,7 @@ ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
464 0x1d, regvalue, cur_col, wrap)); 422 0x1d, regvalue, cur_col, wrap));
465} 423}
466 424
467static ahc_reg_parse_entry_t SEECTL_parse_table[] = { 425static const ahc_reg_parse_entry_t SEECTL_parse_table[] = {
468 { "SEEDI", 0x01, 0x01 }, 426 { "SEEDI", 0x01, 0x01 },
469 { "SEEDO", 0x02, 0x02 }, 427 { "SEEDO", 0x02, 0x02 },
470 { "SEECK", 0x04, 0x04 }, 428 { "SEECK", 0x04, 0x04 },
@@ -482,7 +440,7 @@ ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
482 0x1e, regvalue, cur_col, wrap)); 440 0x1e, regvalue, cur_col, wrap));
483} 441}
484 442
485static ahc_reg_parse_entry_t SBLKCTL_parse_table[] = { 443static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
486 { "XCVR", 0x01, 0x01 }, 444 { "XCVR", 0x01, 0x01 },
487 { "SELWIDE", 0x02, 0x02 }, 445 { "SELWIDE", 0x02, 0x02 },
488 { "ENAB20", 0x04, 0x04 }, 446 { "ENAB20", 0x04, 0x04 },
@@ -522,13 +480,6 @@ ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap)
522} 480}
523 481
524int 482int
525ahc_cmdsize_table_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
526{
527 return (ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL",
528 0x34, regvalue, cur_col, wrap));
529}
530
531int
532ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap) 483ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap)
533{ 484{
534 return (ahc_print_register(NULL, 0, "MWI_RESIDUAL", 485 return (ahc_print_register(NULL, 0, "MWI_RESIDUAL",
@@ -549,7 +500,7 @@ ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
549 0x3a, regvalue, cur_col, wrap)); 500 0x3a, regvalue, cur_col, wrap));
550} 501}
551 502
552static ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = { 503static const ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = {
553 { "FIFORESET", 0x01, 0x01 }, 504 { "FIFORESET", 0x01, 0x01 },
554 { "FIFOFLUSH", 0x02, 0x02 }, 505 { "FIFOFLUSH", 0x02, 0x02 },
555 { "DIRECTION", 0x04, 0x04 }, 506 { "DIRECTION", 0x04, 0x04 },
@@ -569,7 +520,7 @@ ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
569 0x3b, regvalue, cur_col, wrap)); 520 0x3b, regvalue, cur_col, wrap));
570} 521}
571 522
572static ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 523static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
573 { "NO_DISCONNECT", 0x01, 0x01 }, 524 { "NO_DISCONNECT", 0x01, 0x01 },
574 { "SPHASE_PENDING", 0x02, 0x02 }, 525 { "SPHASE_PENDING", 0x02, 0x02 },
575 { "DPHASE_PENDING", 0x04, 0x04 }, 526 { "DPHASE_PENDING", 0x04, 0x04 },
@@ -602,7 +553,7 @@ ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
602 0x3e, regvalue, cur_col, wrap)); 553 0x3e, regvalue, cur_col, wrap));
603} 554}
604 555
605static ahc_reg_parse_entry_t LASTPHASE_parse_table[] = { 556static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
606 { "MSGI", 0x20, 0x20 }, 557 { "MSGI", 0x20, 0x20 },
607 { "IOI", 0x40, 0x40 }, 558 { "IOI", 0x40, 0x40 },
608 { "CDI", 0x80, 0x80 }, 559 { "CDI", 0x80, 0x80 },
@@ -645,13 +596,6 @@ ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
645} 596}
646 597
647int 598int
648ahc_complete_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
649{
650 return (ahc_print_register(NULL, 0, "COMPLETE_SCBH",
651 0x43, regvalue, cur_col, wrap));
652}
653
654int
655ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 599ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
656{ 600{
657 return (ahc_print_register(NULL, 0, "HSCB_ADDR", 601 return (ahc_print_register(NULL, 0, "HSCB_ADDR",
@@ -700,7 +644,7 @@ ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
700 0x50, regvalue, cur_col, wrap)); 644 0x50, regvalue, cur_col, wrap));
701} 645}
702 646
703static ahc_reg_parse_entry_t ARG_1_parse_table[] = { 647static const ahc_reg_parse_entry_t ARG_1_parse_table[] = {
704 { "CONT_TARG_SESSION", 0x02, 0x02 }, 648 { "CONT_TARG_SESSION", 0x02, 0x02 },
705 { "CONT_MSG_LOOP", 0x04, 0x04 }, 649 { "CONT_MSG_LOOP", 0x04, 0x04 },
706 { "EXIT_MSG_LOOP", 0x08, 0x08 }, 650 { "EXIT_MSG_LOOP", 0x08, 0x08 },
@@ -731,7 +675,7 @@ ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
731 0x53, regvalue, cur_col, wrap)); 675 0x53, regvalue, cur_col, wrap));
732} 676}
733 677
734static ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 678static const ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
735 { "ENAUTOATNP", 0x02, 0x02 }, 679 { "ENAUTOATNP", 0x02, 0x02 },
736 { "ENAUTOATNI", 0x04, 0x04 }, 680 { "ENAUTOATNI", 0x04, 0x04 },
737 { "ENAUTOATNO", 0x08, 0x08 }, 681 { "ENAUTOATNO", 0x08, 0x08 },
@@ -747,7 +691,7 @@ ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
747 0x54, regvalue, cur_col, wrap)); 691 0x54, regvalue, cur_col, wrap));
748} 692}
749 693
750static ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = { 694static const ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = {
751 { "HA_274_EXTENDED_TRANS",0x01, 0x01 } 695 { "HA_274_EXTENDED_TRANS",0x01, 0x01 }
752}; 696};
753 697
@@ -758,7 +702,7 @@ ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap)
758 0x56, regvalue, cur_col, wrap)); 702 0x56, regvalue, cur_col, wrap));
759} 703}
760 704
761static ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 705static const ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
762 { "SCB_DMA", 0x01, 0x01 }, 706 { "SCB_DMA", 0x01, 0x01 },
763 { "TARGET_MSG_PENDING", 0x02, 0x02 } 707 { "TARGET_MSG_PENDING", 0x02, 0x02 }
764}; 708};
@@ -770,7 +714,7 @@ ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
770 0x57, regvalue, cur_col, wrap)); 714 0x57, regvalue, cur_col, wrap));
771} 715}
772 716
773static ahc_reg_parse_entry_t SCSICONF_parse_table[] = { 717static const ahc_reg_parse_entry_t SCSICONF_parse_table[] = {
774 { "ENSPCHK", 0x20, 0x20 }, 718 { "ENSPCHK", 0x20, 0x20 },
775 { "RESET_SCSI", 0x40, 0x40 }, 719 { "RESET_SCSI", 0x40, 0x40 },
776 { "TERM_ENB", 0x80, 0x80 }, 720 { "TERM_ENB", 0x80, 0x80 },
@@ -785,7 +729,7 @@ ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
785 0x5a, regvalue, cur_col, wrap)); 729 0x5a, regvalue, cur_col, wrap));
786} 730}
787 731
788static ahc_reg_parse_entry_t INTDEF_parse_table[] = { 732static const ahc_reg_parse_entry_t INTDEF_parse_table[] = {
789 { "EDGE_TRIG", 0x80, 0x80 }, 733 { "EDGE_TRIG", 0x80, 0x80 },
790 { "VECTOR", 0x0f, 0x0f } 734 { "VECTOR", 0x0f, 0x0f }
791}; 735};
@@ -804,7 +748,7 @@ ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
804 0x5d, regvalue, cur_col, wrap)); 748 0x5d, regvalue, cur_col, wrap));
805} 749}
806 750
807static ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = { 751static const ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = {
808 { "CHANNEL_B_PRIMARY", 0x08, 0x08 }, 752 { "CHANNEL_B_PRIMARY", 0x08, 0x08 },
809 { "BIOSMODE", 0x30, 0x30 }, 753 { "BIOSMODE", 0x30, 0x30 },
810 { "BIOSDISABLED", 0x30, 0x30 } 754 { "BIOSDISABLED", 0x30, 0x30 }
@@ -817,7 +761,7 @@ ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
817 0x5f, regvalue, cur_col, wrap)); 761 0x5f, regvalue, cur_col, wrap));
818} 762}
819 763
820static ahc_reg_parse_entry_t SEQCTL_parse_table[] = { 764static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
821 { "LOADRAM", 0x01, 0x01 }, 765 { "LOADRAM", 0x01, 0x01 },
822 { "SEQRESET", 0x02, 0x02 }, 766 { "SEQRESET", 0x02, 0x02 },
823 { "STEP", 0x04, 0x04 }, 767 { "STEP", 0x04, 0x04 },
@@ -849,7 +793,7 @@ ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
849 0x62, regvalue, cur_col, wrap)); 793 0x62, regvalue, cur_col, wrap));
850} 794}
851 795
852static ahc_reg_parse_entry_t SEQADDR1_parse_table[] = { 796static const ahc_reg_parse_entry_t SEQADDR1_parse_table[] = {
853 { "SEQADDR1_MASK", 0x01, 0x01 } 797 { "SEQADDR1_MASK", 0x01, 0x01 }
854}; 798};
855 799
@@ -902,7 +846,7 @@ ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
902 0x6a, regvalue, cur_col, wrap)); 846 0x6a, regvalue, cur_col, wrap));
903} 847}
904 848
905static ahc_reg_parse_entry_t FLAGS_parse_table[] = { 849static const ahc_reg_parse_entry_t FLAGS_parse_table[] = {
906 { "CARRY", 0x01, 0x01 }, 850 { "CARRY", 0x01, 0x01 },
907 { "ZERO", 0x02, 0x02 } 851 { "ZERO", 0x02, 0x02 }
908}; 852};
@@ -929,13 +873,6 @@ ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
929} 873}
930 874
931int 875int
932ahc_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
933{
934 return (ahc_print_register(NULL, 0, "FUNCTION1",
935 0x6e, regvalue, cur_col, wrap));
936}
937
938int
939ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 876ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
940{ 877{
941 return (ahc_print_register(NULL, 0, "STACK", 878 return (ahc_print_register(NULL, 0, "STACK",
@@ -956,19 +893,7 @@ ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
956 0x70, regvalue, cur_col, wrap)); 893 0x70, regvalue, cur_col, wrap));
957} 894}
958 895
959static ahc_reg_parse_entry_t BCTL_parse_table[] = { 896static const ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
960 { "ENABLE", 0x01, 0x01 },
961 { "ACE", 0x08, 0x08 }
962};
963
964int
965ahc_bctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
966{
967 return (ahc_print_register(BCTL_parse_table, 2, "BCTL",
968 0x84, regvalue, cur_col, wrap));
969}
970
971static ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
972 { "CIOPARCKEN", 0x01, 0x01 }, 897 { "CIOPARCKEN", 0x01, 0x01 },
973 { "USCBSIZE32", 0x02, 0x02 }, 898 { "USCBSIZE32", 0x02, 0x02 },
974 { "RAMPS", 0x04, 0x04 }, 899 { "RAMPS", 0x04, 0x04 },
@@ -986,7 +911,7 @@ ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
986 0x84, regvalue, cur_col, wrap)); 911 0x84, regvalue, cur_col, wrap));
987} 912}
988 913
989static ahc_reg_parse_entry_t BUSTIME_parse_table[] = { 914static const ahc_reg_parse_entry_t BUSTIME_parse_table[] = {
990 { "BON", 0x0f, 0x0f }, 915 { "BON", 0x0f, 0x0f },
991 { "BOFF", 0xf0, 0xf0 } 916 { "BOFF", 0xf0, 0xf0 }
992}; 917};
@@ -998,7 +923,7 @@ ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap)
998 0x85, regvalue, cur_col, wrap)); 923 0x85, regvalue, cur_col, wrap));
999} 924}
1000 925
1001static ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = { 926static const ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = {
1002 { "HADDLDSEL0", 0x01, 0x01 }, 927 { "HADDLDSEL0", 0x01, 0x01 },
1003 { "HADDLDSEL1", 0x02, 0x02 }, 928 { "HADDLDSEL1", 0x02, 0x02 },
1004 { "DSLATT", 0xfc, 0xfc } 929 { "DSLATT", 0xfc, 0xfc }
@@ -1011,7 +936,7 @@ ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1011 0x85, regvalue, cur_col, wrap)); 936 0x85, regvalue, cur_col, wrap));
1012} 937}
1013 938
1014static ahc_reg_parse_entry_t BUSSPD_parse_table[] = { 939static const ahc_reg_parse_entry_t BUSSPD_parse_table[] = {
1015 { "STBON", 0x07, 0x07 }, 940 { "STBON", 0x07, 0x07 },
1016 { "STBOFF", 0x38, 0x38 }, 941 { "STBOFF", 0x38, 0x38 },
1017 { "DFTHRSH_75", 0x80, 0x80 }, 942 { "DFTHRSH_75", 0x80, 0x80 },
@@ -1026,7 +951,7 @@ ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap)
1026 0x86, regvalue, cur_col, wrap)); 951 0x86, regvalue, cur_col, wrap));
1027} 952}
1028 953
1029static ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 954static const ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
1030 { "SEQ_MAILBOX", 0x0f, 0x0f }, 955 { "SEQ_MAILBOX", 0x0f, 0x0f },
1031 { "HOST_TQINPOS", 0x80, 0x80 }, 956 { "HOST_TQINPOS", 0x80, 0x80 },
1032 { "HOST_MAILBOX", 0xf0, 0xf0 } 957 { "HOST_MAILBOX", 0xf0, 0xf0 }
@@ -1039,7 +964,7 @@ ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
1039 0x86, regvalue, cur_col, wrap)); 964 0x86, regvalue, cur_col, wrap));
1040} 965}
1041 966
1042static ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = { 967static const ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = {
1043 { "DFTHRSH_100", 0xc0, 0xc0 } 968 { "DFTHRSH_100", 0xc0, 0xc0 }
1044}; 969};
1045 970
@@ -1050,7 +975,7 @@ ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
1050 0x86, regvalue, cur_col, wrap)); 975 0x86, regvalue, cur_col, wrap));
1051} 976}
1052 977
1053static ahc_reg_parse_entry_t HCNTRL_parse_table[] = { 978static const ahc_reg_parse_entry_t HCNTRL_parse_table[] = {
1054 { "CHIPRST", 0x01, 0x01 }, 979 { "CHIPRST", 0x01, 0x01 },
1055 { "CHIPRSTACK", 0x01, 0x01 }, 980 { "CHIPRSTACK", 0x01, 0x01 },
1056 { "INTEN", 0x02, 0x02 }, 981 { "INTEN", 0x02, 0x02 },
@@ -1088,7 +1013,7 @@ ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1088 0x90, regvalue, cur_col, wrap)); 1013 0x90, regvalue, cur_col, wrap));
1089} 1014}
1090 1015
1091static ahc_reg_parse_entry_t INTSTAT_parse_table[] = { 1016static const ahc_reg_parse_entry_t INTSTAT_parse_table[] = {
1092 { "SEQINT", 0x01, 0x01 }, 1017 { "SEQINT", 0x01, 0x01 },
1093 { "CMDCMPLT", 0x02, 0x02 }, 1018 { "CMDCMPLT", 0x02, 0x02 },
1094 { "SCSIINT", 0x04, 0x04 }, 1019 { "SCSIINT", 0x04, 0x04 },
@@ -1119,7 +1044,7 @@ ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1119 0x91, regvalue, cur_col, wrap)); 1044 0x91, regvalue, cur_col, wrap));
1120} 1045}
1121 1046
1122static ahc_reg_parse_entry_t CLRINT_parse_table[] = { 1047static const ahc_reg_parse_entry_t CLRINT_parse_table[] = {
1123 { "CLRSEQINT", 0x01, 0x01 }, 1048 { "CLRSEQINT", 0x01, 0x01 },
1124 { "CLRCMDINT", 0x02, 0x02 }, 1049 { "CLRCMDINT", 0x02, 0x02 },
1125 { "CLRSCSIINT", 0x04, 0x04 }, 1050 { "CLRSCSIINT", 0x04, 0x04 },
@@ -1134,7 +1059,7 @@ ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
1134 0x92, regvalue, cur_col, wrap)); 1059 0x92, regvalue, cur_col, wrap));
1135} 1060}
1136 1061
1137static ahc_reg_parse_entry_t ERROR_parse_table[] = { 1062static const ahc_reg_parse_entry_t ERROR_parse_table[] = {
1138 { "ILLHADDR", 0x01, 0x01 }, 1063 { "ILLHADDR", 0x01, 0x01 },
1139 { "ILLSADDR", 0x02, 0x02 }, 1064 { "ILLSADDR", 0x02, 0x02 },
1140 { "ILLOPCODE", 0x04, 0x04 }, 1065 { "ILLOPCODE", 0x04, 0x04 },
@@ -1152,7 +1077,7 @@ ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
1152 0x92, regvalue, cur_col, wrap)); 1077 0x92, regvalue, cur_col, wrap));
1153} 1078}
1154 1079
1155static ahc_reg_parse_entry_t DFCNTRL_parse_table[] = { 1080static const ahc_reg_parse_entry_t DFCNTRL_parse_table[] = {
1156 { "FIFORESET", 0x01, 0x01 }, 1081 { "FIFORESET", 0x01, 0x01 },
1157 { "FIFOFLUSH", 0x02, 0x02 }, 1082 { "FIFOFLUSH", 0x02, 0x02 },
1158 { "DIRECTION", 0x04, 0x04 }, 1083 { "DIRECTION", 0x04, 0x04 },
@@ -1172,7 +1097,7 @@ ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1172 0x93, regvalue, cur_col, wrap)); 1097 0x93, regvalue, cur_col, wrap));
1173} 1098}
1174 1099
1175static ahc_reg_parse_entry_t DFSTATUS_parse_table[] = { 1100static const ahc_reg_parse_entry_t DFSTATUS_parse_table[] = {
1176 { "FIFOEMP", 0x01, 0x01 }, 1101 { "FIFOEMP", 0x01, 0x01 },
1177 { "FIFOFULL", 0x02, 0x02 }, 1102 { "FIFOFULL", 0x02, 0x02 },
1178 { "DFTHRESH", 0x04, 0x04 }, 1103 { "DFTHRESH", 0x04, 0x04 },
@@ -1198,20 +1123,13 @@ ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1198} 1123}
1199 1124
1200int 1125int
1201ahc_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1202{
1203 return (ahc_print_register(NULL, 0, "DFRADDR",
1204 0x97, regvalue, cur_col, wrap));
1205}
1206
1207int
1208ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1126ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1209{ 1127{
1210 return (ahc_print_register(NULL, 0, "DFDAT", 1128 return (ahc_print_register(NULL, 0, "DFDAT",
1211 0x99, regvalue, cur_col, wrap)); 1129 0x99, regvalue, cur_col, wrap));
1212} 1130}
1213 1131
1214static ahc_reg_parse_entry_t SCBCNT_parse_table[] = { 1132static const ahc_reg_parse_entry_t SCBCNT_parse_table[] = {
1215 { "SCBAUTO", 0x80, 0x80 }, 1133 { "SCBAUTO", 0x80, 0x80 },
1216 { "SCBCNT_MASK", 0x1f, 0x1f } 1134 { "SCBCNT_MASK", 0x1f, 0x1f }
1217}; 1135};
@@ -1231,20 +1149,13 @@ ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1231} 1149}
1232 1150
1233int 1151int
1234ahc_qincnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1235{
1236 return (ahc_print_register(NULL, 0, "QINCNT",
1237 0x9c, regvalue, cur_col, wrap));
1238}
1239
1240int
1241ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) 1152ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1242{ 1153{
1243 return (ahc_print_register(NULL, 0, "QOUTFIFO", 1154 return (ahc_print_register(NULL, 0, "QOUTFIFO",
1244 0x9d, regvalue, cur_col, wrap)); 1155 0x9d, regvalue, cur_col, wrap));
1245} 1156}
1246 1157
1247static ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = { 1158static const ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = {
1248 { "TARGCRCCNTEN", 0x04, 0x04 }, 1159 { "TARGCRCCNTEN", 0x04, 0x04 },
1249 { "TARGCRCENDEN", 0x08, 0x08 }, 1160 { "TARGCRCENDEN", 0x08, 0x08 },
1250 { "CRCREQCHKEN", 0x10, 0x10 }, 1161 { "CRCREQCHKEN", 0x10, 0x10 },
@@ -1260,14 +1171,7 @@ ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1260 0x9d, regvalue, cur_col, wrap)); 1171 0x9d, regvalue, cur_col, wrap));
1261} 1172}
1262 1173
1263int 1174static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
1264ahc_qoutcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1265{
1266 return (ahc_print_register(NULL, 0, "QOUTCNT",
1267 0x9e, regvalue, cur_col, wrap));
1268}
1269
1270static ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
1271 { "DATA_OUT_PHASE", 0x01, 0x01 }, 1175 { "DATA_OUT_PHASE", 0x01, 0x01 },
1272 { "DATA_IN_PHASE", 0x02, 0x02 }, 1176 { "DATA_IN_PHASE", 0x02, 0x02 },
1273 { "MSG_OUT_PHASE", 0x04, 0x04 }, 1177 { "MSG_OUT_PHASE", 0x04, 0x04 },
@@ -1284,7 +1188,7 @@ ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
1284 0x9e, regvalue, cur_col, wrap)); 1188 0x9e, regvalue, cur_col, wrap));
1285} 1189}
1286 1190
1287static ahc_reg_parse_entry_t SFUNCT_parse_table[] = { 1191static const ahc_reg_parse_entry_t SFUNCT_parse_table[] = {
1288 { "ALT_MODE", 0x80, 0x80 } 1192 { "ALT_MODE", 0x80, 0x80 }
1289}; 1193};
1290 1194
@@ -1351,7 +1255,7 @@ ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1351 0xac, regvalue, cur_col, wrap)); 1255 0xac, regvalue, cur_col, wrap));
1352} 1256}
1353 1257
1354static ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 1258static const ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
1355 { "SG_LAST_SEG", 0x80, 0x80 }, 1259 { "SG_LAST_SEG", 0x80, 0x80 },
1356 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f } 1260 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }
1357}; 1261};
@@ -1363,7 +1267,7 @@ ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1363 0xb0, regvalue, cur_col, wrap)); 1267 0xb0, regvalue, cur_col, wrap));
1364} 1268}
1365 1269
1366static ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 1270static const ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
1367 { "SG_LIST_NULL", 0x01, 0x01 }, 1271 { "SG_LIST_NULL", 0x01, 0x01 },
1368 { "SG_FULL_RESID", 0x02, 0x02 }, 1272 { "SG_FULL_RESID", 0x02, 0x02 },
1369 { "SG_RESID_VALID", 0x04, 0x04 } 1273 { "SG_RESID_VALID", 0x04, 0x04 }
@@ -1376,7 +1280,7 @@ ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1376 0xb4, regvalue, cur_col, wrap)); 1280 0xb4, regvalue, cur_col, wrap));
1377} 1281}
1378 1282
1379static ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 1283static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
1380 { "DISCONNECTED", 0x04, 0x04 }, 1284 { "DISCONNECTED", 0x04, 0x04 },
1381 { "ULTRAENB", 0x08, 0x08 }, 1285 { "ULTRAENB", 0x08, 0x08 },
1382 { "MK_MESSAGE", 0x10, 0x10 }, 1286 { "MK_MESSAGE", 0x10, 0x10 },
@@ -1394,7 +1298,7 @@ ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
1394 0xb8, regvalue, cur_col, wrap)); 1298 0xb8, regvalue, cur_col, wrap));
1395} 1299}
1396 1300
1397static ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 1301static const ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
1398 { "TWIN_CHNLB", 0x80, 0x80 }, 1302 { "TWIN_CHNLB", 0x80, 0x80 },
1399 { "OID", 0x0f, 0x0f }, 1303 { "OID", 0x0f, 0x0f },
1400 { "TWIN_TID", 0x70, 0x70 }, 1304 { "TWIN_TID", 0x70, 0x70 },
@@ -1408,7 +1312,7 @@ ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1408 0xb9, regvalue, cur_col, wrap)); 1312 0xb9, regvalue, cur_col, wrap));
1409} 1313}
1410 1314
1411static ahc_reg_parse_entry_t SCB_LUN_parse_table[] = { 1315static const ahc_reg_parse_entry_t SCB_LUN_parse_table[] = {
1412 { "SCB_XFERLEN_ODD", 0x80, 0x80 }, 1316 { "SCB_XFERLEN_ODD", 0x80, 0x80 },
1413 { "LID", 0x3f, 0x3f } 1317 { "LID", 0x3f, 0x3f }
1414}; 1318};
@@ -1455,14 +1359,7 @@ ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
1455 0xbf, regvalue, cur_col, wrap)); 1359 0xbf, regvalue, cur_col, wrap));
1456} 1360}
1457 1361
1458int 1362static const ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
1459ahc_scb_64_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
1460{
1461 return (ahc_print_register(NULL, 0, "SCB_64_SPARE",
1462 0xc0, regvalue, cur_col, wrap));
1463}
1464
1465static ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
1466 { "DO_2840", 0x01, 0x01 }, 1363 { "DO_2840", 0x01, 0x01 },
1467 { "CK_2840", 0x02, 0x02 }, 1364 { "CK_2840", 0x02, 0x02 },
1468 { "CS_2840", 0x04, 0x04 } 1365 { "CS_2840", 0x04, 0x04 }
@@ -1475,7 +1372,7 @@ ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
1475 0xc0, regvalue, cur_col, wrap)); 1372 0xc0, regvalue, cur_col, wrap));
1476} 1373}
1477 1374
1478static ahc_reg_parse_entry_t STATUS_2840_parse_table[] = { 1375static const ahc_reg_parse_entry_t STATUS_2840_parse_table[] = {
1479 { "DI_2840", 0x01, 0x01 }, 1376 { "DI_2840", 0x01, 0x01 },
1480 { "EEPROM_TF", 0x80, 0x80 }, 1377 { "EEPROM_TF", 0x80, 0x80 },
1481 { "ADSEL", 0x1e, 0x1e }, 1378 { "ADSEL", 0x1e, 0x1e },
@@ -1524,7 +1421,7 @@ ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1524 0xea, regvalue, cur_col, wrap)); 1421 0xea, regvalue, cur_col, wrap));
1525} 1422}
1526 1423
1527static ahc_reg_parse_entry_t CCSGCTL_parse_table[] = { 1424static const ahc_reg_parse_entry_t CCSGCTL_parse_table[] = {
1528 { "CCSGRESET", 0x01, 0x01 }, 1425 { "CCSGRESET", 0x01, 0x01 },
1529 { "SG_FETCH_NEEDED", 0x02, 0x02 }, 1426 { "SG_FETCH_NEEDED", 0x02, 0x02 },
1530 { "CCSGEN", 0x08, 0x08 }, 1427 { "CCSGEN", 0x08, 0x08 },
@@ -1552,7 +1449,7 @@ ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1552 0xed, regvalue, cur_col, wrap)); 1449 0xed, regvalue, cur_col, wrap));
1553} 1450}
1554 1451
1555static ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = { 1452static const ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = {
1556 { "CCSCBRESET", 0x01, 0x01 }, 1453 { "CCSCBRESET", 0x01, 0x01 },
1557 { "CCSCBDIR", 0x04, 0x04 }, 1454 { "CCSCBDIR", 0x04, 0x04 },
1558 { "CCSCBEN", 0x08, 0x08 }, 1455 { "CCSCBEN", 0x08, 0x08 },
@@ -1610,7 +1507,7 @@ ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1610 0xf8, regvalue, cur_col, wrap)); 1507 0xf8, regvalue, cur_col, wrap));
1611} 1508}
1612 1509
1613static ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 1510static const ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
1614 { "SDSCB_ROLLOVER", 0x10, 0x10 }, 1511 { "SDSCB_ROLLOVER", 0x10, 0x10 },
1615 { "SNSCB_ROLLOVER", 0x20, 0x20 }, 1512 { "SNSCB_ROLLOVER", 0x20, 0x20 },
1616 { "SCB_AVAIL", 0x40, 0x40 }, 1513 { "SCB_AVAIL", 0x40, 0x40 },
@@ -1625,7 +1522,7 @@ ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
1625 0xfa, regvalue, cur_col, wrap)); 1522 0xfa, regvalue, cur_col, wrap));
1626} 1523}
1627 1524
1628static ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = { 1525static const ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1629 { "RD_DFTHRSH_MIN", 0x00, 0x00 }, 1526 { "RD_DFTHRSH_MIN", 0x00, 0x00 },
1630 { "WR_DFTHRSH_MIN", 0x00, 0x00 }, 1527 { "WR_DFTHRSH_MIN", 0x00, 0x00 },
1631 { "RD_DFTHRSH_25", 0x01, 0x01 }, 1528 { "RD_DFTHRSH_25", 0x01, 0x01 },
@@ -1653,7 +1550,7 @@ ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1653 0xfb, regvalue, cur_col, wrap)); 1550 0xfb, regvalue, cur_col, wrap));
1654} 1551}
1655 1552
1656static ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 1553static const ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
1657 { "LAST_SEG_DONE", 0x01, 0x01 }, 1554 { "LAST_SEG_DONE", 0x01, 0x01 },
1658 { "LAST_SEG", 0x02, 0x02 }, 1555 { "LAST_SEG", 0x02, 0x02 },
1659 { "SG_ADDR_MASK", 0xf8, 0xf8 } 1556 { "SG_ADDR_MASK", 0xf8, 0xf8 }
@@ -1666,7 +1563,7 @@ ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
1666 0xfc, regvalue, cur_col, wrap)); 1563 0xfc, regvalue, cur_col, wrap));
1667} 1564}
1668 1565
1669static ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { 1566static const ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
1670 { "LAST_SEG_DONE", 0x01, 0x01 }, 1567 { "LAST_SEG_DONE", 0x01, 0x01 },
1671 { "LAST_SEG", 0x02, 0x02 }, 1568 { "LAST_SEG", 0x02, 0x02 },
1672 { "SG_ADDR_MASK", 0xf8, 0xf8 } 1569 { "SG_ADDR_MASK", 0xf8, 0xf8 }
diff --git a/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped b/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped
index 4cee08521e75..07e93fbae706 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped
+++ b/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped
@@ -5,7 +5,7 @@
5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $ 5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
7 */ 7 */
8static uint8_t seqprog[] = { 8static const uint8_t seqprog[] = {
9 0xb2, 0x00, 0x00, 0x08, 9 0xb2, 0x00, 0x00, 0x08,
10 0xf7, 0x11, 0x22, 0x08, 10 0xf7, 0x11, 0x22, 0x08,
11 0x00, 0x65, 0xee, 0x59, 11 0x00, 0x65, 0xee, 0x59,
@@ -1081,7 +1081,7 @@ ahc_patch0_func(struct ahc_softc *ahc)
1081 return (0); 1081 return (0);
1082} 1082}
1083 1083
1084static struct patch { 1084static const struct patch {
1085 ahc_patch_func_t *patch_func; 1085 ahc_patch_func_t *patch_func;
1086 uint32_t begin :10, 1086 uint32_t begin :10,
1087 skip_instr :10, 1087 skip_instr :10,
@@ -1291,7 +1291,7 @@ static struct patch {
1291 { ahc_patch4_func, 865, 12, 1 } 1291 { ahc_patch4_func, 865, 12, 1 }
1292}; 1292};
1293 1293
1294static struct cs { 1294static const struct cs {
1295 uint16_t begin; 1295 uint16_t begin;
1296 uint16_t end; 1296 uint16_t end;
1297} critical_sections[] = { 1297} critical_sections[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 20:31:11 -0400