diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/scsi/aic7xxx/aic79xx.reg |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'drivers/scsi/aic7xxx/aic79xx.reg')
-rw-r--r-- | drivers/scsi/aic7xxx/aic79xx.reg | 3958 |
1 files changed, 3958 insertions, 0 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx.reg b/drivers/scsi/aic7xxx/aic79xx.reg new file mode 100644 index 000000000000..cca58edc8648 --- /dev/null +++ b/drivers/scsi/aic7xxx/aic79xx.reg | |||
@@ -0,0 +1,3958 @@ | |||
1 | /* | ||
2 | * Aic79xx register and scratch ram definitions. | ||
3 | * | ||
4 | * Copyright (c) 1994-2001 Justin T. Gibbs. | ||
5 | * Copyright (c) 2000-2002 Adaptec Inc. | ||
6 | * All rights reserved. | ||
7 | * | ||
8 | * Redistribution and use in source and binary forms, with or without | ||
9 | * modification, are permitted provided that the following conditions | ||
10 | * are met: | ||
11 | * 1. Redistributions of source code must retain the above copyright | ||
12 | * notice, this list of conditions, and the following disclaimer, | ||
13 | * without modification. | ||
14 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | ||
15 | * substantially similar to the "NO WARRANTY" disclaimer below | ||
16 | * ("Disclaimer") and any redistribution must be conditioned upon | ||
17 | * including a substantially similar Disclaimer requirement for further | ||
18 | * binary redistribution. | ||
19 | * 3. Neither the names of the above-listed copyright holders nor the names | ||
20 | * of any contributors may be used to endorse or promote products derived | ||
21 | * from this software without specific prior written permission. | ||
22 | * | ||
23 | * Alternatively, this software may be distributed under the terms of the | ||
24 | * GNU General Public License ("GPL") version 2 as published by the Free | ||
25 | * Software Foundation. | ||
26 | * | ||
27 | * NO WARRANTY | ||
28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | ||
31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
32 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | ||
36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | ||
37 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||
38 | * POSSIBILITY OF SUCH DAMAGES. | ||
39 | * | ||
40 | * $FreeBSD$ | ||
41 | */ | ||
42 | VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $" | ||
43 | |||
44 | /* | ||
45 | * This file is processed by the aic7xxx_asm utility for use in assembling | ||
46 | * firmware for the aic79xx family of SCSI host adapters as well as to generate | ||
47 | * a C header file for use in the kernel portion of the Aic79xx driver. | ||
48 | */ | ||
49 | |||
50 | /* Register window Modes */ | ||
51 | #define M_DFF0 0 | ||
52 | #define M_DFF1 1 | ||
53 | #define M_CCHAN 2 | ||
54 | #define M_SCSI 3 | ||
55 | #define M_CFG 4 | ||
56 | #define M_DST_SHIFT 4 | ||
57 | |||
58 | #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) | ||
59 | #define SET_MODE(src, dst) \ | ||
60 | SET_SRC_MODE src; \ | ||
61 | SET_DST_MODE dst; \ | ||
62 | if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ | ||
63 | mvi MK_MODE(src, dst) call set_mode_work_around; \ | ||
64 | } else { \ | ||
65 | mvi MODE_PTR, MK_MODE(src, dst); \ | ||
66 | } | ||
67 | |||
68 | #define TOGGLE_DFF_MODE \ | ||
69 | if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ | ||
70 | call toggle_dff_mode_work_around; \ | ||
71 | } else { \ | ||
72 | xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ | ||
73 | } | ||
74 | |||
75 | #define RESTORE_MODE(mode) \ | ||
76 | if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ | ||
77 | mov mode call set_mode_work_around; \ | ||
78 | } else { \ | ||
79 | mov MODE_PTR, mode; \ | ||
80 | } | ||
81 | |||
82 | #define SET_SEQINTCODE(code) \ | ||
83 | if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ | ||
84 | mvi code call set_seqint_work_around; \ | ||
85 | } else { \ | ||
86 | mvi SEQINTCODE, code; \ | ||
87 | } | ||
88 | |||
89 | /* | ||
90 | * Mode Pointer | ||
91 | * Controls which of the 5, 512byte, address spaces should be used | ||
92 | * as the source and destination of any register accesses in our | ||
93 | * register window. | ||
94 | */ | ||
95 | register MODE_PTR { | ||
96 | address 0x000 | ||
97 | access_mode RW | ||
98 | field DST_MODE 0x70 | ||
99 | field SRC_MODE 0x07 | ||
100 | mode_pointer | ||
101 | } | ||
102 | |||
103 | const SRC_MODE_SHIFT 0 | ||
104 | const DST_MODE_SHIFT 4 | ||
105 | |||
106 | /* | ||
107 | * Host Interrupt Status | ||
108 | */ | ||
109 | register INTSTAT { | ||
110 | address 0x001 | ||
111 | access_mode RW | ||
112 | field HWERRINT 0x80 | ||
113 | field BRKADRINT 0x40 | ||
114 | field SWTMINT 0x20 | ||
115 | field PCIINT 0x10 | ||
116 | field SCSIINT 0x08 | ||
117 | field SEQINT 0x04 | ||
118 | field CMDCMPLT 0x02 | ||
119 | field SPLTINT 0x01 | ||
120 | mask INT_PEND 0xFF | ||
121 | } | ||
122 | |||
123 | /* | ||
124 | * Sequencer Interrupt Code | ||
125 | */ | ||
126 | register SEQINTCODE { | ||
127 | address 0x002 | ||
128 | access_mode RW | ||
129 | field { | ||
130 | NO_SEQINT, /* No seqint pending. */ | ||
131 | BAD_PHASE, /* unknown scsi bus phase */ | ||
132 | SEND_REJECT, /* sending a message reject */ | ||
133 | PROTO_VIOLATION, /* Protocol Violation */ | ||
134 | NO_MATCH, /* no cmd match for reconnect */ | ||
135 | IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ | ||
136 | PDATA_REINIT, /* | ||
137 | * Returned to data phase | ||
138 | * that requires data | ||
139 | * transfer pointers to be | ||
140 | * recalculated from the | ||
141 | * transfer residual. | ||
142 | */ | ||
143 | HOST_MSG_LOOP, /* | ||
144 | * The bus is ready for the | ||
145 | * host to perform another | ||
146 | * message transaction. This | ||
147 | * mechanism is used for things | ||
148 | * like sync/wide negotiation | ||
149 | * that require a kernel based | ||
150 | * message state engine. | ||
151 | */ | ||
152 | BAD_STATUS, /* Bad status from target */ | ||
153 | DATA_OVERRUN, /* | ||
154 | * Target attempted to write | ||
155 | * beyond the bounds of its | ||
156 | * command. | ||
157 | */ | ||
158 | MKMSG_FAILED, /* | ||
159 | * Target completed command | ||
160 | * without honoring our ATN | ||
161 | * request to issue a message. | ||
162 | */ | ||
163 | MISSED_BUSFREE, /* | ||
164 | * The sequencer never saw | ||
165 | * the bus go free after | ||
166 | * either a command complete | ||
167 | * or disconnect message. | ||
168 | */ | ||
169 | DUMP_CARD_STATE, | ||
170 | ILLEGAL_PHASE, | ||
171 | INVALID_SEQINT, | ||
172 | CFG4ISTAT_INTR, | ||
173 | STATUS_OVERRUN, | ||
174 | CFG4OVERRUN, | ||
175 | ENTERING_NONPACK, | ||
176 | TASKMGMT_FUNC_COMPLETE, /* | ||
177 | * Task management function | ||
178 | * request completed with | ||
179 | * an expected busfree. | ||
180 | */ | ||
181 | TASKMGMT_CMD_CMPLT_OKAY, /* | ||
182 | * A command with a non-zero | ||
183 | * task management function | ||
184 | * has completed via the normal | ||
185 | * command completion method | ||
186 | * for commands with a zero | ||
187 | * task management function. | ||
188 | * This happens when an attempt | ||
189 | * to abort a command loses | ||
190 | * the race for the command to | ||
191 | * complete normally. | ||
192 | */ | ||
193 | TRACEPOINT0, | ||
194 | TRACEPOINT1, | ||
195 | TRACEPOINT2, | ||
196 | TRACEPOINT3, | ||
197 | SAW_HWERR, | ||
198 | BAD_SCB_STATUS | ||
199 | } | ||
200 | } | ||
201 | |||
202 | /* | ||
203 | * Clear Host Interrupt | ||
204 | */ | ||
205 | register CLRINT { | ||
206 | address 0x003 | ||
207 | access_mode WO | ||
208 | field CLRHWERRINT 0x80 /* Rev B or greater */ | ||
209 | field CLRBRKADRINT 0x40 | ||
210 | field CLRSWTMINT 0x20 | ||
211 | field CLRPCIINT 0x10 | ||
212 | field CLRSCSIINT 0x08 | ||
213 | field CLRSEQINT 0x04 | ||
214 | field CLRCMDINT 0x02 | ||
215 | field CLRSPLTINT 0x01 | ||
216 | } | ||
217 | |||
218 | /* | ||
219 | * Error Register | ||
220 | */ | ||
221 | register ERROR { | ||
222 | address 0x004 | ||
223 | access_mode RO | ||
224 | field CIOPARERR 0x80 | ||
225 | field CIOACCESFAIL 0x40 /* Rev B or greater */ | ||
226 | field MPARERR 0x20 | ||
227 | field DPARERR 0x10 | ||
228 | field SQPARERR 0x08 | ||
229 | field ILLOPCODE 0x04 | ||
230 | field DSCTMOUT 0x02 | ||
231 | } | ||
232 | |||
233 | /* | ||
234 | * Clear Error | ||
235 | */ | ||
236 | register CLRERR { | ||
237 | address 0x004 | ||
238 | access_mode WO | ||
239 | field CLRCIOPARERR 0x80 | ||
240 | field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ | ||
241 | field CLRMPARERR 0x20 | ||
242 | field CLRDPARERR 0x10 | ||
243 | field CLRSQPARERR 0x08 | ||
244 | field CLRILLOPCODE 0x04 | ||
245 | field CLRDSCTMOUT 0x02 | ||
246 | } | ||
247 | |||
248 | /* | ||
249 | * Host Control Register | ||
250 | * Overall host control of the device. | ||
251 | */ | ||
252 | register HCNTRL { | ||
253 | address 0x005 | ||
254 | access_mode RW | ||
255 | field SEQ_RESET 0x80 /* Rev B or greater */ | ||
256 | field POWRDN 0x40 | ||
257 | field SWINT 0x10 | ||
258 | field SWTIMER_START_B 0x08 /* Rev B or greater */ | ||
259 | field PAUSE 0x04 | ||
260 | field INTEN 0x02 | ||
261 | field CHIPRST 0x01 | ||
262 | field CHIPRSTACK 0x01 | ||
263 | } | ||
264 | |||
265 | /* | ||
266 | * Host New SCB Queue Offset | ||
267 | */ | ||
268 | register HNSCB_QOFF { | ||
269 | address 0x006 | ||
270 | access_mode RW | ||
271 | size 2 | ||
272 | } | ||
273 | |||
274 | /* | ||
275 | * Host Empty SCB Queue Offset | ||
276 | */ | ||
277 | register HESCB_QOFF { | ||
278 | address 0x008 | ||
279 | access_mode RW | ||
280 | } | ||
281 | |||
282 | /* | ||
283 | * Host Mailbox | ||
284 | */ | ||
285 | register HS_MAILBOX { | ||
286 | address 0x00B | ||
287 | access_mode RW | ||
288 | mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ | ||
289 | mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ | ||
290 | } | ||
291 | |||
292 | /* | ||
293 | * Sequencer Interupt Status | ||
294 | */ | ||
295 | register SEQINTSTAT { | ||
296 | address 0x00C | ||
297 | access_mode RO | ||
298 | field SEQ_SWTMRTO 0x10 | ||
299 | field SEQ_SEQINT 0x08 | ||
300 | field SEQ_SCSIINT 0x04 | ||
301 | field SEQ_PCIINT 0x02 | ||
302 | field SEQ_SPLTINT 0x01 | ||
303 | } | ||
304 | |||
305 | /* | ||
306 | * Clear SEQ Interrupt | ||
307 | */ | ||
308 | register CLRSEQINTSTAT { | ||
309 | address 0x00C | ||
310 | access_mode WO | ||
311 | field CLRSEQ_SWTMRTO 0x10 | ||
312 | field CLRSEQ_SEQINT 0x08 | ||
313 | field CLRSEQ_SCSIINT 0x04 | ||
314 | field CLRSEQ_PCIINT 0x02 | ||
315 | field CLRSEQ_SPLTINT 0x01 | ||
316 | } | ||
317 | |||
318 | /* | ||
319 | * Software Timer | ||
320 | */ | ||
321 | register SWTIMER { | ||
322 | address 0x00E | ||
323 | access_mode RW | ||
324 | size 2 | ||
325 | } | ||
326 | |||
327 | /* | ||
328 | * SEQ New SCB Queue Offset | ||
329 | */ | ||
330 | register SNSCB_QOFF { | ||
331 | address 0x010 | ||
332 | access_mode RW | ||
333 | size 2 | ||
334 | modes M_CCHAN | ||
335 | } | ||
336 | |||
337 | /* | ||
338 | * SEQ Empty SCB Queue Offset | ||
339 | */ | ||
340 | register SESCB_QOFF { | ||
341 | address 0x012 | ||
342 | access_mode RW | ||
343 | modes M_CCHAN | ||
344 | } | ||
345 | |||
346 | /* | ||
347 | * SEQ Done SCB Queue Offset | ||
348 | */ | ||
349 | register SDSCB_QOFF { | ||
350 | address 0x014 | ||
351 | access_mode RW | ||
352 | modes M_CCHAN | ||
353 | size 2 | ||
354 | } | ||
355 | |||
356 | /* | ||
357 | * Queue Offset Control & Status | ||
358 | */ | ||
359 | register QOFF_CTLSTA { | ||
360 | address 0x016 | ||
361 | access_mode RW | ||
362 | modes M_CCHAN | ||
363 | field EMPTY_SCB_AVAIL 0x80 | ||
364 | field NEW_SCB_AVAIL 0x40 | ||
365 | field SDSCB_ROLLOVR 0x20 | ||
366 | field HS_MAILBOX_ACT 0x10 | ||
367 | field SCB_QSIZE 0x0F { | ||
368 | SCB_QSIZE_4, | ||
369 | SCB_QSIZE_8, | ||
370 | SCB_QSIZE_16, | ||
371 | SCB_QSIZE_32, | ||
372 | SCB_QSIZE_64, | ||
373 | SCB_QSIZE_128, | ||
374 | SCB_QSIZE_256, | ||
375 | SCB_QSIZE_512, | ||
376 | SCB_QSIZE_1024, | ||
377 | SCB_QSIZE_2048, | ||
378 | SCB_QSIZE_4096, | ||
379 | SCB_QSIZE_8192, | ||
380 | SCB_QSIZE_16384 | ||
381 | } | ||
382 | } | ||
383 | |||
384 | /* | ||
385 | * Interrupt Control | ||
386 | */ | ||
387 | register INTCTL { | ||
388 | address 0x018 | ||
389 | access_mode RW | ||
390 | field SWTMINTMASK 0x80 | ||
391 | field SWTMINTEN 0x40 | ||
392 | field SWTIMER_START 0x20 | ||
393 | field AUTOCLRCMDINT 0x10 | ||
394 | field PCIINTEN 0x08 | ||
395 | field SCSIINTEN 0x04 | ||
396 | field SEQINTEN 0x02 | ||
397 | field SPLTINTEN 0x01 | ||
398 | } | ||
399 | |||
400 | /* | ||
401 | * Data FIFO Control | ||
402 | */ | ||
403 | register DFCNTRL { | ||
404 | address 0x019 | ||
405 | access_mode RW | ||
406 | modes M_DFF0, M_DFF1 | ||
407 | field PRELOADEN 0x80 | ||
408 | field SCSIENWRDIS 0x40 /* Rev B only. */ | ||
409 | field SCSIEN 0x20 | ||
410 | field SCSIENACK 0x20 | ||
411 | field HDMAEN 0x08 | ||
412 | field HDMAENACK 0x08 | ||
413 | field DIRECTION 0x04 | ||
414 | field DIRECTIONACK 0x04 | ||
415 | field FIFOFLUSH 0x02 | ||
416 | field FIFOFLUSHACK 0x02 | ||
417 | field DIRECTIONEN 0x01 | ||
418 | } | ||
419 | |||
420 | /* | ||
421 | * Device Space Command 0 | ||
422 | */ | ||
423 | register DSCOMMAND0 { | ||
424 | address 0x019 | ||
425 | access_mode RW | ||
426 | modes M_CFG | ||
427 | field CACHETHEN 0x80 /* Cache Threshold enable */ | ||
428 | field DPARCKEN 0x40 /* Data Parity Check Enable */ | ||
429 | field MPARCKEN 0x20 /* Memory Parity Check Enable */ | ||
430 | field EXTREQLCK 0x10 /* External Request Lock */ | ||
431 | field DISABLE_TWATE 0x02 /* Rev B or greater */ | ||
432 | field CIOPARCKEN 0x01 /* Internal bus parity error enable */ | ||
433 | } | ||
434 | |||
435 | /* | ||
436 | * Data FIFO Status | ||
437 | */ | ||
438 | register DFSTATUS { | ||
439 | address 0x01A | ||
440 | access_mode RO | ||
441 | modes M_DFF0, M_DFF1 | ||
442 | field PRELOAD_AVAIL 0x80 | ||
443 | field PKT_PRELOAD_AVAIL 0x40 | ||
444 | field MREQPEND 0x10 | ||
445 | field HDONE 0x08 | ||
446 | field DFTHRESH 0x04 | ||
447 | field FIFOFULL 0x02 | ||
448 | field FIFOEMP 0x01 | ||
449 | } | ||
450 | |||
451 | /* | ||
452 | * S/G Cache Pointer | ||
453 | */ | ||
454 | register SG_CACHE_PRE { | ||
455 | address 0x01B | ||
456 | access_mode WO | ||
457 | modes M_DFF0, M_DFF1 | ||
458 | field SG_ADDR_MASK 0xf8 | ||
459 | field ODD_SEG 0x04 | ||
460 | field LAST_SEG 0x02 | ||
461 | } | ||
462 | |||
463 | register SG_CACHE_SHADOW { | ||
464 | address 0x01B | ||
465 | access_mode RO | ||
466 | modes M_DFF0, M_DFF1 | ||
467 | field SG_ADDR_MASK 0xf8 | ||
468 | field ODD_SEG 0x04 | ||
469 | field LAST_SEG 0x02 | ||
470 | field LAST_SEG_DONE 0x01 | ||
471 | } | ||
472 | |||
473 | /* | ||
474 | * Arbiter Control | ||
475 | */ | ||
476 | register ARBCTL { | ||
477 | address 0x01B | ||
478 | access_mode RW | ||
479 | modes M_CFG | ||
480 | field RESET_HARB 0x80 | ||
481 | field RETRY_SWEN 0x08 | ||
482 | field USE_TIME 0x07 | ||
483 | } | ||
484 | |||
485 | /* | ||
486 | * Data Channel Host Address | ||
487 | */ | ||
488 | register HADDR { | ||
489 | address 0x070 | ||
490 | access_mode RW | ||
491 | size 8 | ||
492 | modes M_DFF0, M_DFF1 | ||
493 | } | ||
494 | |||
495 | /* | ||
496 | * Host Overlay DMA Address | ||
497 | */ | ||
498 | register HODMAADR { | ||
499 | address 0x070 | ||
500 | access_mode RW | ||
501 | size 8 | ||
502 | modes M_SCSI | ||
503 | } | ||
504 | |||
505 | /* | ||
506 | * PCI PLL Delay. | ||
507 | */ | ||
508 | register PLLDELAY { | ||
509 | address 0x070 | ||
510 | access_mode RW | ||
511 | size 1 | ||
512 | modes M_CFG | ||
513 | field SPLIT_DROP_REQ 0x80 | ||
514 | } | ||
515 | |||
516 | /* | ||
517 | * Data Channel Host Count | ||
518 | */ | ||
519 | register HCNT { | ||
520 | address 0x078 | ||
521 | access_mode RW | ||
522 | size 3 | ||
523 | modes M_DFF0, M_DFF1 | ||
524 | } | ||
525 | |||
526 | /* | ||
527 | * Host Overlay DMA Count | ||
528 | */ | ||
529 | register HODMACNT { | ||
530 | address 0x078 | ||
531 | access_mode RW | ||
532 | size 2 | ||
533 | modes M_SCSI | ||
534 | } | ||
535 | |||
536 | /* | ||
537 | * Host Overlay DMA Enable | ||
538 | */ | ||
539 | register HODMAEN { | ||
540 | address 0x07A | ||
541 | access_mode RW | ||
542 | modes M_SCSI | ||
543 | } | ||
544 | |||
545 | /* | ||
546 | * Scatter/Gather Host Address | ||
547 | */ | ||
548 | register SGHADDR { | ||
549 | address 0x07C | ||
550 | access_mode RW | ||
551 | size 8 | ||
552 | modes M_DFF0, M_DFF1 | ||
553 | } | ||
554 | |||
555 | /* | ||
556 | * SCB Host Address | ||
557 | */ | ||
558 | register SCBHADDR { | ||
559 | address 0x07C | ||
560 | access_mode RW | ||
561 | size 8 | ||
562 | modes M_CCHAN | ||
563 | } | ||
564 | |||
565 | /* | ||
566 | * Scatter/Gather Host Count | ||
567 | */ | ||
568 | register SGHCNT { | ||
569 | address 0x084 | ||
570 | access_mode RW | ||
571 | modes M_DFF0, M_DFF1 | ||
572 | } | ||
573 | |||
574 | /* | ||
575 | * SCB Host Count | ||
576 | */ | ||
577 | register SCBHCNT { | ||
578 | address 0x084 | ||
579 | access_mode RW | ||
580 | modes M_CCHAN | ||
581 | } | ||
582 | |||
583 | /* | ||
584 | * Data FIFO Threshold | ||
585 | */ | ||
586 | register DFF_THRSH { | ||
587 | address 0x088 | ||
588 | access_mode RW | ||
589 | modes M_CFG | ||
590 | field WR_DFTHRSH 0x70 { | ||
591 | WR_DFTHRSH_MIN, | ||
592 | WR_DFTHRSH_25, | ||
593 | WR_DFTHRSH_50, | ||
594 | WR_DFTHRSH_63, | ||
595 | WR_DFTHRSH_75, | ||
596 | WR_DFTHRSH_85, | ||
597 | WR_DFTHRSH_90, | ||
598 | WR_DFTHRSH_MAX | ||
599 | } | ||
600 | field RD_DFTHRSH 0x07 { | ||
601 | RD_DFTHRSH_MIN, | ||
602 | RD_DFTHRSH_25, | ||
603 | RD_DFTHRSH_50, | ||
604 | RD_DFTHRSH_63, | ||
605 | RD_DFTHRSH_75, | ||
606 | RD_DFTHRSH_85, | ||
607 | RD_DFTHRSH_90, | ||
608 | RD_DFTHRSH_MAX | ||
609 | } | ||
610 | } | ||
611 | |||
612 | /* | ||
613 | * ROM Address | ||
614 | */ | ||
615 | register ROMADDR { | ||
616 | address 0x08A | ||
617 | access_mode RW | ||
618 | size 3 | ||
619 | } | ||
620 | |||
621 | /* | ||
622 | * ROM Control | ||
623 | */ | ||
624 | register ROMCNTRL { | ||
625 | address 0x08D | ||
626 | access_mode RW | ||
627 | field ROMOP 0xE0 | ||
628 | field ROMSPD 0x18 | ||
629 | field REPEAT 0x02 | ||
630 | field RDY 0x01 | ||
631 | } | ||
632 | |||
633 | /* | ||
634 | * ROM Data | ||
635 | */ | ||
636 | register ROMDATA { | ||
637 | address 0x08E | ||
638 | access_mode RW | ||
639 | } | ||
640 | |||
641 | /* | ||
642 | * Data Channel Receive Message 0 | ||
643 | */ | ||
644 | register DCHRXMSG0 { | ||
645 | address 0x090 | ||
646 | access_mode RO | ||
647 | modes M_DFF0, M_DFF1 | ||
648 | field CDNUM 0xF8 | ||
649 | field CFNUM 0x07 | ||
650 | } | ||
651 | |||
652 | /* | ||
653 | * CMC Recieve Message 0 | ||
654 | */ | ||
655 | register CMCRXMSG0 { | ||
656 | address 0x090 | ||
657 | access_mode RO | ||
658 | modes M_CCHAN | ||
659 | field CDNUM 0xF8 | ||
660 | field CFNUM 0x07 | ||
661 | } | ||
662 | |||
663 | /* | ||
664 | * Overlay Recieve Message 0 | ||
665 | */ | ||
666 | register OVLYRXMSG0 { | ||
667 | address 0x090 | ||
668 | access_mode RO | ||
669 | modes M_SCSI | ||
670 | field CDNUM 0xF8 | ||
671 | field CFNUM 0x07 | ||
672 | } | ||
673 | |||
674 | /* | ||
675 | * Relaxed Order Enable | ||
676 | */ | ||
677 | register ROENABLE { | ||
678 | address 0x090 | ||
679 | access_mode RW | ||
680 | modes M_CFG | ||
681 | field MSIROEN 0x20 | ||
682 | field OVLYROEN 0x10 | ||
683 | field CMCROEN 0x08 | ||
684 | field SGROEN 0x04 | ||
685 | field DCH1ROEN 0x02 | ||
686 | field DCH0ROEN 0x01 | ||
687 | } | ||
688 | |||
689 | /* | ||
690 | * Data Channel Receive Message 1 | ||
691 | */ | ||
692 | register DCHRXMSG1 { | ||
693 | address 0x091 | ||
694 | access_mode RO | ||
695 | modes M_DFF0, M_DFF1 | ||
696 | field CBNUM 0xFF | ||
697 | } | ||
698 | |||
699 | /* | ||
700 | * CMC Recieve Message 1 | ||
701 | */ | ||
702 | register CMCRXMSG1 { | ||
703 | address 0x091 | ||
704 | access_mode RO | ||
705 | modes M_CCHAN | ||
706 | field CBNUM 0xFF | ||
707 | } | ||
708 | |||
709 | /* | ||
710 | * Overlay Recieve Message 1 | ||
711 | */ | ||
712 | register OVLYRXMSG1 { | ||
713 | address 0x091 | ||
714 | access_mode RO | ||
715 | modes M_SCSI | ||
716 | field CBNUM 0xFF | ||
717 | } | ||
718 | |||
719 | /* | ||
720 | * No Snoop Enable | ||
721 | */ | ||
722 | register NSENABLE { | ||
723 | address 0x091 | ||
724 | access_mode RW | ||
725 | modes M_CFG | ||
726 | field MSINSEN 0x20 | ||
727 | field OVLYNSEN 0x10 | ||
728 | field CMCNSEN 0x08 | ||
729 | field SGNSEN 0x04 | ||
730 | field DCH1NSEN 0x02 | ||
731 | field DCH0NSEN 0x01 | ||
732 | } | ||
733 | |||
734 | /* | ||
735 | * Data Channel Receive Message 2 | ||
736 | */ | ||
737 | register DCHRXMSG2 { | ||
738 | address 0x092 | ||
739 | access_mode RO | ||
740 | modes M_DFF0, M_DFF1 | ||
741 | field MINDEX 0xFF | ||
742 | } | ||
743 | |||
744 | /* | ||
745 | * CMC Recieve Message 2 | ||
746 | */ | ||
747 | register CMCRXMSG2 { | ||
748 | address 0x092 | ||
749 | access_mode RO | ||
750 | modes M_CCHAN | ||
751 | field MINDEX 0xFF | ||
752 | } | ||
753 | |||
754 | /* | ||
755 | * Overlay Recieve Message 2 | ||
756 | */ | ||
757 | register OVLYRXMSG2 { | ||
758 | address 0x092 | ||
759 | access_mode RO | ||
760 | modes M_SCSI | ||
761 | field MINDEX 0xFF | ||
762 | } | ||
763 | |||
764 | /* | ||
765 | * Outstanding Split Transactions | ||
766 | */ | ||
767 | register OST { | ||
768 | address 0x092 | ||
769 | access_mode RW | ||
770 | modes M_CFG | ||
771 | } | ||
772 | |||
773 | /* | ||
774 | * Data Channel Receive Message 3 | ||
775 | */ | ||
776 | register DCHRXMSG3 { | ||
777 | address 0x093 | ||
778 | access_mode RO | ||
779 | modes M_DFF0, M_DFF1 | ||
780 | field MCLASS 0x0F | ||
781 | } | ||
782 | |||
783 | /* | ||
784 | * CMC Recieve Message 3 | ||
785 | */ | ||
786 | register CMCRXMSG3 { | ||
787 | address 0x093 | ||
788 | access_mode RO | ||
789 | modes M_CCHAN | ||
790 | field MCLASS 0x0F | ||
791 | } | ||
792 | |||
793 | /* | ||
794 | * Overlay Recieve Message 3 | ||
795 | */ | ||
796 | register OVLYRXMSG3 { | ||
797 | address 0x093 | ||
798 | access_mode RO | ||
799 | modes M_SCSI | ||
800 | field MCLASS 0x0F | ||
801 | } | ||
802 | |||
803 | /* | ||
804 | * PCI-X Control | ||
805 | */ | ||
806 | register PCIXCTL { | ||
807 | address 0x093 | ||
808 | access_mode RW | ||
809 | modes M_CFG | ||
810 | field SERRPULSE 0x80 | ||
811 | field UNEXPSCIEN 0x20 | ||
812 | field SPLTSMADIS 0x10 | ||
813 | field SPLTSTADIS 0x08 | ||
814 | field SRSPDPEEN 0x04 | ||
815 | field TSCSERREN 0x02 | ||
816 | field CMPABCDIS 0x01 | ||
817 | } | ||
818 | |||
819 | /* | ||
820 | * CMC Sequencer Byte Count | ||
821 | */ | ||
822 | register CMCSEQBCNT { | ||
823 | address 0x094 | ||
824 | access_mode RO | ||
825 | modes M_CCHAN | ||
826 | } | ||
827 | |||
828 | /* | ||
829 | * Overlay Sequencer Byte Count | ||
830 | */ | ||
831 | register OVLYSEQBCNT { | ||
832 | address 0x094 | ||
833 | access_mode RO | ||
834 | modes M_SCSI | ||
835 | } | ||
836 | |||
837 | /* | ||
838 | * Data Channel Sequencer Byte Count | ||
839 | */ | ||
840 | register DCHSEQBCNT { | ||
841 | address 0x094 | ||
842 | access_mode RO | ||
843 | size 2 | ||
844 | modes M_DFF0, M_DFF1 | ||
845 | } | ||
846 | |||
847 | /* | ||
848 | * Data Channel Split Status 0 | ||
849 | */ | ||
850 | register DCHSPLTSTAT0 { | ||
851 | address 0x096 | ||
852 | access_mode RW | ||
853 | modes M_DFF0, M_DFF1 | ||
854 | field STAETERM 0x80 | ||
855 | field SCBCERR 0x40 | ||
856 | field SCADERR 0x20 | ||
857 | field SCDATBUCKET 0x10 | ||
858 | field CNTNOTCMPLT 0x08 | ||
859 | field RXOVRUN 0x04 | ||
860 | field RXSCEMSG 0x02 | ||
861 | field RXSPLTRSP 0x01 | ||
862 | } | ||
863 | |||
864 | /* | ||
865 | * CMC Split Status 0 | ||
866 | */ | ||
867 | register CMCSPLTSTAT0 { | ||
868 | address 0x096 | ||
869 | access_mode RW | ||
870 | modes M_CCHAN | ||
871 | field STAETERM 0x80 | ||
872 | field SCBCERR 0x40 | ||
873 | field SCADERR 0x20 | ||
874 | field SCDATBUCKET 0x10 | ||
875 | field CNTNOTCMPLT 0x08 | ||
876 | field RXOVRUN 0x04 | ||
877 | field RXSCEMSG 0x02 | ||
878 | field RXSPLTRSP 0x01 | ||
879 | } | ||
880 | |||
881 | /* | ||
882 | * Overlay Split Status 0 | ||
883 | */ | ||
884 | register OVLYSPLTSTAT0 { | ||
885 | address 0x096 | ||
886 | access_mode RW | ||
887 | modes M_SCSI | ||
888 | field STAETERM 0x80 | ||
889 | field SCBCERR 0x40 | ||
890 | field SCADERR 0x20 | ||
891 | field SCDATBUCKET 0x10 | ||
892 | field CNTNOTCMPLT 0x08 | ||
893 | field RXOVRUN 0x04 | ||
894 | field RXSCEMSG 0x02 | ||
895 | field RXSPLTRSP 0x01 | ||
896 | } | ||
897 | |||
898 | /* | ||
899 | * Data Channel Split Status 1 | ||
900 | */ | ||
901 | register DCHSPLTSTAT1 { | ||
902 | address 0x097 | ||
903 | access_mode RW | ||
904 | modes M_DFF0, M_DFF1 | ||
905 | field RXDATABUCKET 0x01 | ||
906 | } | ||
907 | |||
908 | /* | ||
909 | * CMC Split Status 1 | ||
910 | */ | ||
911 | register CMCSPLTSTAT1 { | ||
912 | address 0x097 | ||
913 | access_mode RW | ||
914 | modes M_CCHAN | ||
915 | field RXDATABUCKET 0x01 | ||
916 | } | ||
917 | |||
918 | /* | ||
919 | * Overlay Split Status 1 | ||
920 | */ | ||
921 | register OVLYSPLTSTAT1 { | ||
922 | address 0x097 | ||
923 | access_mode RW | ||
924 | modes M_SCSI | ||
925 | field RXDATABUCKET 0x01 | ||
926 | } | ||
927 | |||
928 | /* | ||
929 | * S/G Receive Message 0 | ||
930 | */ | ||
931 | register SGRXMSG0 { | ||
932 | address 0x098 | ||
933 | access_mode RO | ||
934 | modes M_DFF0, M_DFF1 | ||
935 | field CDNUM 0xF8 | ||
936 | field CFNUM 0x07 | ||
937 | } | ||
938 | |||
939 | /* | ||
940 | * S/G Receive Message 1 | ||
941 | */ | ||
942 | register SGRXMSG1 { | ||
943 | address 0x099 | ||
944 | access_mode RO | ||
945 | modes M_DFF0, M_DFF1 | ||
946 | field CBNUM 0xFF | ||
947 | } | ||
948 | |||
949 | /* | ||
950 | * S/G Receive Message 2 | ||
951 | */ | ||
952 | register SGRXMSG2 { | ||
953 | address 0x09A | ||
954 | access_mode RO | ||
955 | modes M_DFF0, M_DFF1 | ||
956 | field MINDEX 0xFF | ||
957 | } | ||
958 | |||
959 | /* | ||
960 | * S/G Receive Message 3 | ||
961 | */ | ||
962 | register SGRXMSG3 { | ||
963 | address 0x09B | ||
964 | access_mode RO | ||
965 | modes M_DFF0, M_DFF1 | ||
966 | field MCLASS 0x0F | ||
967 | } | ||
968 | |||
969 | /* | ||
970 | * Slave Split Out Address 0 | ||
971 | */ | ||
972 | register SLVSPLTOUTADR0 { | ||
973 | address 0x098 | ||
974 | access_mode RO | ||
975 | modes M_SCSI | ||
976 | field LOWER_ADDR 0x7F | ||
977 | } | ||
978 | |||
979 | /* | ||
980 | * Slave Split Out Address 1 | ||
981 | */ | ||
982 | register SLVSPLTOUTADR1 { | ||
983 | address 0x099 | ||
984 | access_mode RO | ||
985 | modes M_SCSI | ||
986 | field REQ_DNUM 0xF8 | ||
987 | field REQ_FNUM 0x07 | ||
988 | } | ||
989 | |||
990 | /* | ||
991 | * Slave Split Out Address 2 | ||
992 | */ | ||
993 | register SLVSPLTOUTADR2 { | ||
994 | address 0x09A | ||
995 | access_mode RO | ||
996 | modes M_SCSI | ||
997 | field REQ_BNUM 0xFF | ||
998 | } | ||
999 | |||
1000 | /* | ||
1001 | * Slave Split Out Address 3 | ||
1002 | */ | ||
1003 | register SLVSPLTOUTADR3 { | ||
1004 | address 0x09B | ||
1005 | access_mode RO | ||
1006 | modes M_SCSI | ||
1007 | field RLXORD 020 | ||
1008 | field TAG_NUM 0x1F | ||
1009 | } | ||
1010 | |||
1011 | /* | ||
1012 | * SG Sequencer Byte Count | ||
1013 | */ | ||
1014 | register SGSEQBCNT { | ||
1015 | address 0x09C | ||
1016 | access_mode RO | ||
1017 | modes M_DFF0, M_DFF1 | ||
1018 | } | ||
1019 | |||
1020 | /* | ||
1021 | * Slave Split Out Attribute 0 | ||
1022 | */ | ||
1023 | register SLVSPLTOUTATTR0 { | ||
1024 | address 0x09C | ||
1025 | access_mode RO | ||
1026 | modes M_SCSI | ||
1027 | field LOWER_BCNT 0xFF | ||
1028 | } | ||
1029 | |||
1030 | /* | ||
1031 | * Slave Split Out Attribute 1 | ||
1032 | */ | ||
1033 | register SLVSPLTOUTATTR1 { | ||
1034 | address 0x09D | ||
1035 | access_mode RO | ||
1036 | modes M_SCSI | ||
1037 | field CMPLT_DNUM 0xF8 | ||
1038 | field CMPLT_FNUM 0x07 | ||
1039 | } | ||
1040 | |||
1041 | /* | ||
1042 | * Slave Split Out Attribute 2 | ||
1043 | */ | ||
1044 | register SLVSPLTOUTATTR2 { | ||
1045 | address 0x09E | ||
1046 | access_mode RO | ||
1047 | size 2 | ||
1048 | modes M_SCSI | ||
1049 | field CMPLT_BNUM 0xFF | ||
1050 | } | ||
1051 | /* | ||
1052 | * S/G Split Status 0 | ||
1053 | */ | ||
1054 | register SGSPLTSTAT0 { | ||
1055 | address 0x09E | ||
1056 | access_mode RW | ||
1057 | modes M_DFF0, M_DFF1 | ||
1058 | field STAETERM 0x80 | ||
1059 | field SCBCERR 0x40 | ||
1060 | field SCADERR 0x20 | ||
1061 | field SCDATBUCKET 0x10 | ||
1062 | field CNTNOTCMPLT 0x08 | ||
1063 | field RXOVRUN 0x04 | ||
1064 | field RXSCEMSG 0x02 | ||
1065 | field RXSPLTRSP 0x01 | ||
1066 | } | ||
1067 | |||
1068 | /* | ||
1069 | * S/G Split Status 1 | ||
1070 | */ | ||
1071 | register SGSPLTSTAT1 { | ||
1072 | address 0x09F | ||
1073 | access_mode RW | ||
1074 | modes M_DFF0, M_DFF1 | ||
1075 | field RXDATABUCKET 0x01 | ||
1076 | } | ||
1077 | |||
1078 | /* | ||
1079 | * Special Function | ||
1080 | */ | ||
1081 | register SFUNCT { | ||
1082 | address 0x09f | ||
1083 | access_mode RW | ||
1084 | modes M_CFG | ||
1085 | field TEST_GROUP 0xF0 | ||
1086 | field TEST_NUM 0x0F | ||
1087 | } | ||
1088 | |||
1089 | /* | ||
1090 | * Data FIFO 0 PCI Status | ||
1091 | */ | ||
1092 | register DF0PCISTAT { | ||
1093 | address 0x0A0 | ||
1094 | access_mode RW | ||
1095 | modes M_CFG | ||
1096 | field DPE 0x80 | ||
1097 | field SSE 0x40 | ||
1098 | field RMA 0x20 | ||
1099 | field RTA 0x10 | ||
1100 | field SCAAPERR 0x08 | ||
1101 | field RDPERR 0x04 | ||
1102 | field TWATERR 0x02 | ||
1103 | field DPR 0x01 | ||
1104 | } | ||
1105 | |||
1106 | /* | ||
1107 | * Data FIFO 1 PCI Status | ||
1108 | */ | ||
1109 | register DF1PCISTAT { | ||
1110 | address 0x0A1 | ||
1111 | access_mode RW | ||
1112 | modes M_CFG | ||
1113 | field DPE 0x80 | ||
1114 | field SSE 0x40 | ||
1115 | field RMA 0x20 | ||
1116 | field RTA 0x10 | ||
1117 | field SCAAPERR 0x08 | ||
1118 | field RDPERR 0x04 | ||
1119 | field TWATERR 0x02 | ||
1120 | field DPR 0x01 | ||
1121 | } | ||
1122 | |||
1123 | /* | ||
1124 | * S/G PCI Status | ||
1125 | */ | ||
1126 | register SGPCISTAT { | ||
1127 | address 0x0A2 | ||
1128 | access_mode RW | ||
1129 | modes M_CFG | ||
1130 | field DPE 0x80 | ||
1131 | field SSE 0x40 | ||
1132 | field RMA 0x20 | ||
1133 | field RTA 0x10 | ||
1134 | field SCAAPERR 0x08 | ||
1135 | field RDPERR 0x04 | ||
1136 | field DPR 0x01 | ||
1137 | } | ||
1138 | |||
1139 | /* | ||
1140 | * CMC PCI Status | ||
1141 | */ | ||
1142 | register CMCPCISTAT { | ||
1143 | address 0x0A3 | ||
1144 | access_mode RW | ||
1145 | modes M_CFG | ||
1146 | field DPE 0x80 | ||
1147 | field SSE 0x40 | ||
1148 | field RMA 0x20 | ||
1149 | field RTA 0x10 | ||
1150 | field SCAAPERR 0x08 | ||
1151 | field RDPERR 0x04 | ||
1152 | field TWATERR 0x02 | ||
1153 | field DPR 0x01 | ||
1154 | } | ||
1155 | |||
1156 | /* | ||
1157 | * Overlay PCI Status | ||
1158 | */ | ||
1159 | register OVLYPCISTAT { | ||
1160 | address 0x0A4 | ||
1161 | access_mode RW | ||
1162 | modes M_CFG | ||
1163 | field DPE 0x80 | ||
1164 | field SSE 0x40 | ||
1165 | field RMA 0x20 | ||
1166 | field RTA 0x10 | ||
1167 | field SCAAPERR 0x08 | ||
1168 | field RDPERR 0x04 | ||
1169 | field DPR 0x01 | ||
1170 | } | ||
1171 | |||
1172 | /* | ||
1173 | * PCI Status for MSI Master DMA Transfer | ||
1174 | */ | ||
1175 | register MSIPCISTAT { | ||
1176 | address 0x0A6 | ||
1177 | access_mode RW | ||
1178 | modes M_CFG | ||
1179 | field SSE 0x40 | ||
1180 | field RMA 0x20 | ||
1181 | field RTA 0x10 | ||
1182 | field CLRPENDMSI 0x08 | ||
1183 | field TWATERR 0x02 | ||
1184 | field DPR 0x01 | ||
1185 | } | ||
1186 | |||
1187 | /* | ||
1188 | * PCI Status for Target | ||
1189 | */ | ||
1190 | register TARGPCISTAT { | ||
1191 | address 0x0A7 | ||
1192 | access_mode RW | ||
1193 | modes M_CFG | ||
1194 | field DPE 0x80 | ||
1195 | field SSE 0x40 | ||
1196 | field STA 0x08 | ||
1197 | field TWATERR 0x02 | ||
1198 | } | ||
1199 | |||
1200 | /* | ||
1201 | * LQ Packet In | ||
1202 | * The last LQ Packet received | ||
1203 | */ | ||
1204 | register LQIN { | ||
1205 | address 0x020 | ||
1206 | access_mode RW | ||
1207 | size 20 | ||
1208 | modes M_DFF0, M_DFF1, M_SCSI | ||
1209 | } | ||
1210 | |||
1211 | /* | ||
1212 | * SCB Type Pointer | ||
1213 | * SCB offset for Target Mode SCB type information | ||
1214 | */ | ||
1215 | register TYPEPTR { | ||
1216 | address 0x020 | ||
1217 | access_mode RW | ||
1218 | modes M_CFG | ||
1219 | } | ||
1220 | |||
1221 | /* | ||
1222 | * Queue Tag Pointer | ||
1223 | * SCB offset to the Two Byte tag identifier used for target mode. | ||
1224 | */ | ||
1225 | register TAGPTR { | ||
1226 | address 0x021 | ||
1227 | access_mode RW | ||
1228 | modes M_CFG | ||
1229 | } | ||
1230 | |||
1231 | /* | ||
1232 | * Logical Unit Number Pointer | ||
1233 | * SCB offset to the LSB (little endian) of the lun field. | ||
1234 | */ | ||
1235 | register LUNPTR { | ||
1236 | address 0x022 | ||
1237 | access_mode RW | ||
1238 | modes M_CFG | ||
1239 | } | ||
1240 | |||
1241 | /* | ||
1242 | * Data Length Pointer | ||
1243 | * SCB offset for the 4 byte data length field in target mode. | ||
1244 | */ | ||
1245 | register DATALENPTR { | ||
1246 | address 0x023 | ||
1247 | access_mode RW | ||
1248 | modes M_CFG | ||
1249 | } | ||
1250 | |||
1251 | /* | ||
1252 | * Status Length Pointer | ||
1253 | * SCB offset to the two byte status field in target SCBs. | ||
1254 | */ | ||
1255 | register STATLENPTR { | ||
1256 | address 0x024 | ||
1257 | access_mode RW | ||
1258 | modes M_CFG | ||
1259 | } | ||
1260 | |||
1261 | /* | ||
1262 | * Command Length Pointer | ||
1263 | * Scb offset for the CDB length field in initiator SCBs. | ||
1264 | */ | ||
1265 | register CMDLENPTR { | ||
1266 | address 0x025 | ||
1267 | access_mode RW | ||
1268 | modes M_CFG | ||
1269 | } | ||
1270 | |||
1271 | /* | ||
1272 | * Task Attribute Pointer | ||
1273 | * Scb offset for the byte field specifying the attribute byte | ||
1274 | * to be used in command packets. | ||
1275 | */ | ||
1276 | register ATTRPTR { | ||
1277 | address 0x026 | ||
1278 | access_mode RW | ||
1279 | modes M_CFG | ||
1280 | } | ||
1281 | |||
1282 | /* | ||
1283 | * Task Management Flags Pointer | ||
1284 | * Scb offset for the byte field specifying the attribute flags | ||
1285 | * byte to be used in command packets. | ||
1286 | */ | ||
1287 | register FLAGPTR { | ||
1288 | address 0x027 | ||
1289 | access_mode RW | ||
1290 | modes M_CFG | ||
1291 | } | ||
1292 | |||
1293 | /* | ||
1294 | * Command Pointer | ||
1295 | * Scb offset for the first byte in the CDB for initiator SCBs. | ||
1296 | */ | ||
1297 | register CMDPTR { | ||
1298 | address 0x028 | ||
1299 | access_mode RW | ||
1300 | modes M_CFG | ||
1301 | } | ||
1302 | |||
1303 | /* | ||
1304 | * Queue Next Pointer | ||
1305 | * Scb offset for the 2 byte "next scb link". | ||
1306 | */ | ||
1307 | register QNEXTPTR { | ||
1308 | address 0x029 | ||
1309 | access_mode RW | ||
1310 | modes M_CFG | ||
1311 | } | ||
1312 | |||
1313 | /* | ||
1314 | * SCSI ID Pointer | ||
1315 | * Scb offset to the value to place in the SCSIID register | ||
1316 | * during target mode connections. | ||
1317 | */ | ||
1318 | register IDPTR { | ||
1319 | address 0x02A | ||
1320 | access_mode RW | ||
1321 | modes M_CFG | ||
1322 | } | ||
1323 | |||
1324 | /* | ||
1325 | * Command Aborted Byte Pointer | ||
1326 | * Offset to the SCB flags field that includes the | ||
1327 | * "SCB aborted" status bit. | ||
1328 | */ | ||
1329 | register ABRTBYTEPTR { | ||
1330 | address 0x02B | ||
1331 | access_mode RW | ||
1332 | modes M_CFG | ||
1333 | } | ||
1334 | |||
1335 | /* | ||
1336 | * Command Aborted Bit Pointer | ||
1337 | * Bit offset in the SCB flags field for "SCB aborted" status. | ||
1338 | */ | ||
1339 | register ABRTBITPTR { | ||
1340 | address 0x02C | ||
1341 | access_mode RW | ||
1342 | modes M_CFG | ||
1343 | } | ||
1344 | |||
1345 | /* | ||
1346 | * Rev B or greater. | ||
1347 | */ | ||
1348 | register MAXCMDBYTES { | ||
1349 | address 0x02D | ||
1350 | access_mode RW | ||
1351 | modes M_CFG | ||
1352 | } | ||
1353 | |||
1354 | /* | ||
1355 | * Rev B or greater. | ||
1356 | */ | ||
1357 | register MAXCMD2RCV { | ||
1358 | address 0x02E | ||
1359 | access_mode RW | ||
1360 | modes M_CFG | ||
1361 | } | ||
1362 | |||
1363 | /* | ||
1364 | * Rev B or greater. | ||
1365 | */ | ||
1366 | register SHORTTHRESH { | ||
1367 | address 0x02F | ||
1368 | access_mode RW | ||
1369 | modes M_CFG | ||
1370 | } | ||
1371 | |||
1372 | /* | ||
1373 | * Logical Unit Number Length | ||
1374 | * The length, in bytes, of the SCB lun field. | ||
1375 | */ | ||
1376 | register LUNLEN { | ||
1377 | address 0x030 | ||
1378 | access_mode RW | ||
1379 | modes M_CFG | ||
1380 | mask ILUNLEN 0x0F | ||
1381 | mask TLUNLEN 0xF0 | ||
1382 | } | ||
1383 | const LUNLEN_SINGLE_LEVEL_LUN 0xF | ||
1384 | |||
1385 | /* | ||
1386 | * CDB Limit | ||
1387 | * The size, in bytes, of the embedded CDB field in initator SCBs. | ||
1388 | */ | ||
1389 | register CDBLIMIT { | ||
1390 | address 0x031 | ||
1391 | access_mode RW | ||
1392 | modes M_CFG | ||
1393 | } | ||
1394 | |||
1395 | /* | ||
1396 | * Maximum Commands | ||
1397 | * The maximum number of commands to issue during a | ||
1398 | * single packetized connection. | ||
1399 | */ | ||
1400 | register MAXCMD { | ||
1401 | address 0x032 | ||
1402 | access_mode RW | ||
1403 | modes M_CFG | ||
1404 | } | ||
1405 | |||
1406 | /* | ||
1407 | * Maximum Command Counter | ||
1408 | * The number of commands already sent during this connection | ||
1409 | */ | ||
1410 | register MAXCMDCNT { | ||
1411 | address 0x033 | ||
1412 | access_mode RW | ||
1413 | modes M_CFG | ||
1414 | } | ||
1415 | |||
1416 | /* | ||
1417 | * LQ Packet Reserved Bytes | ||
1418 | * The bytes to be sent in the currently reserved fileds | ||
1419 | * of all LQ packets. | ||
1420 | */ | ||
1421 | register LQRSVD01 { | ||
1422 | address 0x034 | ||
1423 | access_mode RW | ||
1424 | modes M_SCSI | ||
1425 | } | ||
1426 | register LQRSVD16 { | ||
1427 | address 0x035 | ||
1428 | access_mode RW | ||
1429 | modes M_SCSI | ||
1430 | } | ||
1431 | register LQRSVD17 { | ||
1432 | address 0x036 | ||
1433 | access_mode RW | ||
1434 | modes M_SCSI | ||
1435 | } | ||
1436 | |||
1437 | /* | ||
1438 | * Command Reserved 0 | ||
1439 | * The byte to be sent for the reserved byte 0 of | ||
1440 | * outgoing command packets. | ||
1441 | */ | ||
1442 | register CMDRSVD0 { | ||
1443 | address 0x037 | ||
1444 | access_mode RW | ||
1445 | modes M_CFG | ||
1446 | } | ||
1447 | |||
1448 | /* | ||
1449 | * LQ Manager Control 0 | ||
1450 | */ | ||
1451 | register LQCTL0 { | ||
1452 | address 0x038 | ||
1453 | access_mode RW | ||
1454 | modes M_CFG | ||
1455 | field LQITARGCLT 0xC0 | ||
1456 | field LQIINITGCLT 0x30 | ||
1457 | field LQ0TARGCLT 0x0C | ||
1458 | field LQ0INITGCLT 0x03 | ||
1459 | } | ||
1460 | |||
1461 | /* | ||
1462 | * LQ Manager Control 1 | ||
1463 | */ | ||
1464 | register LQCTL1 { | ||
1465 | address 0x038 | ||
1466 | access_mode RW | ||
1467 | modes M_DFF0, M_DFF1, M_SCSI | ||
1468 | field PCI2PCI 0x04 | ||
1469 | field SINGLECMD 0x02 | ||
1470 | field ABORTPENDING 0x01 | ||
1471 | } | ||
1472 | |||
1473 | /* | ||
1474 | * LQ Manager Control 2 | ||
1475 | */ | ||
1476 | register LQCTL2 { | ||
1477 | address 0x039 | ||
1478 | access_mode RW | ||
1479 | modes M_DFF0, M_DFF1, M_SCSI | ||
1480 | field LQIRETRY 0x80 | ||
1481 | field LQICONTINUE 0x40 | ||
1482 | field LQITOIDLE 0x20 | ||
1483 | field LQIPAUSE 0x10 | ||
1484 | field LQORETRY 0x08 | ||
1485 | field LQOCONTINUE 0x04 | ||
1486 | field LQOTOIDLE 0x02 | ||
1487 | field LQOPAUSE 0x01 | ||
1488 | } | ||
1489 | |||
1490 | /* | ||
1491 | * SCSI RAM BIST0 | ||
1492 | */ | ||
1493 | register SCSBIST0 { | ||
1494 | address 0x039 | ||
1495 | access_mode RW | ||
1496 | modes M_CFG | ||
1497 | field GSBISTERR 0x40 | ||
1498 | field GSBISTDONE 0x20 | ||
1499 | field GSBISTRUN 0x10 | ||
1500 | field OSBISTERR 0x04 | ||
1501 | field OSBISTDONE 0x02 | ||
1502 | field OSBISTRUN 0x01 | ||
1503 | } | ||
1504 | |||
1505 | /* | ||
1506 | * SCSI Sequence Control0 | ||
1507 | */ | ||
1508 | register SCSISEQ0 { | ||
1509 | address 0x03A | ||
1510 | access_mode RW | ||
1511 | modes M_DFF0, M_DFF1, M_SCSI | ||
1512 | field TEMODEO 0x80 | ||
1513 | field ENSELO 0x40 | ||
1514 | field ENARBO 0x20 | ||
1515 | field FORCEBUSFREE 0x10 | ||
1516 | field SCSIRSTO 0x01 | ||
1517 | } | ||
1518 | |||
1519 | /* | ||
1520 | * SCSI RAM BIST 1 | ||
1521 | */ | ||
1522 | register SCSBIST1 { | ||
1523 | address 0x03A | ||
1524 | access_mode RW | ||
1525 | modes M_CFG | ||
1526 | field NTBISTERR 0x04 | ||
1527 | field NTBISTDONE 0x02 | ||
1528 | field NTBISTRUN 0x01 | ||
1529 | } | ||
1530 | |||
1531 | /* | ||
1532 | * SCSI Sequence Control 1 | ||
1533 | */ | ||
1534 | register SCSISEQ1 { | ||
1535 | address 0x03B | ||
1536 | access_mode RW | ||
1537 | modes M_DFF0, M_DFF1, M_SCSI | ||
1538 | field MANUALCTL 0x40 | ||
1539 | field ENSELI 0x20 | ||
1540 | field ENRSELI 0x10 | ||
1541 | field MANUALP 0x0C | ||
1542 | field ENAUTOATNP 0x02 | ||
1543 | field ALTSTIM 0x01 | ||
1544 | } | ||
1545 | |||
1546 | /* | ||
1547 | * SCSI Transfer Control 0 | ||
1548 | */ | ||
1549 | register SXFRCTL0 { | ||
1550 | address 0x03C | ||
1551 | access_mode RW | ||
1552 | modes M_SCSI | ||
1553 | field DFON 0x80 | ||
1554 | field DFPEXP 0x40 | ||
1555 | field BIOSCANCELEN 0x10 | ||
1556 | field SPIOEN 0x08 | ||
1557 | } | ||
1558 | |||
1559 | /* | ||
1560 | * SCSI Transfer Control 1 | ||
1561 | */ | ||
1562 | register SXFRCTL1 { | ||
1563 | address 0x03D | ||
1564 | access_mode RW | ||
1565 | modes M_SCSI | ||
1566 | field BITBUCKET 0x80 | ||
1567 | field ENSACHK 0x40 | ||
1568 | field ENSPCHK 0x20 | ||
1569 | field STIMESEL 0x18 | ||
1570 | field ENSTIMER 0x04 | ||
1571 | field ACTNEGEN 0x02 | ||
1572 | field STPWEN 0x01 | ||
1573 | } | ||
1574 | |||
1575 | /* | ||
1576 | * SCSI Transfer Control 2 | ||
1577 | */ | ||
1578 | register SXFRCTL2 { | ||
1579 | address 0x03E | ||
1580 | access_mode RW | ||
1581 | modes M_SCSI | ||
1582 | field AUTORSTDIS 0x10 | ||
1583 | field CMDDMAEN 0x08 | ||
1584 | field ASU 0x07 | ||
1585 | } | ||
1586 | |||
1587 | /* | ||
1588 | * SCSI Bus Initiator IDs | ||
1589 | * Bitmask of observed initiators on the bus. | ||
1590 | */ | ||
1591 | register BUSINITID { | ||
1592 | address 0x03C | ||
1593 | access_mode RW | ||
1594 | modes M_CFG | ||
1595 | size 2 | ||
1596 | } | ||
1597 | |||
1598 | /* | ||
1599 | * Data Length Counters | ||
1600 | * Packet byte counter. | ||
1601 | */ | ||
1602 | register DLCOUNT { | ||
1603 | address 0x03C | ||
1604 | access_mode RW | ||
1605 | modes M_DFF0, M_DFF1 | ||
1606 | size 3 | ||
1607 | } | ||
1608 | |||
1609 | /* | ||
1610 | * Data FIFO Status | ||
1611 | */ | ||
1612 | register DFFSTAT { | ||
1613 | address 0x03F | ||
1614 | access_mode RW | ||
1615 | modes M_SCSI | ||
1616 | field FIFO1FREE 0x20 | ||
1617 | field FIFO0FREE 0x10 | ||
1618 | /* | ||
1619 | * On the B, this enum only works | ||
1620 | * in the read direction. For writes, | ||
1621 | * you must use the B version of the | ||
1622 | * CURRFIFO_0 definition which is defined | ||
1623 | * as a constant outside of this register | ||
1624 | * definition to avoid confusing the | ||
1625 | * register pretty printing code. | ||
1626 | */ | ||
1627 | enum CURRFIFO 0x03 { | ||
1628 | CURRFIFO_0, | ||
1629 | CURRFIFO_1, | ||
1630 | CURRFIFO_NONE 0x3 | ||
1631 | } | ||
1632 | } | ||
1633 | |||
1634 | const B_CURRFIFO_0 0x2 | ||
1635 | |||
1636 | /* | ||
1637 | * SCSI Bus Target IDs | ||
1638 | * Bitmask of observed targets on the bus. | ||
1639 | */ | ||
1640 | register BUSTARGID { | ||
1641 | address 0x03E | ||
1642 | access_mode RW | ||
1643 | modes M_CFG | ||
1644 | size 2 | ||
1645 | } | ||
1646 | |||
1647 | /* | ||
1648 | * SCSI Control Signal Out | ||
1649 | */ | ||
1650 | register SCSISIGO { | ||
1651 | address 0x040 | ||
1652 | access_mode RW | ||
1653 | modes M_DFF0, M_DFF1, M_SCSI | ||
1654 | field CDO 0x80 | ||
1655 | field IOO 0x40 | ||
1656 | field MSGO 0x20 | ||
1657 | field ATNO 0x10 | ||
1658 | field SELO 0x08 | ||
1659 | field BSYO 0x04 | ||
1660 | field REQO 0x02 | ||
1661 | field ACKO 0x01 | ||
1662 | /* | ||
1663 | * Possible phases to write into SCSISIG0 | ||
1664 | */ | ||
1665 | enum PHASE_MASK CDO|IOO|MSGO { | ||
1666 | P_DATAOUT 0x0, | ||
1667 | P_DATAIN IOO, | ||
1668 | P_DATAOUT_DT P_DATAOUT|MSGO, | ||
1669 | P_DATAIN_DT P_DATAIN|MSGO, | ||
1670 | P_COMMAND CDO, | ||
1671 | P_MESGOUT CDO|MSGO, | ||
1672 | P_STATUS CDO|IOO, | ||
1673 | P_MESGIN CDO|IOO|MSGO | ||
1674 | } | ||
1675 | } | ||
1676 | |||
1677 | register SCSISIGI { | ||
1678 | address 0x041 | ||
1679 | access_mode RO | ||
1680 | modes M_DFF0, M_DFF1, M_SCSI | ||
1681 | field CDI 0x80 | ||
1682 | field IOI 0x40 | ||
1683 | field MSGI 0x20 | ||
1684 | field ATNI 0x10 | ||
1685 | field SELI 0x08 | ||
1686 | field BSYI 0x04 | ||
1687 | field REQI 0x02 | ||
1688 | field ACKI 0x01 | ||
1689 | /* | ||
1690 | * Possible phases in SCSISIGI | ||
1691 | */ | ||
1692 | enum PHASE_MASK CDO|IOO|MSGO { | ||
1693 | P_DATAOUT 0x0, | ||
1694 | P_DATAIN IOO, | ||
1695 | P_DATAOUT_DT P_DATAOUT|MSGO, | ||
1696 | P_DATAIN_DT P_DATAIN|MSGO, | ||
1697 | P_COMMAND CDO, | ||
1698 | P_MESGOUT CDO|MSGO, | ||
1699 | P_STATUS CDO|IOO, | ||
1700 | P_MESGIN CDO|IOO|MSGO | ||
1701 | } | ||
1702 | } | ||
1703 | |||
1704 | /* | ||
1705 | * Multiple Target IDs | ||
1706 | * Bitmask of ids to respond as a target. | ||
1707 | */ | ||
1708 | register MULTARGID { | ||
1709 | address 0x040 | ||
1710 | access_mode RW | ||
1711 | modes M_CFG | ||
1712 | size 2 | ||
1713 | } | ||
1714 | |||
1715 | /* | ||
1716 | * SCSI Phase | ||
1717 | */ | ||
1718 | register SCSIPHASE { | ||
1719 | address 0x042 | ||
1720 | access_mode RO | ||
1721 | modes M_DFF0, M_DFF1, M_SCSI | ||
1722 | field STATUS_PHASE 0x20 | ||
1723 | field COMMAND_PHASE 0x10 | ||
1724 | field MSG_IN_PHASE 0x08 | ||
1725 | field MSG_OUT_PHASE 0x04 | ||
1726 | field DATA_PHASE_MASK 0x03 { | ||
1727 | DATA_OUT_PHASE 0x01, | ||
1728 | DATA_IN_PHASE 0x02 | ||
1729 | } | ||
1730 | } | ||
1731 | |||
1732 | /* | ||
1733 | * SCSI Data 0 Image | ||
1734 | */ | ||
1735 | register SCSIDAT0_IMG { | ||
1736 | address 0x043 | ||
1737 | access_mode RW | ||
1738 | modes M_DFF0, M_DFF1, M_SCSI | ||
1739 | } | ||
1740 | |||
1741 | /* | ||
1742 | * SCSI Latched Data | ||
1743 | */ | ||
1744 | register SCSIDAT { | ||
1745 | address 0x044 | ||
1746 | access_mode RW | ||
1747 | modes M_DFF0, M_DFF1, M_SCSI | ||
1748 | size 2 | ||
1749 | } | ||
1750 | |||
1751 | /* | ||
1752 | * SCSI Data Bus | ||
1753 | */ | ||
1754 | register SCSIBUS { | ||
1755 | address 0x046 | ||
1756 | access_mode RW | ||
1757 | modes M_DFF0, M_DFF1, M_SCSI | ||
1758 | size 2 | ||
1759 | } | ||
1760 | |||
1761 | /* | ||
1762 | * Target ID In | ||
1763 | */ | ||
1764 | register TARGIDIN { | ||
1765 | address 0x048 | ||
1766 | access_mode RO | ||
1767 | modes M_DFF0, M_DFF1, M_SCSI | ||
1768 | field CLKOUT 0x80 | ||
1769 | field TARGID 0x0F | ||
1770 | } | ||
1771 | |||
1772 | /* | ||
1773 | * Selection/Reselection ID | ||
1774 | * Upper four bits are the device id. The ONEBIT is set when the re/selecting | ||
1775 | * device did not set its own ID. | ||
1776 | */ | ||
1777 | register SELID { | ||
1778 | address 0x049 | ||
1779 | access_mode RW | ||
1780 | modes M_DFF0, M_DFF1, M_SCSI | ||
1781 | field SELID_MASK 0xf0 | ||
1782 | field ONEBIT 0x08 | ||
1783 | } | ||
1784 | |||
1785 | /* | ||
1786 | * SCSI Block Control | ||
1787 | * Controls Bus type and channel selection. SELWIDE allows for the | ||
1788 | * coexistence of 8bit and 16bit devices on a wide bus. | ||
1789 | */ | ||
1790 | register SBLKCTL { | ||
1791 | address 0x04A | ||
1792 | access_mode RW | ||
1793 | modes M_DFF0, M_DFF1, M_SCSI | ||
1794 | field DIAGLEDEN 0x80 | ||
1795 | field DIAGLEDON 0x40 | ||
1796 | field ENAB40 0x08 /* LVD transceiver active */ | ||
1797 | field ENAB20 0x04 /* SE/HVD transceiver active */ | ||
1798 | field SELWIDE 0x02 | ||
1799 | } | ||
1800 | |||
1801 | /* | ||
1802 | * Option Mode | ||
1803 | */ | ||
1804 | register OPTIONMODE { | ||
1805 | address 0x04A | ||
1806 | access_mode RW | ||
1807 | modes M_CFG | ||
1808 | field BIOSCANCTL 0x80 | ||
1809 | field AUTOACKEN 0x40 | ||
1810 | field BIASCANCTL 0x20 | ||
1811 | field BUSFREEREV 0x10 | ||
1812 | field ENDGFORMCHK 0x04 | ||
1813 | field AUTO_MSGOUT_DE 0x02 | ||
1814 | mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE | ||
1815 | } | ||
1816 | |||
1817 | /* | ||
1818 | * SCSI Status 0 | ||
1819 | */ | ||
1820 | register SSTAT0 { | ||
1821 | address 0x04B | ||
1822 | access_mode RO | ||
1823 | modes M_DFF0, M_DFF1, M_SCSI | ||
1824 | field TARGET 0x80 /* Board acting as target */ | ||
1825 | field SELDO 0x40 /* Selection Done */ | ||
1826 | field SELDI 0x20 /* Board has been selected */ | ||
1827 | field SELINGO 0x10 /* Selection In Progress */ | ||
1828 | field IOERR 0x08 /* LVD Tranceiver mode changed */ | ||
1829 | field OVERRUN 0x04 /* SCSI Offset overrun detected */ | ||
1830 | field SPIORDY 0x02 /* SCSI PIO Ready */ | ||
1831 | field ARBDO 0x01 /* Arbitration Done Out */ | ||
1832 | } | ||
1833 | |||
1834 | /* | ||
1835 | * Clear SCSI Interrupt 0 | ||
1836 | * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. | ||
1837 | */ | ||
1838 | register CLRSINT0 { | ||
1839 | address 0x04B | ||
1840 | access_mode WO | ||
1841 | modes M_DFF0, M_DFF1, M_SCSI | ||
1842 | field CLRSELDO 0x40 | ||
1843 | field CLRSELDI 0x20 | ||
1844 | field CLRSELINGO 0x10 | ||
1845 | field CLRIOERR 0x08 | ||
1846 | field CLROVERRUN 0x04 | ||
1847 | field CLRSPIORDY 0x02 | ||
1848 | field CLRARBDO 0x01 | ||
1849 | } | ||
1850 | |||
1851 | /* | ||
1852 | * SCSI Interrupt Mode 0 | ||
1853 | * Setting any bit will enable the corresponding function | ||
1854 | * in SIMODE0 to interrupt via the IRQ pin. | ||
1855 | */ | ||
1856 | register SIMODE0 { | ||
1857 | address 0x04B | ||
1858 | access_mode RW | ||
1859 | modes M_CFG | ||
1860 | field ENSELDO 0x40 | ||
1861 | field ENSELDI 0x20 | ||
1862 | field ENSELINGO 0x10 | ||
1863 | field ENIOERR 0x08 | ||
1864 | field ENOVERRUN 0x04 | ||
1865 | field ENSPIORDY 0x02 | ||
1866 | field ENARBDO 0x01 | ||
1867 | } | ||
1868 | |||
1869 | /* | ||
1870 | * SCSI Status 1 | ||
1871 | */ | ||
1872 | register SSTAT1 { | ||
1873 | address 0x04C | ||
1874 | access_mode RO | ||
1875 | modes M_DFF0, M_DFF1, M_SCSI | ||
1876 | field SELTO 0x80 | ||
1877 | field ATNTARG 0x40 | ||
1878 | field SCSIRSTI 0x20 | ||
1879 | field PHASEMIS 0x10 | ||
1880 | field BUSFREE 0x08 | ||
1881 | field SCSIPERR 0x04 | ||
1882 | field STRB2FAST 0x02 | ||
1883 | field REQINIT 0x01 | ||
1884 | } | ||
1885 | |||
1886 | /* | ||
1887 | * Clear SCSI Interrupt 1 | ||
1888 | * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. | ||
1889 | */ | ||
1890 | register CLRSINT1 { | ||
1891 | address 0x04C | ||
1892 | access_mode WO | ||
1893 | modes M_DFF0, M_DFF1, M_SCSI | ||
1894 | field CLRSELTIMEO 0x80 | ||
1895 | field CLRATNO 0x40 | ||
1896 | field CLRSCSIRSTI 0x20 | ||
1897 | field CLRBUSFREE 0x08 | ||
1898 | field CLRSCSIPERR 0x04 | ||
1899 | field CLRSTRB2FAST 0x02 | ||
1900 | field CLRREQINIT 0x01 | ||
1901 | } | ||
1902 | |||
1903 | /* | ||
1904 | * SCSI Status 2 | ||
1905 | */ | ||
1906 | register SSTAT2 { | ||
1907 | address 0x04d | ||
1908 | access_mode RO | ||
1909 | modes M_DFF0, M_DFF1, M_SCSI | ||
1910 | field BUSFREETIME 0xc0 { | ||
1911 | BUSFREE_LQO 0x40, | ||
1912 | BUSFREE_DFF0 0x80, | ||
1913 | BUSFREE_DFF1 0xC0 | ||
1914 | } | ||
1915 | field NONPACKREQ 0x20 | ||
1916 | field EXP_ACTIVE 0x10 /* SCSI Expander Active */ | ||
1917 | field BSYX 0x08 /* Busy Expander */ | ||
1918 | field WIDE_RES 0x04 /* Modes 0 and 1 only */ | ||
1919 | field SDONE 0x02 /* Modes 0 and 1 only */ | ||
1920 | field DMADONE 0x01 /* Modes 0 and 1 only */ | ||
1921 | } | ||
1922 | |||
1923 | /* | ||
1924 | * Clear SCSI Interrupt 2 | ||
1925 | */ | ||
1926 | register CLRSINT2 { | ||
1927 | address 0x04D | ||
1928 | access_mode WO | ||
1929 | modes M_DFF0, M_DFF1, M_SCSI | ||
1930 | field CLRNONPACKREQ 0x20 | ||
1931 | field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ | ||
1932 | field CLRSDONE 0x02 /* Modes 0 and 1 only */ | ||
1933 | field CLRDMADONE 0x01 /* Modes 0 and 1 only */ | ||
1934 | } | ||
1935 | |||
1936 | /* | ||
1937 | * SCSI Interrupt Mode 2 | ||
1938 | */ | ||
1939 | register SIMODE2 { | ||
1940 | address 0x04D | ||
1941 | access_mode RW | ||
1942 | modes M_CFG | ||
1943 | field ENWIDE_RES 0x04 | ||
1944 | field ENSDONE 0x02 | ||
1945 | field ENDMADONE 0x01 | ||
1946 | } | ||
1947 | |||
1948 | /* | ||
1949 | * Physical Error Diagnosis | ||
1950 | */ | ||
1951 | register PERRDIAG { | ||
1952 | address 0x04E | ||
1953 | access_mode RO | ||
1954 | modes M_DFF0, M_DFF1, M_SCSI | ||
1955 | field HIZERO 0x80 | ||
1956 | field HIPERR 0x40 | ||
1957 | field PREVPHASE 0x20 | ||
1958 | field PARITYERR 0x10 | ||
1959 | field AIPERR 0x08 | ||
1960 | field CRCERR 0x04 | ||
1961 | field DGFORMERR 0x02 | ||
1962 | field DTERR 0x01 | ||
1963 | } | ||
1964 | |||
1965 | /* | ||
1966 | * LQI Manager Current State | ||
1967 | */ | ||
1968 | register LQISTATE { | ||
1969 | address 0x04E | ||
1970 | access_mode RO | ||
1971 | modes M_CFG | ||
1972 | } | ||
1973 | |||
1974 | /* | ||
1975 | * SCSI Offset Count | ||
1976 | */ | ||
1977 | register SOFFCNT { | ||
1978 | address 0x04F | ||
1979 | access_mode RO | ||
1980 | modes M_DFF0, M_DFF1, M_SCSI | ||
1981 | } | ||
1982 | |||
1983 | /* | ||
1984 | * LQO Manager Current State | ||
1985 | */ | ||
1986 | register LQOSTATE { | ||
1987 | address 0x04F | ||
1988 | access_mode RO | ||
1989 | modes M_CFG | ||
1990 | } | ||
1991 | |||
1992 | /* | ||
1993 | * LQI Manager Status | ||
1994 | */ | ||
1995 | register LQISTAT0 { | ||
1996 | address 0x050 | ||
1997 | access_mode RO | ||
1998 | modes M_DFF0, M_DFF1, M_SCSI | ||
1999 | field LQIATNQAS 0x20 | ||
2000 | field LQICRCT1 0x10 | ||
2001 | field LQICRCT2 0x08 | ||
2002 | field LQIBADLQT 0x04 | ||
2003 | field LQIATNLQ 0x02 | ||
2004 | field LQIATNCMD 0x01 | ||
2005 | } | ||
2006 | |||
2007 | /* | ||
2008 | * Clear LQI Interrupts 0 | ||
2009 | */ | ||
2010 | register CLRLQIINT0 { | ||
2011 | address 0x050 | ||
2012 | access_mode WO | ||
2013 | modes M_DFF0, M_DFF1, M_SCSI | ||
2014 | field CLRLQIATNQAS 0x20 | ||
2015 | field CLRLQICRCT1 0x10 | ||
2016 | field CLRLQICRCT2 0x08 | ||
2017 | field CLRLQIBADLQT 0x04 | ||
2018 | field CLRLQIATNLQ 0x02 | ||
2019 | field CLRLQIATNCMD 0x01 | ||
2020 | } | ||
2021 | |||
2022 | /* | ||
2023 | * LQI Manager Interrupt Mode 0 | ||
2024 | */ | ||
2025 | register LQIMODE0 { | ||
2026 | address 0x050 | ||
2027 | access_mode RW | ||
2028 | modes M_CFG | ||
2029 | field ENLQIATNQASK 0x20 | ||
2030 | field ENLQICRCT1 0x10 | ||
2031 | field ENLQICRCT2 0x08 | ||
2032 | field ENLQIBADLQT 0x04 | ||
2033 | field ENLQIATNLQ 0x02 | ||
2034 | field ENLQIATNCMD 0x01 | ||
2035 | } | ||
2036 | |||
2037 | /* | ||
2038 | * LQI Manager Status 1 | ||
2039 | */ | ||
2040 | register LQISTAT1 { | ||
2041 | address 0x051 | ||
2042 | access_mode RO | ||
2043 | modes M_DFF0, M_DFF1, M_SCSI | ||
2044 | field LQIPHASE_LQ 0x80 | ||
2045 | field LQIPHASE_NLQ 0x40 | ||
2046 | field LQIABORT 0x20 | ||
2047 | field LQICRCI_LQ 0x10 | ||
2048 | field LQICRCI_NLQ 0x08 | ||
2049 | field LQIBADLQI 0x04 | ||
2050 | field LQIOVERI_LQ 0x02 | ||
2051 | field LQIOVERI_NLQ 0x01 | ||
2052 | } | ||
2053 | |||
2054 | /* | ||
2055 | * Clear LQI Manager Interrupts1 | ||
2056 | */ | ||
2057 | register CLRLQIINT1 { | ||
2058 | address 0x051 | ||
2059 | access_mode WO | ||
2060 | modes M_DFF0, M_DFF1, M_SCSI | ||
2061 | field CLRLQIPHASE_LQ 0x80 | ||
2062 | field CLRLQIPHASE_NLQ 0x40 | ||
2063 | field CLRLIQABORT 0x20 | ||
2064 | field CLRLQICRCI_LQ 0x10 | ||
2065 | field CLRLQICRCI_NLQ 0x08 | ||
2066 | field CLRLQIBADLQI 0x04 | ||
2067 | field CLRLQIOVERI_LQ 0x02 | ||
2068 | field CLRLQIOVERI_NLQ 0x01 | ||
2069 | } | ||
2070 | |||
2071 | /* | ||
2072 | * LQI Manager Interrupt Mode 1 | ||
2073 | */ | ||
2074 | register LQIMODE1 { | ||
2075 | address 0x051 | ||
2076 | access_mode RW | ||
2077 | modes M_CFG | ||
2078 | field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ | ||
2079 | field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ | ||
2080 | field ENLIQABORT 0x20 | ||
2081 | field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ | ||
2082 | field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ | ||
2083 | field ENLQIBADLQI 0x04 | ||
2084 | field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ | ||
2085 | field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ | ||
2086 | } | ||
2087 | |||
2088 | /* | ||
2089 | * LQI Manager Status 2 | ||
2090 | */ | ||
2091 | register LQISTAT2 { | ||
2092 | address 0x052 | ||
2093 | access_mode RO | ||
2094 | modes M_DFF0, M_DFF1, M_SCSI | ||
2095 | field PACKETIZED 0x80 | ||
2096 | field LQIPHASE_OUTPKT 0x40 | ||
2097 | field LQIWORKONLQ 0x20 | ||
2098 | field LQIWAITFIFO 0x10 | ||
2099 | field LQISTOPPKT 0x08 | ||
2100 | field LQISTOPLQ 0x04 | ||
2101 | field LQISTOPCMD 0x02 | ||
2102 | field LQIGSAVAIL 0x01 | ||
2103 | } | ||
2104 | |||
2105 | /* | ||
2106 | * SCSI Status 3 | ||
2107 | */ | ||
2108 | register SSTAT3 { | ||
2109 | address 0x053 | ||
2110 | access_mode RO | ||
2111 | modes M_DFF0, M_DFF1, M_SCSI | ||
2112 | field NTRAMPERR 0x02 | ||
2113 | field OSRAMPERR 0x01 | ||
2114 | } | ||
2115 | |||
2116 | /* | ||
2117 | * Clear SCSI Status 3 | ||
2118 | */ | ||
2119 | register CLRSINT3 { | ||
2120 | address 0x053 | ||
2121 | access_mode WO | ||
2122 | modes M_DFF0, M_DFF1, M_SCSI | ||
2123 | field CLRNTRAMPERR 0x02 | ||
2124 | field CLROSRAMPERR 0x01 | ||
2125 | } | ||
2126 | |||
2127 | /* | ||
2128 | * SCSI Interrupt Mode 3 | ||
2129 | */ | ||
2130 | register SIMODE3 { | ||
2131 | address 0x053 | ||
2132 | access_mode RW | ||
2133 | modes M_CFG | ||
2134 | field ENNTRAMPERR 0x02 | ||
2135 | field ENOSRAMPERR 0x01 | ||
2136 | } | ||
2137 | |||
2138 | /* | ||
2139 | * LQO Manager Status 0 | ||
2140 | */ | ||
2141 | register LQOSTAT0 { | ||
2142 | address 0x054 | ||
2143 | access_mode RO | ||
2144 | modes M_DFF0, M_DFF1, M_SCSI | ||
2145 | field LQOTARGSCBPERR 0x10 | ||
2146 | field LQOSTOPT2 0x08 | ||
2147 | field LQOATNLQ 0x04 | ||
2148 | field LQOATNPKT 0x02 | ||
2149 | field LQOTCRC 0x01 | ||
2150 | } | ||
2151 | |||
2152 | /* | ||
2153 | * Clear LQO Manager interrupt 0 | ||
2154 | */ | ||
2155 | register CLRLQOINT0 { | ||
2156 | address 0x054 | ||
2157 | access_mode WO | ||
2158 | modes M_DFF0, M_DFF1, M_SCSI | ||
2159 | field CLRLQOTARGSCBPERR 0x10 | ||
2160 | field CLRLQOSTOPT2 0x08 | ||
2161 | field CLRLQOATNLQ 0x04 | ||
2162 | field CLRLQOATNPKT 0x02 | ||
2163 | field CLRLQOTCRC 0x01 | ||
2164 | } | ||
2165 | |||
2166 | /* | ||
2167 | * LQO Manager Interrupt Mode 0 | ||
2168 | */ | ||
2169 | register LQOMODE0 { | ||
2170 | address 0x054 | ||
2171 | access_mode RW | ||
2172 | modes M_CFG | ||
2173 | field ENLQOTARGSCBPERR 0x10 | ||
2174 | field ENLQOSTOPT2 0x08 | ||
2175 | field ENLQOATNLQ 0x04 | ||
2176 | field ENLQOATNPKT 0x02 | ||
2177 | field ENLQOTCRC 0x01 | ||
2178 | } | ||
2179 | |||
2180 | /* | ||
2181 | * LQO Manager Status 1 | ||
2182 | */ | ||
2183 | register LQOSTAT1 { | ||
2184 | address 0x055 | ||
2185 | access_mode RO | ||
2186 | modes M_DFF0, M_DFF1, M_SCSI | ||
2187 | field LQOINITSCBPERR 0x10 | ||
2188 | field LQOSTOPI2 0x08 | ||
2189 | field LQOBADQAS 0x04 | ||
2190 | field LQOBUSFREE 0x02 | ||
2191 | field LQOPHACHGINPKT 0x01 | ||
2192 | } | ||
2193 | |||
2194 | /* | ||
2195 | * Clear LOQ Interrupt 1 | ||
2196 | */ | ||
2197 | register CLRLQOINT1 { | ||
2198 | address 0x055 | ||
2199 | access_mode WO | ||
2200 | modes M_DFF0, M_DFF1, M_SCSI | ||
2201 | field CLRLQOINITSCBPERR 0x10 | ||
2202 | field CLRLQOSTOPI2 0x08 | ||
2203 | field CLRLQOBADQAS 0x04 | ||
2204 | field CLRLQOBUSFREE 0x02 | ||
2205 | field CLRLQOPHACHGINPKT 0x01 | ||
2206 | } | ||
2207 | |||
2208 | /* | ||
2209 | * LQO Manager Interrupt Mode 1 | ||
2210 | */ | ||
2211 | register LQOMODE1 { | ||
2212 | address 0x055 | ||
2213 | access_mode RW | ||
2214 | modes M_CFG | ||
2215 | field ENLQOINITSCBPERR 0x10 | ||
2216 | field ENLQOSTOPI2 0x08 | ||
2217 | field ENLQOBADQAS 0x04 | ||
2218 | field ENLQOBUSFREE 0x02 | ||
2219 | field ENLQOPHACHGINPKT 0x01 | ||
2220 | } | ||
2221 | |||
2222 | /* | ||
2223 | * LQO Manager Status 2 | ||
2224 | */ | ||
2225 | register LQOSTAT2 { | ||
2226 | address 0x056 | ||
2227 | access_mode RO | ||
2228 | modes M_DFF0, M_DFF1, M_SCSI | ||
2229 | field LQOPKT 0xE0 | ||
2230 | field LQOWAITFIFO 0x10 | ||
2231 | field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ | ||
2232 | field LQOSTOP0 0x01 /* Stopped after sending all packets */ | ||
2233 | } | ||
2234 | |||
2235 | /* | ||
2236 | * Output Synchronizer Space Count | ||
2237 | */ | ||
2238 | register OS_SPACE_CNT { | ||
2239 | address 0x056 | ||
2240 | access_mode RO | ||
2241 | modes M_CFG | ||
2242 | } | ||
2243 | |||
2244 | /* | ||
2245 | * SCSI Interrupt Mode 1 | ||
2246 | * Setting any bit will enable the corresponding function | ||
2247 | * in SIMODE1 to interrupt via the IRQ pin. | ||
2248 | */ | ||
2249 | register SIMODE1 { | ||
2250 | address 0x057 | ||
2251 | access_mode RW | ||
2252 | modes M_DFF0, M_DFF1, M_SCSI | ||
2253 | field ENSELTIMO 0x80 | ||
2254 | field ENATNTARG 0x40 | ||
2255 | field ENSCSIRST 0x20 | ||
2256 | field ENPHASEMIS 0x10 | ||
2257 | field ENBUSFREE 0x08 | ||
2258 | field ENSCSIPERR 0x04 | ||
2259 | field ENSTRB2FAST 0x02 | ||
2260 | field ENREQINIT 0x01 | ||
2261 | } | ||
2262 | |||
2263 | /* | ||
2264 | * Good Status FIFO | ||
2265 | */ | ||
2266 | register GSFIFO { | ||
2267 | address 0x058 | ||
2268 | access_mode RO | ||
2269 | size 2 | ||
2270 | modes M_DFF0, M_DFF1, M_SCSI | ||
2271 | } | ||
2272 | |||
2273 | /* | ||
2274 | * Data FIFO SCSI Transfer Control | ||
2275 | */ | ||
2276 | register DFFSXFRCTL { | ||
2277 | address 0x05A | ||
2278 | access_mode RW | ||
2279 | modes M_DFF0, M_DFF1 | ||
2280 | field DFFBITBUCKET 0x08 | ||
2281 | field CLRSHCNT 0x04 | ||
2282 | field CLRCHN 0x02 | ||
2283 | field RSTCHN 0x01 | ||
2284 | } | ||
2285 | |||
2286 | /* | ||
2287 | * Next SCSI Control Block | ||
2288 | */ | ||
2289 | register NEXTSCB { | ||
2290 | address 0x05A | ||
2291 | access_mode RW | ||
2292 | size 2 | ||
2293 | modes M_SCSI | ||
2294 | } | ||
2295 | |||
2296 | /* Rev B only. */ | ||
2297 | register LQOSCSCTL { | ||
2298 | address 0x05A | ||
2299 | access_mode RW | ||
2300 | size 1 | ||
2301 | modes M_CFG | ||
2302 | field LQOH2A_VERSION 0x80 | ||
2303 | field LQONOCHKOVER 0x01 | ||
2304 | } | ||
2305 | |||
2306 | /* | ||
2307 | * SEQ Interrupts | ||
2308 | */ | ||
2309 | register SEQINTSRC { | ||
2310 | address 0x05B | ||
2311 | access_mode RO | ||
2312 | modes M_DFF0, M_DFF1 | ||
2313 | field CTXTDONE 0x40 | ||
2314 | field SAVEPTRS 0x20 | ||
2315 | field CFG4DATA 0x10 | ||
2316 | field CFG4ISTAT 0x08 | ||
2317 | field CFG4TSTAT 0x04 | ||
2318 | field CFG4ICMD 0x02 | ||
2319 | field CFG4TCMD 0x01 | ||
2320 | } | ||
2321 | |||
2322 | /* | ||
2323 | * Clear Arp Interrupts | ||
2324 | */ | ||
2325 | register CLRSEQINTSRC { | ||
2326 | address 0x05B | ||
2327 | access_mode WO | ||
2328 | modes M_DFF0, M_DFF1 | ||
2329 | field CLRCTXTDONE 0x40 | ||
2330 | field CLRSAVEPTRS 0x20 | ||
2331 | field CLRCFG4DATA 0x10 | ||
2332 | field CLRCFG4ISTAT 0x08 | ||
2333 | field CLRCFG4TSTAT 0x04 | ||
2334 | field CLRCFG4ICMD 0x02 | ||
2335 | field CLRCFG4TCMD 0x01 | ||
2336 | } | ||
2337 | |||
2338 | /* | ||
2339 | * SEQ Interrupt Enabled (Shared) | ||
2340 | */ | ||
2341 | register SEQIMODE { | ||
2342 | address 0x05C | ||
2343 | access_mode RW | ||
2344 | modes M_DFF0, M_DFF1 | ||
2345 | field ENCTXTDONE 0x40 | ||
2346 | field ENSAVEPTRS 0x20 | ||
2347 | field ENCFG4DATA 0x10 | ||
2348 | field ENCFG4ISTAT 0x08 | ||
2349 | field ENCFG4TSTAT 0x04 | ||
2350 | field ENCFG4ICMD 0x02 | ||
2351 | field ENCFG4TCMD 0x01 | ||
2352 | } | ||
2353 | |||
2354 | /* | ||
2355 | * Current SCSI Control Block | ||
2356 | */ | ||
2357 | register CURRSCB { | ||
2358 | address 0x05C | ||
2359 | access_mode RW | ||
2360 | size 2 | ||
2361 | modes M_SCSI | ||
2362 | } | ||
2363 | |||
2364 | /* | ||
2365 | * Data FIFO Status | ||
2366 | */ | ||
2367 | register MDFFSTAT { | ||
2368 | address 0x05D | ||
2369 | access_mode RO | ||
2370 | modes M_DFF0, M_DFF1 | ||
2371 | field SHCNTNEGATIVE 0x40 /* Rev B or higher */ | ||
2372 | field SHCNTMINUS1 0x20 /* Rev B or higher */ | ||
2373 | field LASTSDONE 0x10 | ||
2374 | field SHVALID 0x08 | ||
2375 | field DLZERO 0x04 /* FIFO data ends on packet boundary. */ | ||
2376 | field DATAINFIFO 0x02 | ||
2377 | field FIFOFREE 0x01 | ||
2378 | } | ||
2379 | |||
2380 | /* | ||
2381 | * CRC Control | ||
2382 | */ | ||
2383 | register CRCCONTROL { | ||
2384 | address 0x05d | ||
2385 | access_mode RW | ||
2386 | modes M_CFG | ||
2387 | field CRCVALCHKEN 0x40 | ||
2388 | } | ||
2389 | |||
2390 | /* | ||
2391 | * SCSI Test Control | ||
2392 | */ | ||
2393 | register SCSITEST { | ||
2394 | address 0x05E | ||
2395 | access_mode RW | ||
2396 | modes M_CFG | ||
2397 | field CNTRTEST 0x08 | ||
2398 | field SEL_TXPLL_DEBUG 0x04 | ||
2399 | } | ||
2400 | |||
2401 | /* | ||
2402 | * Data FIFO Queue Tag | ||
2403 | */ | ||
2404 | register DFFTAG { | ||
2405 | address 0x05E | ||
2406 | access_mode RW | ||
2407 | size 2 | ||
2408 | modes M_DFF0, M_DFF1 | ||
2409 | } | ||
2410 | |||
2411 | /* | ||
2412 | * Last SCSI Control Block | ||
2413 | */ | ||
2414 | register LASTSCB { | ||
2415 | address 0x05E | ||
2416 | access_mode RW | ||
2417 | size 2 | ||
2418 | modes M_SCSI | ||
2419 | } | ||
2420 | |||
2421 | /* | ||
2422 | * SCSI I/O Cell Power-down Control | ||
2423 | */ | ||
2424 | register IOPDNCTL { | ||
2425 | address 0x05F | ||
2426 | access_mode RW | ||
2427 | modes M_CFG | ||
2428 | field DISABLE_OE 0x80 | ||
2429 | field PDN_IDIST 0x04 | ||
2430 | field PDN_DIFFSENSE 0x01 | ||
2431 | } | ||
2432 | |||
2433 | /* | ||
2434 | * Shaddow Host Address. | ||
2435 | */ | ||
2436 | register SHADDR { | ||
2437 | address 0x060 | ||
2438 | access_mode RO | ||
2439 | size 8 | ||
2440 | modes M_DFF0, M_DFF1 | ||
2441 | } | ||
2442 | |||
2443 | /* | ||
2444 | * Data Group CRC Interval. | ||
2445 | */ | ||
2446 | register DGRPCRCI { | ||
2447 | address 0x060 | ||
2448 | access_mode RW | ||
2449 | size 2 | ||
2450 | modes M_CFG | ||
2451 | } | ||
2452 | |||
2453 | /* | ||
2454 | * Data Transfer Negotiation Address | ||
2455 | */ | ||
2456 | register NEGOADDR { | ||
2457 | address 0x060 | ||
2458 | access_mode RW | ||
2459 | modes M_SCSI | ||
2460 | } | ||
2461 | |||
2462 | /* | ||
2463 | * Data Transfer Negotiation Data - Period Byte | ||
2464 | */ | ||
2465 | register NEGPERIOD { | ||
2466 | address 0x061 | ||
2467 | access_mode RW | ||
2468 | modes M_SCSI | ||
2469 | } | ||
2470 | |||
2471 | /* | ||
2472 | * Packetized CRC Interval | ||
2473 | */ | ||
2474 | register PACKCRCI { | ||
2475 | address 0x062 | ||
2476 | access_mode RW | ||
2477 | size 2 | ||
2478 | modes M_CFG | ||
2479 | } | ||
2480 | |||
2481 | /* | ||
2482 | * Data Transfer Negotiation Data - Offset Byte | ||
2483 | */ | ||
2484 | register NEGOFFSET { | ||
2485 | address 0x062 | ||
2486 | access_mode RW | ||
2487 | modes M_SCSI | ||
2488 | } | ||
2489 | |||
2490 | /* | ||
2491 | * Data Transfer Negotiation Data - PPR Options | ||
2492 | */ | ||
2493 | register NEGPPROPTS { | ||
2494 | address 0x063 | ||
2495 | access_mode RW | ||
2496 | modes M_SCSI | ||
2497 | field PPROPT_PACE 0x08 | ||
2498 | field PPROPT_QAS 0x04 | ||
2499 | field PPROPT_DT 0x02 | ||
2500 | field PPROPT_IUT 0x01 | ||
2501 | } | ||
2502 | |||
2503 | /* | ||
2504 | * Data Transfer Negotiation Data - Connection Options | ||
2505 | */ | ||
2506 | register NEGCONOPTS { | ||
2507 | address 0x064 | ||
2508 | access_mode RW | ||
2509 | modes M_SCSI | ||
2510 | field ENSNAPSHOT 0x40 | ||
2511 | field RTI_WRTDIS 0x20 | ||
2512 | field RTI_OVRDTRN 0x10 | ||
2513 | field ENSLOWCRC 0x08 | ||
2514 | field ENAUTOATNI 0x04 | ||
2515 | field ENAUTOATNO 0x02 | ||
2516 | field WIDEXFER 0x01 | ||
2517 | } | ||
2518 | |||
2519 | /* | ||
2520 | * Negotiation Table Annex Column Index. | ||
2521 | */ | ||
2522 | register ANNEXCOL { | ||
2523 | address 0x065 | ||
2524 | access_mode RW | ||
2525 | modes M_SCSI | ||
2526 | } | ||
2527 | |||
2528 | register SCSCHKN { | ||
2529 | address 0x066 | ||
2530 | access_mode RW | ||
2531 | modes M_CFG | ||
2532 | field STSELSKIDDIS 0x40 | ||
2533 | field CURRFIFODEF 0x20 | ||
2534 | field WIDERESEN 0x10 | ||
2535 | field SDONEMSKDIS 0x08 | ||
2536 | field DFFACTCLR 0x04 | ||
2537 | field SHVALIDSTDIS 0x02 | ||
2538 | field LSTSGCLRDIS 0x01 | ||
2539 | } | ||
2540 | |||
2541 | const AHD_ANNEXCOL_PER_DEV0 4 | ||
2542 | const AHD_NUM_PER_DEV_ANNEXCOLS 4 | ||
2543 | const AHD_ANNEXCOL_PRECOMP_SLEW 4 | ||
2544 | const AHD_PRECOMP_MASK 0x07 | ||
2545 | const AHD_PRECOMP_SHIFT 0 | ||
2546 | const AHD_PRECOMP_CUTBACK_17 0x04 | ||
2547 | const AHD_PRECOMP_CUTBACK_29 0x06 | ||
2548 | const AHD_PRECOMP_CUTBACK_37 0x07 | ||
2549 | const AHD_SLEWRATE_MASK 0x78 | ||
2550 | const AHD_SLEWRATE_SHIFT 3 | ||
2551 | /* | ||
2552 | * Rev A has only a single bit (high bit of field) of slew adjustment. | ||
2553 | * Rev B has 4 bits. The current default happens to be the same for both. | ||
2554 | */ | ||
2555 | const AHD_SLEWRATE_DEF_REVA 0x08 | ||
2556 | const AHD_SLEWRATE_DEF_REVB 0x08 | ||
2557 | |||
2558 | /* Rev A does not have any amplitude setting. */ | ||
2559 | const AHD_ANNEXCOL_AMPLITUDE 6 | ||
2560 | const AHD_AMPLITUDE_MASK 0x7 | ||
2561 | const AHD_AMPLITUDE_SHIFT 0 | ||
2562 | const AHD_AMPLITUDE_DEF 0x7 | ||
2563 | |||
2564 | /* | ||
2565 | * Negotiation Table Annex Data Port. | ||
2566 | */ | ||
2567 | register ANNEXDAT { | ||
2568 | address 0x066 | ||
2569 | access_mode RW | ||
2570 | modes M_SCSI | ||
2571 | } | ||
2572 | |||
2573 | /* | ||
2574 | * Initiator's Own Id. | ||
2575 | * The SCSI ID to use for Selection Out and seen during a reselection.. | ||
2576 | */ | ||
2577 | register IOWNID { | ||
2578 | address 0x067 | ||
2579 | access_mode RW | ||
2580 | modes M_SCSI | ||
2581 | } | ||
2582 | |||
2583 | /* | ||
2584 | * 960MHz Phase-Locked Loop Control 0 | ||
2585 | */ | ||
2586 | register PLL960CTL0 { | ||
2587 | address 0x068 | ||
2588 | access_mode RW | ||
2589 | modes M_CFG | ||
2590 | field PLL_VCOSEL 0x80 | ||
2591 | field PLL_PWDN 0x40 | ||
2592 | field PLL_NS 0x30 | ||
2593 | field PLL_ENLUD 0x08 | ||
2594 | field PLL_ENLPF 0x04 | ||
2595 | field PLL_DLPF 0x02 | ||
2596 | field PLL_ENFBM 0x01 | ||
2597 | } | ||
2598 | |||
2599 | /* | ||
2600 | * Target Own Id | ||
2601 | */ | ||
2602 | register TOWNID { | ||
2603 | address 0x069 | ||
2604 | access_mode RW | ||
2605 | modes M_SCSI | ||
2606 | } | ||
2607 | |||
2608 | /* | ||
2609 | * 960MHz Phase-Locked Loop Control 1 | ||
2610 | */ | ||
2611 | register PLL960CTL1 { | ||
2612 | address 0x069 | ||
2613 | access_mode RW | ||
2614 | modes M_CFG | ||
2615 | field PLL_CNTEN 0x80 | ||
2616 | field PLL_CNTCLR 0x40 | ||
2617 | field PLL_RST 0x01 | ||
2618 | } | ||
2619 | |||
2620 | /* | ||
2621 | * Expander Signature | ||
2622 | */ | ||
2623 | register XSIG { | ||
2624 | address 0x06A | ||
2625 | access_mode RW | ||
2626 | modes M_SCSI | ||
2627 | } | ||
2628 | |||
2629 | /* | ||
2630 | * Shadow Byte Count | ||
2631 | */ | ||
2632 | register SHCNT { | ||
2633 | address 0x068 | ||
2634 | access_mode RW | ||
2635 | size 3 | ||
2636 | modes M_DFF0, M_DFF1 | ||
2637 | } | ||
2638 | |||
2639 | /* | ||
2640 | * Selection Out ID | ||
2641 | */ | ||
2642 | register SELOID { | ||
2643 | address 0x06B | ||
2644 | access_mode RW | ||
2645 | modes M_SCSI | ||
2646 | } | ||
2647 | |||
2648 | /* | ||
2649 | * 960-MHz Phase-Locked Loop Test Count | ||
2650 | */ | ||
2651 | register PLL960CNT0 { | ||
2652 | address 0x06A | ||
2653 | access_mode RO | ||
2654 | size 2 | ||
2655 | modes M_CFG | ||
2656 | } | ||
2657 | |||
2658 | /* | ||
2659 | * 400-MHz Phase-Locked Loop Control 0 | ||
2660 | */ | ||
2661 | register PLL400CTL0 { | ||
2662 | address 0x06C | ||
2663 | access_mode RW | ||
2664 | modes M_CFG | ||
2665 | field PLL_VCOSEL 0x80 | ||
2666 | field PLL_PWDN 0x40 | ||
2667 | field PLL_NS 0x30 | ||
2668 | field PLL_ENLUD 0x08 | ||
2669 | field PLL_ENLPF 0x04 | ||
2670 | field PLL_DLPF 0x02 | ||
2671 | field PLL_ENFBM 0x01 | ||
2672 | } | ||
2673 | |||
2674 | /* | ||
2675 | * Arbitration Fairness | ||
2676 | */ | ||
2677 | register FAIRNESS { | ||
2678 | address 0x06C | ||
2679 | access_mode RW | ||
2680 | size 2 | ||
2681 | modes M_SCSI | ||
2682 | } | ||
2683 | |||
2684 | /* | ||
2685 | * 400-MHz Phase-Locked Loop Control 1 | ||
2686 | */ | ||
2687 | register PLL400CTL1 { | ||
2688 | address 0x06D | ||
2689 | access_mode RW | ||
2690 | modes M_CFG | ||
2691 | field PLL_CNTEN 0x80 | ||
2692 | field PLL_CNTCLR 0x40 | ||
2693 | field PLL_RST 0x01 | ||
2694 | } | ||
2695 | |||
2696 | /* | ||
2697 | * Arbitration Unfairness | ||
2698 | */ | ||
2699 | register UNFAIRNESS { | ||
2700 | address 0x06E | ||
2701 | access_mode RW | ||
2702 | size 2 | ||
2703 | modes M_SCSI | ||
2704 | } | ||
2705 | |||
2706 | /* | ||
2707 | * 400-MHz Phase-Locked Loop Test Count | ||
2708 | */ | ||
2709 | register PLL400CNT0 { | ||
2710 | address 0x06E | ||
2711 | access_mode RO | ||
2712 | size 2 | ||
2713 | modes M_CFG | ||
2714 | } | ||
2715 | |||
2716 | /* | ||
2717 | * SCB Page Pointer | ||
2718 | */ | ||
2719 | register SCBPTR { | ||
2720 | address 0x0A8 | ||
2721 | access_mode RW | ||
2722 | size 2 | ||
2723 | modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI | ||
2724 | } | ||
2725 | |||
2726 | /* | ||
2727 | * CMC SCB Array Count | ||
2728 | * Number of bytes to transfer between CMC SCB memory and SCBRAM. | ||
2729 | * Transfers must be 8byte aligned and sized. | ||
2730 | */ | ||
2731 | register CCSCBACNT { | ||
2732 | address 0x0AB | ||
2733 | access_mode RW | ||
2734 | modes M_CCHAN | ||
2735 | } | ||
2736 | |||
2737 | /* | ||
2738 | * SCB Autopointer | ||
2739 | * SCB-Next Address Snooping logic. When an SCB is transferred to | ||
2740 | * the card, the next SCB address to be used by the CMC array can | ||
2741 | * be autoloaded from that transfer. | ||
2742 | */ | ||
2743 | register SCBAUTOPTR { | ||
2744 | address 0x0AB | ||
2745 | access_mode RW | ||
2746 | modes M_CFG | ||
2747 | field AUSCBPTR_EN 0x80 | ||
2748 | field SCBPTR_ADDR 0x38 | ||
2749 | field SCBPTR_OFF 0x07 | ||
2750 | } | ||
2751 | |||
2752 | /* | ||
2753 | * CMC SG Ram Address Pointer | ||
2754 | */ | ||
2755 | register CCSGADDR { | ||
2756 | address 0x0AC | ||
2757 | access_mode RW | ||
2758 | modes M_DFF0, M_DFF1 | ||
2759 | } | ||
2760 | |||
2761 | /* | ||
2762 | * CMC SCB RAM Address Pointer | ||
2763 | */ | ||
2764 | register CCSCBADDR { | ||
2765 | address 0x0AC | ||
2766 | access_mode RW | ||
2767 | modes M_CCHAN | ||
2768 | } | ||
2769 | |||
2770 | /* | ||
2771 | * CMC SCB Ram Back-up Address Pointer | ||
2772 | * Indicates the true stop location of transfers halted prior | ||
2773 | * to SCBHCNT going to 0. | ||
2774 | */ | ||
2775 | register CCSCBADR_BK { | ||
2776 | address 0x0AC | ||
2777 | access_mode RO | ||
2778 | modes M_CFG | ||
2779 | } | ||
2780 | |||
2781 | /* | ||
2782 | * CMC SG Control | ||
2783 | */ | ||
2784 | register CCSGCTL { | ||
2785 | address 0x0AD | ||
2786 | access_mode RW | ||
2787 | modes M_DFF0, M_DFF1 | ||
2788 | field CCSGDONE 0x80 | ||
2789 | field SG_CACHE_AVAIL 0x10 | ||
2790 | field CCSGENACK 0x08 | ||
2791 | mask CCSGEN 0x0C | ||
2792 | field SG_FETCH_REQ 0x02 | ||
2793 | field CCSGRESET 0x01 | ||
2794 | } | ||
2795 | |||
2796 | /* | ||
2797 | * CMD SCB Control | ||
2798 | */ | ||
2799 | register CCSCBCTL { | ||
2800 | address 0x0AD | ||
2801 | access_mode RW | ||
2802 | modes M_CCHAN | ||
2803 | field CCSCBDONE 0x80 | ||
2804 | field ARRDONE 0x40 | ||
2805 | field CCARREN 0x10 | ||
2806 | field CCSCBEN 0x08 | ||
2807 | field CCSCBDIR 0x04 | ||
2808 | field CCSCBRESET 0x01 | ||
2809 | } | ||
2810 | |||
2811 | /* | ||
2812 | * CMC Ram BIST | ||
2813 | */ | ||
2814 | register CMC_RAMBIST { | ||
2815 | address 0x0AD | ||
2816 | access_mode RW | ||
2817 | modes M_CFG | ||
2818 | field SG_ELEMENT_SIZE 0x80 | ||
2819 | field SCBRAMBIST_FAIL 0x40 | ||
2820 | field SG_BIST_FAIL 0x20 | ||
2821 | field SG_BIST_EN 0x10 | ||
2822 | field CMC_BUFFER_BIST_FAIL 0x02 | ||
2823 | field CMC_BUFFER_BIST_EN 0x01 | ||
2824 | } | ||
2825 | |||
2826 | /* | ||
2827 | * CMC SG RAM Data Port | ||
2828 | */ | ||
2829 | register CCSGRAM { | ||
2830 | address 0x0B0 | ||
2831 | access_mode RW | ||
2832 | modes M_DFF0, M_DFF1 | ||
2833 | } | ||
2834 | |||
2835 | /* | ||
2836 | * CMC SCB RAM Data Port | ||
2837 | */ | ||
2838 | register CCSCBRAM { | ||
2839 | address 0x0B0 | ||
2840 | access_mode RW | ||
2841 | modes M_CCHAN | ||
2842 | } | ||
2843 | |||
2844 | /* | ||
2845 | * Flex DMA Address. | ||
2846 | */ | ||
2847 | register FLEXADR { | ||
2848 | address 0x0B0 | ||
2849 | access_mode RW | ||
2850 | size 3 | ||
2851 | modes M_SCSI | ||
2852 | } | ||
2853 | |||
2854 | /* | ||
2855 | * Flex DMA Byte Count | ||
2856 | */ | ||
2857 | register FLEXCNT { | ||
2858 | address 0x0B3 | ||
2859 | access_mode RW | ||
2860 | size 2 | ||
2861 | modes M_SCSI | ||
2862 | } | ||
2863 | |||
2864 | /* | ||
2865 | * Flex DMA Status | ||
2866 | */ | ||
2867 | register FLEXDMASTAT { | ||
2868 | address 0x0B5 | ||
2869 | access_mode RW | ||
2870 | modes M_SCSI | ||
2871 | field FLEXDMAERR 0x02 | ||
2872 | field FLEXDMADONE 0x01 | ||
2873 | } | ||
2874 | |||
2875 | /* | ||
2876 | * Flex DMA Data Port | ||
2877 | */ | ||
2878 | register FLEXDATA { | ||
2879 | address 0x0B6 | ||
2880 | access_mode RW | ||
2881 | modes M_SCSI | ||
2882 | } | ||
2883 | |||
2884 | /* | ||
2885 | * Board Data | ||
2886 | */ | ||
2887 | register BRDDAT { | ||
2888 | address 0x0B8 | ||
2889 | access_mode RW | ||
2890 | modes M_SCSI | ||
2891 | } | ||
2892 | |||
2893 | /* | ||
2894 | * Board Control | ||
2895 | */ | ||
2896 | register BRDCTL { | ||
2897 | address 0x0B9 | ||
2898 | access_mode RW | ||
2899 | modes M_SCSI | ||
2900 | field FLXARBACK 0x80 | ||
2901 | field FLXARBREQ 0x40 | ||
2902 | field BRDADDR 0x38 | ||
2903 | field BRDEN 0x04 | ||
2904 | field BRDRW 0x02 | ||
2905 | field BRDSTB 0x01 | ||
2906 | } | ||
2907 | |||
2908 | /* | ||
2909 | * Serial EEPROM Address | ||
2910 | */ | ||
2911 | register SEEADR { | ||
2912 | address 0x0BA | ||
2913 | access_mode RW | ||
2914 | modes M_SCSI | ||
2915 | } | ||
2916 | |||
2917 | /* | ||
2918 | * Serial EEPROM Data | ||
2919 | */ | ||
2920 | register SEEDAT { | ||
2921 | address 0x0BC | ||
2922 | access_mode RW | ||
2923 | size 2 | ||
2924 | modes M_SCSI | ||
2925 | } | ||
2926 | |||
2927 | /* | ||
2928 | * Serial EEPROM Status | ||
2929 | */ | ||
2930 | register SEESTAT { | ||
2931 | address 0x0BE | ||
2932 | access_mode RO | ||
2933 | modes M_SCSI | ||
2934 | field INIT_DONE 0x80 | ||
2935 | field SEEOPCODE 0x70 | ||
2936 | field LDALTID_L 0x08 | ||
2937 | field SEEARBACK 0x04 | ||
2938 | field SEEBUSY 0x02 | ||
2939 | field SEESTART 0x01 | ||
2940 | } | ||
2941 | |||
2942 | /* | ||
2943 | * Serial EEPROM Control | ||
2944 | */ | ||
2945 | register SEECTL { | ||
2946 | address 0x0BE | ||
2947 | access_mode RW | ||
2948 | modes M_SCSI | ||
2949 | field SEEOPCODE 0x70 { | ||
2950 | SEEOP_ERASE 0x70, | ||
2951 | SEEOP_READ 0x60, | ||
2952 | SEEOP_WRITE 0x50, | ||
2953 | /* | ||
2954 | * The following four commands use special | ||
2955 | * addresses for differentiation. | ||
2956 | */ | ||
2957 | SEEOP_ERAL 0x40 | ||
2958 | } | ||
2959 | mask SEEOP_EWEN 0x40 | ||
2960 | mask SEEOP_WALL 0x40 | ||
2961 | mask SEEOP_EWDS 0x40 | ||
2962 | field SEERST 0x02 | ||
2963 | field SEESTART 0x01 | ||
2964 | } | ||
2965 | |||
2966 | const SEEOP_ERAL_ADDR 0x80 | ||
2967 | const SEEOP_EWEN_ADDR 0xC0 | ||
2968 | const SEEOP_WRAL_ADDR 0x40 | ||
2969 | const SEEOP_EWDS_ADDR 0x00 | ||
2970 | |||
2971 | /* | ||
2972 | * SCB Counter | ||
2973 | */ | ||
2974 | register SCBCNT { | ||
2975 | address 0x0BF | ||
2976 | access_mode RW | ||
2977 | modes M_SCSI | ||
2978 | } | ||
2979 | |||
2980 | /* | ||
2981 | * Data FIFO Write Address | ||
2982 | * Pointer to the next QWD location to be written to the data FIFO. | ||
2983 | */ | ||
2984 | register DFWADDR { | ||
2985 | address 0x0C0 | ||
2986 | access_mode RW | ||
2987 | size 2 | ||
2988 | modes M_DFF0, M_DFF1 | ||
2989 | } | ||
2990 | |||
2991 | /* | ||
2992 | * DSP Filter Control | ||
2993 | */ | ||
2994 | register DSPFLTRCTL { | ||
2995 | address 0x0C0 | ||
2996 | access_mode RW | ||
2997 | modes M_CFG | ||
2998 | field FLTRDISABLE 0x20 | ||
2999 | field EDGESENSE 0x10 | ||
3000 | field DSPFCNTSEL 0x0F | ||
3001 | } | ||
3002 | |||
3003 | /* | ||
3004 | * DSP Data Channel Control | ||
3005 | */ | ||
3006 | register DSPDATACTL { | ||
3007 | address 0x0C1 | ||
3008 | access_mode RW | ||
3009 | modes M_CFG | ||
3010 | field BYPASSENAB 0x80 | ||
3011 | field DESQDIS 0x10 | ||
3012 | field RCVROFFSTDIS 0x04 | ||
3013 | field XMITOFFSTDIS 0x02 | ||
3014 | } | ||
3015 | |||
3016 | /* | ||
3017 | * Data FIFO Read Address | ||
3018 | * Pointer to the next QWD location to be read from the data FIFO. | ||
3019 | */ | ||
3020 | register DFRADDR { | ||
3021 | address 0x0C2 | ||
3022 | access_mode RW | ||
3023 | size 2 | ||
3024 | modes M_DFF0, M_DFF1 | ||
3025 | } | ||
3026 | |||
3027 | /* | ||
3028 | * DSP REQ Control | ||
3029 | */ | ||
3030 | register DSPREQCTL { | ||
3031 | address 0x0C2 | ||
3032 | access_mode RW | ||
3033 | modes M_CFG | ||
3034 | field MANREQCTL 0xC0 | ||
3035 | field MANREQDLY 0x3F | ||
3036 | } | ||
3037 | |||
3038 | /* | ||
3039 | * DSP ACK Control | ||
3040 | */ | ||
3041 | register DSPACKCTL { | ||
3042 | address 0x0C3 | ||
3043 | access_mode RW | ||
3044 | modes M_CFG | ||
3045 | field MANACKCTL 0xC0 | ||
3046 | field MANACKDLY 0x3F | ||
3047 | } | ||
3048 | |||
3049 | /* | ||
3050 | * Data FIFO Data | ||
3051 | * Read/Write byte port into the data FIFO. The read and write | ||
3052 | * FIFO pointers increment with each read and write respectively | ||
3053 | * to this port. | ||
3054 | */ | ||
3055 | register DFDAT { | ||
3056 | address 0x0C4 | ||
3057 | access_mode RW | ||
3058 | modes M_DFF0, M_DFF1 | ||
3059 | } | ||
3060 | |||
3061 | /* | ||
3062 | * DSP Channel Select | ||
3063 | */ | ||
3064 | register DSPSELECT { | ||
3065 | address 0x0C4 | ||
3066 | access_mode RW | ||
3067 | modes M_CFG | ||
3068 | field AUTOINCEN 0x80 | ||
3069 | field DSPSEL 0x1F | ||
3070 | } | ||
3071 | |||
3072 | const NUMDSPS 0x14 | ||
3073 | |||
3074 | /* | ||
3075 | * Write Bias Control | ||
3076 | */ | ||
3077 | register WRTBIASCTL { | ||
3078 | address 0x0C5 | ||
3079 | access_mode WO | ||
3080 | modes M_CFG | ||
3081 | field AUTOXBCDIS 0x80 | ||
3082 | field XMITMANVAL 0x3F | ||
3083 | } | ||
3084 | |||
3085 | /* | ||
3086 | * Currently the WRTBIASCTL is the same as the default. | ||
3087 | */ | ||
3088 | const WRTBIASCTL_HP_DEFAULT 0x0 | ||
3089 | |||
3090 | /* | ||
3091 | * Receiver Bias Control | ||
3092 | */ | ||
3093 | register RCVRBIOSCTL { | ||
3094 | address 0x0C6 | ||
3095 | access_mode WO | ||
3096 | modes M_CFG | ||
3097 | field AUTORBCDIS 0x80 | ||
3098 | field RCVRMANVAL 0x3F | ||
3099 | } | ||
3100 | |||
3101 | /* | ||
3102 | * Write Bias Calculator | ||
3103 | */ | ||
3104 | register WRTBIASCALC { | ||
3105 | address 0x0C7 | ||
3106 | access_mode RO | ||
3107 | modes M_CFG | ||
3108 | } | ||
3109 | |||
3110 | /* | ||
3111 | * Data FIFO Pointers | ||
3112 | * Contains the byte offset from DFWADDR and DWRADDR to the current | ||
3113 | * FIFO write/read locations. | ||
3114 | */ | ||
3115 | register DFPTRS { | ||
3116 | address 0x0C8 | ||
3117 | access_mode RW | ||
3118 | modes M_DFF0, M_DFF1 | ||
3119 | } | ||
3120 | |||
3121 | /* | ||
3122 | * Receiver Bias Calculator | ||
3123 | */ | ||
3124 | register RCVRBIASCALC { | ||
3125 | address 0x0C8 | ||
3126 | access_mode RO | ||
3127 | modes M_CFG | ||
3128 | } | ||
3129 | |||
3130 | /* | ||
3131 | * Data FIFO Backup Read Pointer | ||
3132 | * Contains the data FIFO address to be restored if the last | ||
3133 | * data accessed from the data FIFO was not transferred successfully. | ||
3134 | */ | ||
3135 | register DFBKPTR { | ||
3136 | address 0x0C9 | ||
3137 | access_mode RW | ||
3138 | size 2 | ||
3139 | modes M_DFF0, M_DFF1 | ||
3140 | } | ||
3141 | |||
3142 | /* | ||
3143 | * Skew Calculator | ||
3144 | */ | ||
3145 | register SKEWCALC { | ||
3146 | address 0x0C9 | ||
3147 | access_mode RO | ||
3148 | modes M_CFG | ||
3149 | } | ||
3150 | |||
3151 | /* | ||
3152 | * Data FIFO Debug Control | ||
3153 | */ | ||
3154 | register DFDBCTL { | ||
3155 | address 0x0CB | ||
3156 | access_mode RW | ||
3157 | modes M_DFF0, M_DFF1 | ||
3158 | field DFF_CIO_WR_RDY 0x20 | ||
3159 | field DFF_CIO_RD_RDY 0x10 | ||
3160 | field DFF_DIR_ERR 0x08 | ||
3161 | field DFF_RAMBIST_FAIL 0x04 | ||
3162 | field DFF_RAMBIST_DONE 0x02 | ||
3163 | field DFF_RAMBIST_EN 0x01 | ||
3164 | } | ||
3165 | |||
3166 | /* | ||
3167 | * Data FIFO Space Count | ||
3168 | * Number of FIFO locations that are free. | ||
3169 | */ | ||
3170 | register DFSCNT { | ||
3171 | address 0x0CC | ||
3172 | access_mode RO | ||
3173 | size 2 | ||
3174 | modes M_DFF0, M_DFF1 | ||
3175 | } | ||
3176 | |||
3177 | /* | ||
3178 | * Data FIFO Byte Count | ||
3179 | * Number of filled FIFO locations. | ||
3180 | */ | ||
3181 | register DFBCNT { | ||
3182 | address 0x0CE | ||
3183 | access_mode RO | ||
3184 | size 2 | ||
3185 | modes M_DFF0, M_DFF1 | ||
3186 | } | ||
3187 | |||
3188 | /* | ||
3189 | * Sequencer Program Overlay Address. | ||
3190 | * Low address must be written prior to high address. | ||
3191 | */ | ||
3192 | register OVLYADDR { | ||
3193 | address 0x0D4 | ||
3194 | modes M_SCSI | ||
3195 | size 2 | ||
3196 | access_mode RW | ||
3197 | } | ||
3198 | |||
3199 | /* | ||
3200 | * Sequencer Control 0 | ||
3201 | * Error detection mode, speed configuration, | ||
3202 | * single step, breakpoints and program load. | ||
3203 | */ | ||
3204 | register SEQCTL0 { | ||
3205 | address 0x0D6 | ||
3206 | access_mode RW | ||
3207 | field PERRORDIS 0x80 | ||
3208 | field PAUSEDIS 0x40 | ||
3209 | field FAILDIS 0x20 | ||
3210 | field FASTMODE 0x10 | ||
3211 | field BRKADRINTEN 0x08 | ||
3212 | field STEP 0x04 | ||
3213 | field SEQRESET 0x02 | ||
3214 | field LOADRAM 0x01 | ||
3215 | } | ||
3216 | |||
3217 | /* | ||
3218 | * Sequencer Control 1 | ||
3219 | * Instruction RAM Diagnostics | ||
3220 | */ | ||
3221 | register SEQCTL1 { | ||
3222 | address 0x0D7 | ||
3223 | access_mode RW | ||
3224 | field OVRLAY_DATA_CHK 0x08 | ||
3225 | field RAMBIST_DONE 0x04 | ||
3226 | field RAMBIST_FAIL 0x02 | ||
3227 | field RAMBIST_EN 0x01 | ||
3228 | } | ||
3229 | |||
3230 | /* | ||
3231 | * Sequencer Flags | ||
3232 | * Zero and Carry state of the ALU. | ||
3233 | */ | ||
3234 | register FLAGS { | ||
3235 | address 0x0D8 | ||
3236 | access_mode RO | ||
3237 | field ZERO 0x02 | ||
3238 | field CARRY 0x01 | ||
3239 | } | ||
3240 | |||
3241 | /* | ||
3242 | * Sequencer Interrupt Control | ||
3243 | */ | ||
3244 | register SEQINTCTL { | ||
3245 | address 0x0D9 | ||
3246 | access_mode RW | ||
3247 | field INTVEC1DSL 0x80 | ||
3248 | field INT1_CONTEXT 0x20 | ||
3249 | field SCS_SEQ_INT1M1 0x10 | ||
3250 | field SCS_SEQ_INT1M0 0x08 | ||
3251 | field INTMASK2 0x04 | ||
3252 | field INTMASK1 0x02 | ||
3253 | field IRET 0x01 | ||
3254 | } | ||
3255 | |||
3256 | /* | ||
3257 | * Sequencer RAM Data Port | ||
3258 | * Single byte window into the Sequencer Instruction Ram area starting | ||
3259 | * at the address specified by OVLYADDR. To write a full instruction word, | ||
3260 | * simply write four bytes in succession. OVLYADDR will increment after the | ||
3261 | * most significant instrution byte (the byte with the parity bit) is written. | ||
3262 | */ | ||
3263 | register SEQRAM { | ||
3264 | address 0x0DA | ||
3265 | access_mode RW | ||
3266 | } | ||
3267 | |||
3268 | /* | ||
3269 | * Sequencer Program Counter | ||
3270 | * Low byte must be written prior to high byte. | ||
3271 | */ | ||
3272 | register PRGMCNT { | ||
3273 | address 0x0DE | ||
3274 | access_mode RW | ||
3275 | size 2 | ||
3276 | } | ||
3277 | |||
3278 | /* | ||
3279 | * Accumulator | ||
3280 | */ | ||
3281 | register ACCUM { | ||
3282 | address 0x0E0 | ||
3283 | access_mode RW | ||
3284 | accumulator | ||
3285 | } | ||
3286 | |||
3287 | /* | ||
3288 | * Source Index Register | ||
3289 | * Incrementing index for reads of SINDIR and the destination (low byte only) | ||
3290 | * for any immediate operands passed in jmp, jc, jnc, call instructions. | ||
3291 | * Example: | ||
3292 | * mvi 0xFF call some_routine; | ||
3293 | * | ||
3294 | * Will set SINDEX[0] to 0xFF and call the routine "some_routine. | ||
3295 | */ | ||
3296 | register SINDEX { | ||
3297 | address 0x0E2 | ||
3298 | access_mode RW | ||
3299 | size 2 | ||
3300 | sindex | ||
3301 | } | ||
3302 | |||
3303 | /* | ||
3304 | * Destination Index Register | ||
3305 | * Incrementing index for writes to DINDIR. Can be used as a scratch register. | ||
3306 | */ | ||
3307 | register DINDEX { | ||
3308 | address 0x0E4 | ||
3309 | access_mode RW | ||
3310 | size 2 | ||
3311 | } | ||
3312 | |||
3313 | /* | ||
3314 | * Break Address | ||
3315 | * Sequencer instruction breakpoint address address. | ||
3316 | */ | ||
3317 | register BRKADDR0 { | ||
3318 | address 0x0E6 | ||
3319 | access_mode RW | ||
3320 | } | ||
3321 | |||
3322 | register BRKADDR1 { | ||
3323 | address 0x0E6 | ||
3324 | access_mode RW | ||
3325 | field BRKDIS 0x80 /* Disable Breakpoint */ | ||
3326 | } | ||
3327 | |||
3328 | /* | ||
3329 | * All Ones | ||
3330 | * All reads to this register return the value 0xFF. | ||
3331 | */ | ||
3332 | register ALLONES { | ||
3333 | address 0x0E8 | ||
3334 | access_mode RO | ||
3335 | allones | ||
3336 | } | ||
3337 | |||
3338 | /* | ||
3339 | * All Zeros | ||
3340 | * All reads to this register return the value 0. | ||
3341 | */ | ||
3342 | register ALLZEROS { | ||
3343 | address 0x0EA | ||
3344 | access_mode RO | ||
3345 | allzeros | ||
3346 | } | ||
3347 | |||
3348 | /* | ||
3349 | * No Destination | ||
3350 | * Writes to this register have no effect. | ||
3351 | */ | ||
3352 | register NONE { | ||
3353 | address 0x0EA | ||
3354 | access_mode WO | ||
3355 | none | ||
3356 | } | ||
3357 | |||
3358 | /* | ||
3359 | * Source Index Indirect | ||
3360 | * Reading this register is equivalent to reading (register_base + SINDEX) and | ||
3361 | * incrementing SINDEX by 1. | ||
3362 | */ | ||
3363 | register SINDIR { | ||
3364 | address 0x0EC | ||
3365 | access_mode RO | ||
3366 | } | ||
3367 | |||
3368 | /* | ||
3369 | * Destination Index Indirect | ||
3370 | * Writing this register is equivalent to writing to (register_base + DINDEX) | ||
3371 | * and incrementing DINDEX by 1. | ||
3372 | */ | ||
3373 | register DINDIR { | ||
3374 | address 0x0ED | ||
3375 | access_mode WO | ||
3376 | } | ||
3377 | |||
3378 | /* | ||
3379 | * Function One | ||
3380 | * 2's complement to bit value conversion. Write the 2's complement value | ||
3381 | * (0-7 only) to the top nibble and retrieve the bit indexed by that value | ||
3382 | * on the next read of this register. | ||
3383 | * Example: | ||
3384 | * Write 0x60 | ||
3385 | * Read 0x40 | ||
3386 | */ | ||
3387 | register FUNCTION1 { | ||
3388 | address 0x0F0 | ||
3389 | access_mode RW | ||
3390 | } | ||
3391 | |||
3392 | /* | ||
3393 | * Stack | ||
3394 | * Window into the stack. Each stack location is 10 bits wide reported | ||
3395 | * low byte followed by high byte. There are 8 stack locations. | ||
3396 | */ | ||
3397 | register STACK { | ||
3398 | address 0x0F2 | ||
3399 | access_mode RW | ||
3400 | } | ||
3401 | |||
3402 | /* | ||
3403 | * Interrupt Vector 1 Address | ||
3404 | * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. | ||
3405 | */ | ||
3406 | register INTVEC1_ADDR { | ||
3407 | address 0x0F4 | ||
3408 | access_mode RW | ||
3409 | size 2 | ||
3410 | modes M_CFG | ||
3411 | } | ||
3412 | |||
3413 | /* | ||
3414 | * Current Address | ||
3415 | * Address of the SEQRAM instruction currently executing instruction. | ||
3416 | */ | ||
3417 | register CURADDR { | ||
3418 | address 0x0F4 | ||
3419 | access_mode RW | ||
3420 | size 2 | ||
3421 | modes M_SCSI | ||
3422 | } | ||
3423 | |||
3424 | /* | ||
3425 | * Interrupt Vector 2 Address | ||
3426 | * Interrupt branch address for HST_SEQ_INT2 interrupts. | ||
3427 | */ | ||
3428 | register INTVEC2_ADDR { | ||
3429 | address 0x0F6 | ||
3430 | access_mode RW | ||
3431 | size 2 | ||
3432 | modes M_CFG | ||
3433 | } | ||
3434 | |||
3435 | /* | ||
3436 | * Last Address | ||
3437 | * Address of the SEQRAM instruction executed prior to the current instruction. | ||
3438 | */ | ||
3439 | register LASTADDR { | ||
3440 | address 0x0F6 | ||
3441 | access_mode RW | ||
3442 | size 2 | ||
3443 | modes M_SCSI | ||
3444 | } | ||
3445 | |||
3446 | register AHD_PCI_CONFIG_BASE { | ||
3447 | address 0x100 | ||
3448 | access_mode RW | ||
3449 | size 256 | ||
3450 | modes M_CFG | ||
3451 | } | ||
3452 | |||
3453 | /* ---------------------- Scratch RAM Offsets ------------------------- */ | ||
3454 | scratch_ram { | ||
3455 | /* Mode Specific */ | ||
3456 | address 0x0A0 | ||
3457 | size 8 | ||
3458 | modes 0, 1, 2, 3 | ||
3459 | REG0 { | ||
3460 | size 2 | ||
3461 | } | ||
3462 | REG1 { | ||
3463 | size 2 | ||
3464 | } | ||
3465 | REG_ISR { | ||
3466 | size 2 | ||
3467 | } | ||
3468 | SG_STATE { | ||
3469 | size 1 | ||
3470 | field SEGS_AVAIL 0x01 | ||
3471 | field LOADING_NEEDED 0x02 | ||
3472 | field FETCH_INPROG 0x04 | ||
3473 | } | ||
3474 | /* | ||
3475 | * Track whether the transfer byte count for | ||
3476 | * the current data phase is odd. | ||
3477 | */ | ||
3478 | DATA_COUNT_ODD { | ||
3479 | size 1 | ||
3480 | } | ||
3481 | } | ||
3482 | |||
3483 | scratch_ram { | ||
3484 | /* Mode Specific */ | ||
3485 | address 0x0F8 | ||
3486 | size 8 | ||
3487 | modes 0, 1, 2, 3 | ||
3488 | LONGJMP_ADDR { | ||
3489 | size 2 | ||
3490 | } | ||
3491 | ACCUM_SAVE { | ||
3492 | size 1 | ||
3493 | } | ||
3494 | } | ||
3495 | |||
3496 | |||
3497 | scratch_ram { | ||
3498 | address 0x100 | ||
3499 | size 128 | ||
3500 | modes 0, 1, 2, 3 | ||
3501 | /* | ||
3502 | * Per "other-id" execution queues. We use an array of | ||
3503 | * tail pointers into lists of SCBs sorted by "other-id". | ||
3504 | * The execution head pointer threads the head SCBs for | ||
3505 | * each list. | ||
3506 | */ | ||
3507 | WAITING_SCB_TAILS { | ||
3508 | size 32 | ||
3509 | } | ||
3510 | WAITING_TID_HEAD { | ||
3511 | size 2 | ||
3512 | } | ||
3513 | WAITING_TID_TAIL { | ||
3514 | size 2 | ||
3515 | } | ||
3516 | /* | ||
3517 | * SCBID of the next SCB in the new SCB queue. | ||
3518 | */ | ||
3519 | NEXT_QUEUED_SCB_ADDR { | ||
3520 | size 4 | ||
3521 | } | ||
3522 | /* | ||
3523 | * head of list of SCBs that have | ||
3524 | * completed but have not been | ||
3525 | * put into the qoutfifo. | ||
3526 | */ | ||
3527 | COMPLETE_SCB_HEAD { | ||
3528 | size 2 | ||
3529 | } | ||
3530 | /* | ||
3531 | * The list of completed SCBs in | ||
3532 | * the active DMA. | ||
3533 | */ | ||
3534 | COMPLETE_SCB_DMAINPROG_HEAD { | ||
3535 | size 2 | ||
3536 | } | ||
3537 | /* | ||
3538 | * head of list of SCBs that have | ||
3539 | * completed but need to be uploaded | ||
3540 | * to the host prior to being completed. | ||
3541 | */ | ||
3542 | COMPLETE_DMA_SCB_HEAD { | ||
3543 | size 2 | ||
3544 | } | ||
3545 | /* Counting semaphore to prevent new select-outs */ | ||
3546 | QFREEZE_COUNT { | ||
3547 | size 2 | ||
3548 | } | ||
3549 | /* | ||
3550 | * Mode to restore on legacy idle loop exit. | ||
3551 | */ | ||
3552 | SAVED_MODE { | ||
3553 | size 1 | ||
3554 | } | ||
3555 | /* | ||
3556 | * Single byte buffer used to designate the type or message | ||
3557 | * to send to a target. | ||
3558 | */ | ||
3559 | MSG_OUT { | ||
3560 | size 1 | ||
3561 | } | ||
3562 | /* Parameters for DMA Logic */ | ||
3563 | DMAPARAMS { | ||
3564 | size 1 | ||
3565 | field PRELOADEN 0x80 | ||
3566 | field WIDEODD 0x40 | ||
3567 | field SCSIEN 0x20 | ||
3568 | field SDMAEN 0x10 | ||
3569 | field SDMAENACK 0x10 | ||
3570 | field HDMAEN 0x08 | ||
3571 | field HDMAENACK 0x08 | ||
3572 | field DIRECTION 0x04 /* Set indicates PCI->SCSI */ | ||
3573 | field FIFOFLUSH 0x02 | ||
3574 | field FIFORESET 0x01 | ||
3575 | } | ||
3576 | SEQ_FLAGS { | ||
3577 | size 1 | ||
3578 | field NOT_IDENTIFIED 0x80 | ||
3579 | field NO_CDB_SENT 0x40 | ||
3580 | field TARGET_CMD_IS_TAGGED 0x40 | ||
3581 | field DPHASE 0x20 | ||
3582 | /* Target flags */ | ||
3583 | field TARG_CMD_PENDING 0x10 | ||
3584 | field CMDPHASE_PENDING 0x08 | ||
3585 | field DPHASE_PENDING 0x04 | ||
3586 | field SPHASE_PENDING 0x02 | ||
3587 | field NO_DISCONNECT 0x01 | ||
3588 | } | ||
3589 | /* | ||
3590 | * Temporary storage for the | ||
3591 | * target/channel/lun of a | ||
3592 | * reconnecting target | ||
3593 | */ | ||
3594 | SAVED_SCSIID { | ||
3595 | size 1 | ||
3596 | } | ||
3597 | SAVED_LUN { | ||
3598 | size 1 | ||
3599 | } | ||
3600 | /* | ||
3601 | * The last bus phase as seen by the sequencer. | ||
3602 | */ | ||
3603 | LASTPHASE { | ||
3604 | size 1 | ||
3605 | field CDI 0x80 | ||
3606 | field IOI 0x40 | ||
3607 | field MSGI 0x20 | ||
3608 | field P_BUSFREE 0x01 | ||
3609 | enum PHASE_MASK CDO|IOO|MSGO { | ||
3610 | P_DATAOUT 0x0, | ||
3611 | P_DATAIN IOO, | ||
3612 | P_DATAOUT_DT P_DATAOUT|MSGO, | ||
3613 | P_DATAIN_DT P_DATAIN|MSGO, | ||
3614 | P_COMMAND CDO, | ||
3615 | P_MESGOUT CDO|MSGO, | ||
3616 | P_STATUS CDO|IOO, | ||
3617 | P_MESGIN CDO|IOO|MSGO | ||
3618 | } | ||
3619 | } | ||
3620 | /* | ||
3621 | * Value to "or" into the SCBPTR[1] value to | ||
3622 | * indicate that an entry in the QINFIFO is valid. | ||
3623 | */ | ||
3624 | QOUTFIFO_ENTRY_VALID_TAG { | ||
3625 | size 1 | ||
3626 | } | ||
3627 | /* | ||
3628 | * Base address of our shared data with the kernel driver in host | ||
3629 | * memory. This includes the qoutfifo and target mode | ||
3630 | * incoming command queue. | ||
3631 | */ | ||
3632 | SHARED_DATA_ADDR { | ||
3633 | size 4 | ||
3634 | } | ||
3635 | /* | ||
3636 | * Pointer to location in host memory for next | ||
3637 | * position in the qoutfifo. | ||
3638 | */ | ||
3639 | QOUTFIFO_NEXT_ADDR { | ||
3640 | size 4 | ||
3641 | } | ||
3642 | /* | ||
3643 | * Kernel and sequencer offsets into the queue of | ||
3644 | * incoming target mode command descriptors. The | ||
3645 | * queue is full when the KERNEL_TQINPOS == TQINPOS. | ||
3646 | */ | ||
3647 | KERNEL_TQINPOS { | ||
3648 | size 1 | ||
3649 | } | ||
3650 | TQINPOS { | ||
3651 | size 1 | ||
3652 | } | ||
3653 | ARG_1 { | ||
3654 | size 1 | ||
3655 | mask SEND_MSG 0x80 | ||
3656 | mask SEND_SENSE 0x40 | ||
3657 | mask SEND_REJ 0x20 | ||
3658 | mask MSGOUT_PHASEMIS 0x10 | ||
3659 | mask EXIT_MSG_LOOP 0x08 | ||
3660 | mask CONT_MSG_LOOP_WRITE 0x04 | ||
3661 | mask CONT_MSG_LOOP_READ 0x03 | ||
3662 | mask CONT_MSG_LOOP_TARG 0x02 | ||
3663 | alias RETURN_1 | ||
3664 | } | ||
3665 | ARG_2 { | ||
3666 | size 1 | ||
3667 | alias RETURN_2 | ||
3668 | } | ||
3669 | |||
3670 | /* | ||
3671 | * Snapshot of MSG_OUT taken after each message is sent. | ||
3672 | */ | ||
3673 | LAST_MSG { | ||
3674 | size 1 | ||
3675 | } | ||
3676 | |||
3677 | /* | ||
3678 | * Sequences the kernel driver has okayed for us. This allows | ||
3679 | * the driver to do things like prevent initiator or target | ||
3680 | * operations. | ||
3681 | */ | ||
3682 | SCSISEQ_TEMPLATE { | ||
3683 | size 1 | ||
3684 | field MANUALCTL 0x40 | ||
3685 | field ENSELI 0x20 | ||
3686 | field ENRSELI 0x10 | ||
3687 | field MANUALP 0x0C | ||
3688 | field ENAUTOATNP 0x02 | ||
3689 | field ALTSTIM 0x01 | ||
3690 | } | ||
3691 | |||
3692 | /* | ||
3693 | * The initiator specified tag for this target mode transaction. | ||
3694 | */ | ||
3695 | INITIATOR_TAG { | ||
3696 | size 1 | ||
3697 | } | ||
3698 | |||
3699 | SEQ_FLAGS2 { | ||
3700 | size 1 | ||
3701 | field TARGET_MSG_PENDING 0x02 | ||
3702 | field SELECTOUT_QFROZEN 0x04 | ||
3703 | } | ||
3704 | |||
3705 | ALLOCFIFO_SCBPTR { | ||
3706 | size 2 | ||
3707 | } | ||
3708 | |||
3709 | /* | ||
3710 | * The maximum amount of time to wait, when interrupt coalescing | ||
3711 | * is enabled, before issueing a CMDCMPLT interrupt for a completed | ||
3712 | * command. | ||
3713 | */ | ||
3714 | INT_COALESCING_TIMER { | ||
3715 | size 2 | ||
3716 | } | ||
3717 | |||
3718 | /* | ||
3719 | * The maximum number of commands to coalesce into a single interrupt. | ||
3720 | * Actually the 2's complement of that value to simplify sequencer | ||
3721 | * code. | ||
3722 | */ | ||
3723 | INT_COALESCING_MAXCMDS { | ||
3724 | size 1 | ||
3725 | } | ||
3726 | |||
3727 | /* | ||
3728 | * The minimum number of commands still outstanding required | ||
3729 | * to continue coalescing (2's complement of value). | ||
3730 | */ | ||
3731 | INT_COALESCING_MINCMDS { | ||
3732 | size 1 | ||
3733 | } | ||
3734 | |||
3735 | /* | ||
3736 | * Number of commands "in-flight". | ||
3737 | */ | ||
3738 | CMDS_PENDING { | ||
3739 | size 2 | ||
3740 | } | ||
3741 | |||
3742 | /* | ||
3743 | * The count of commands that have been coalesced. | ||
3744 | */ | ||
3745 | INT_COALESCING_CMDCOUNT { | ||
3746 | size 1 | ||
3747 | } | ||
3748 | |||
3749 | /* | ||
3750 | * Since the HS_MAIBOX is self clearing, copy its contents to | ||
3751 | * this position in scratch ram every time it changes. | ||
3752 | */ | ||
3753 | LOCAL_HS_MAILBOX { | ||
3754 | size 1 | ||
3755 | } | ||
3756 | /* | ||
3757 | * Target-mode CDB type to CDB length table used | ||
3758 | * in non-packetized operation. | ||
3759 | */ | ||
3760 | CMDSIZE_TABLE { | ||
3761 | size 8 | ||
3762 | } | ||
3763 | } | ||
3764 | |||
3765 | /************************* Hardware SCB Definition ****************************/ | ||
3766 | scb { | ||
3767 | address 0x180 | ||
3768 | size 64 | ||
3769 | modes 0, 1, 2, 3 | ||
3770 | SCB_RESIDUAL_DATACNT { | ||
3771 | size 4 | ||
3772 | alias SCB_CDB_STORE | ||
3773 | alias SCB_HOST_CDB_PTR | ||
3774 | } | ||
3775 | SCB_RESIDUAL_SGPTR { | ||
3776 | size 4 | ||
3777 | field SG_ADDR_MASK 0xf8 /* In the last byte */ | ||
3778 | field SG_OVERRUN_RESID 0x02 /* In the first byte */ | ||
3779 | field SG_LIST_NULL 0x01 /* In the first byte */ | ||
3780 | } | ||
3781 | SCB_SCSI_STATUS { | ||
3782 | size 1 | ||
3783 | alias SCB_HOST_CDB_LEN | ||
3784 | } | ||
3785 | SCB_TARGET_PHASES { | ||
3786 | size 1 | ||
3787 | } | ||
3788 | SCB_TARGET_DATA_DIR { | ||
3789 | size 1 | ||
3790 | } | ||
3791 | SCB_TARGET_ITAG { | ||
3792 | size 1 | ||
3793 | } | ||
3794 | SCB_SENSE_BUSADDR { | ||
3795 | /* | ||
3796 | * Only valid if CDB length is less than 13 bytes or | ||
3797 | * we are using a CDB pointer. Otherwise contains | ||
3798 | * the last 4 bytes of embedded cdb information. | ||
3799 | */ | ||
3800 | size 4 | ||
3801 | alias SCB_NEXT_COMPLETE | ||
3802 | } | ||
3803 | SCB_TAG { | ||
3804 | alias SCB_FIFO_USE_COUNT | ||
3805 | size 2 | ||
3806 | } | ||
3807 | SCB_CONTROL { | ||
3808 | size 1 | ||
3809 | field TARGET_SCB 0x80 | ||
3810 | field DISCENB 0x40 | ||
3811 | field TAG_ENB 0x20 | ||
3812 | field MK_MESSAGE 0x10 | ||
3813 | field STATUS_RCVD 0x08 | ||
3814 | field DISCONNECTED 0x04 | ||
3815 | field SCB_TAG_TYPE 0x03 | ||
3816 | } | ||
3817 | SCB_SCSIID { | ||
3818 | size 1 | ||
3819 | field TID 0xF0 | ||
3820 | field OID 0x0F | ||
3821 | } | ||
3822 | SCB_LUN { | ||
3823 | size 1 | ||
3824 | field LID 0xff | ||
3825 | } | ||
3826 | SCB_TASK_ATTRIBUTE { | ||
3827 | size 1 | ||
3828 | /* | ||
3829 | * Overloaded field for non-packetized | ||
3830 | * ignore wide residue message handling. | ||
3831 | */ | ||
3832 | field SCB_XFERLEN_ODD 0x01 | ||
3833 | } | ||
3834 | SCB_CDB_LEN { | ||
3835 | size 1 | ||
3836 | field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ | ||
3837 | } | ||
3838 | SCB_TASK_MANAGEMENT { | ||
3839 | size 1 | ||
3840 | } | ||
3841 | SCB_DATAPTR { | ||
3842 | size 8 | ||
3843 | } | ||
3844 | SCB_DATACNT { | ||
3845 | /* | ||
3846 | * The last byte is really the high address bits for | ||
3847 | * the data address. | ||
3848 | */ | ||
3849 | size 4 | ||
3850 | field SG_LAST_SEG 0x80 /* In the fourth byte */ | ||
3851 | field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ | ||
3852 | } | ||
3853 | SCB_SGPTR { | ||
3854 | size 4 | ||
3855 | field SG_STATUS_VALID 0x04 /* In the first byte */ | ||
3856 | field SG_FULL_RESID 0x02 /* In the first byte */ | ||
3857 | field SG_LIST_NULL 0x01 /* In the first byte */ | ||
3858 | } | ||
3859 | SCB_BUSADDR { | ||
3860 | size 4 | ||
3861 | } | ||
3862 | SCB_NEXT { | ||
3863 | alias SCB_NEXT_SCB_BUSADDR | ||
3864 | size 2 | ||
3865 | } | ||
3866 | SCB_NEXT2 { | ||
3867 | size 2 | ||
3868 | } | ||
3869 | SCB_SPARE { | ||
3870 | size 8 | ||
3871 | alias SCB_PKT_LUN | ||
3872 | } | ||
3873 | SCB_DISCONNECTED_LISTS { | ||
3874 | size 8 | ||
3875 | } | ||
3876 | } | ||
3877 | |||
3878 | /*********************************** Constants ********************************/ | ||
3879 | const MK_MESSAGE_BIT_OFFSET 4 | ||
3880 | const TID_SHIFT 4 | ||
3881 | const TARGET_CMD_CMPLT 0xfe | ||
3882 | const INVALID_ADDR 0x80 | ||
3883 | #define SCB_LIST_NULL 0xff | ||
3884 | #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 | ||
3885 | |||
3886 | const CCSGADDR_MAX 0x80 | ||
3887 | const CCSCBADDR_MAX 0x80 | ||
3888 | const CCSGRAM_MAXSEGS 16 | ||
3889 | |||
3890 | /* Selection Timeout Timer Constants */ | ||
3891 | const STIMESEL_SHIFT 3 | ||
3892 | const STIMESEL_MIN 0x18 | ||
3893 | const STIMESEL_BUG_ADJ 0x8 | ||
3894 | |||
3895 | /* WDTR Message values */ | ||
3896 | const BUS_8_BIT 0x00 | ||
3897 | const BUS_16_BIT 0x01 | ||
3898 | const BUS_32_BIT 0x02 | ||
3899 | |||
3900 | /* Offset maximums */ | ||
3901 | const MAX_OFFSET 0xfe | ||
3902 | const MAX_OFFSET_PACED 0xfe | ||
3903 | const MAX_OFFSET_PACED_BUG 0x7f | ||
3904 | /* | ||
3905 | * Some 160 devices incorrectly accept 0xfe as a | ||
3906 | * sync offset, but will overrun this value. Limit | ||
3907 | * to 0x7f for speed lower than U320 which will | ||
3908 | * avoid the persistent sync offset overruns. | ||
3909 | */ | ||
3910 | const MAX_OFFSET_NON_PACED 0x7f | ||
3911 | const HOST_MSG 0xff | ||
3912 | |||
3913 | /* | ||
3914 | * The size of our sense buffers. | ||
3915 | * Sense buffer mapping can be handled in either of two ways. | ||
3916 | * The first is to allocate a dmamap for each transaction. | ||
3917 | * Depending on the architecture, dmamaps can be costly. The | ||
3918 | * alternative is to statically map the buffers in much the same | ||
3919 | * way we handle our scatter gather lists. The driver implements | ||
3920 | * the later. | ||
3921 | */ | ||
3922 | const AHD_SENSE_BUFSIZE 256 | ||
3923 | |||
3924 | /* Target mode command processing constants */ | ||
3925 | const CMD_GROUP_CODE_SHIFT 0x05 | ||
3926 | |||
3927 | const STATUS_BUSY 0x08 | ||
3928 | const STATUS_QUEUE_FULL 0x28 | ||
3929 | const STATUS_PKT_SENSE 0xFF | ||
3930 | const TARGET_DATA_IN 1 | ||
3931 | |||
3932 | const SCB_TRANSFER_SIZE_FULL_LUN 56 | ||
3933 | const SCB_TRANSFER_SIZE_1BYTE_LUN 48 | ||
3934 | /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ | ||
3935 | const PKT_OVERRUN_BUFSIZE 512 | ||
3936 | |||
3937 | /* | ||
3938 | * Timer parameters. | ||
3939 | */ | ||
3940 | const AHD_TIMER_US_PER_TICK 25 | ||
3941 | const AHD_TIMER_MAX_TICKS 0xFFFF | ||
3942 | const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) | ||
3943 | |||
3944 | /* | ||
3945 | * Downloaded (kernel inserted) constants | ||
3946 | */ | ||
3947 | const SG_PREFETCH_CNT download | ||
3948 | const SG_PREFETCH_CNT_LIMIT download | ||
3949 | const SG_PREFETCH_ALIGN_MASK download | ||
3950 | const SG_PREFETCH_ADDR_MASK download | ||
3951 | const SG_SIZEOF download | ||
3952 | const PKT_OVERRUN_BUFOFFSET download | ||
3953 | const SCB_TRANSFER_SIZE download | ||
3954 | |||
3955 | /* | ||
3956 | * BIOS SCB offsets | ||
3957 | */ | ||
3958 | const NVRAM_SCB_OFFSET 0x2C | ||