diff options
author | Jeff Garzik <jgarzik@pobox.com> | 2005-11-18 11:44:17 -0500 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-11-18 11:44:17 -0500 |
commit | f333b3f111e9db76109e304df8ee777ace7fbf86 (patch) | |
tree | ce9a74a7327020c48c80d278e1db5f12552f0fb0 /drivers/scsi/ahci.c | |
parent | f4256e301d9800b1e0276404cb01b3ac85b51067 (diff) | |
parent | 79bfb0a98fdc73ed6a18469cef245cbf50a1d8bb (diff) |
Merge branch 'upstream'
Diffstat (limited to 'drivers/scsi/ahci.c')
-rw-r--r-- | drivers/scsi/ahci.c | 71 |
1 files changed, 57 insertions, 14 deletions
diff --git a/drivers/scsi/ahci.c b/drivers/scsi/ahci.c index 57ef7ae387d9..83467a05dc8e 100644 --- a/drivers/scsi/ahci.c +++ b/drivers/scsi/ahci.c | |||
@@ -48,7 +48,7 @@ | |||
48 | #include <asm/io.h> | 48 | #include <asm/io.h> |
49 | 49 | ||
50 | #define DRV_NAME "ahci" | 50 | #define DRV_NAME "ahci" |
51 | #define DRV_VERSION "1.01" | 51 | #define DRV_VERSION "1.2" |
52 | 52 | ||
53 | 53 | ||
54 | enum { | 54 | enum { |
@@ -134,6 +134,7 @@ enum { | |||
134 | PORT_IRQ_D2H_REG_FIS, | 134 | PORT_IRQ_D2H_REG_FIS, |
135 | 135 | ||
136 | /* PORT_CMD bits */ | 136 | /* PORT_CMD bits */ |
137 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ | ||
137 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ | 138 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
138 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | 139 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
139 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | 140 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
@@ -441,7 +442,7 @@ static void ahci_phy_reset(struct ata_port *ap) | |||
441 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | 442 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
442 | struct ata_taskfile tf; | 443 | struct ata_taskfile tf; |
443 | struct ata_device *dev = &ap->device[0]; | 444 | struct ata_device *dev = &ap->device[0]; |
444 | u32 tmp; | 445 | u32 new_tmp, tmp; |
445 | 446 | ||
446 | __sata_phy_reset(ap); | 447 | __sata_phy_reset(ap); |
447 | 448 | ||
@@ -455,8 +456,21 @@ static void ahci_phy_reset(struct ata_port *ap) | |||
455 | tf.nsect = (tmp) & 0xff; | 456 | tf.nsect = (tmp) & 0xff; |
456 | 457 | ||
457 | dev->class = ata_dev_classify(&tf); | 458 | dev->class = ata_dev_classify(&tf); |
458 | if (!ata_dev_present(dev)) | 459 | if (!ata_dev_present(dev)) { |
459 | ata_port_disable(ap); | 460 | ata_port_disable(ap); |
461 | return; | ||
462 | } | ||
463 | |||
464 | /* Make sure port's ATAPI bit is set appropriately */ | ||
465 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | ||
466 | if (dev->class == ATA_DEV_ATAPI) | ||
467 | new_tmp |= PORT_CMD_ATAPI; | ||
468 | else | ||
469 | new_tmp &= ~PORT_CMD_ATAPI; | ||
470 | if (new_tmp != tmp) { | ||
471 | writel(new_tmp, port_mmio + PORT_CMD); | ||
472 | readl(port_mmio + PORT_CMD); /* flush */ | ||
473 | } | ||
460 | } | 474 | } |
461 | 475 | ||
462 | static u8 ahci_check_status(struct ata_port *ap) | 476 | static u8 ahci_check_status(struct ata_port *ap) |
@@ -474,11 +488,12 @@ static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |||
474 | ata_tf_from_fis(d2h_fis, tf); | 488 | ata_tf_from_fis(d2h_fis, tf); |
475 | } | 489 | } |
476 | 490 | ||
477 | static void ahci_fill_sg(struct ata_queued_cmd *qc) | 491 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc) |
478 | { | 492 | { |
479 | struct ahci_port_priv *pp = qc->ap->private_data; | 493 | struct ahci_port_priv *pp = qc->ap->private_data; |
480 | struct scatterlist *sg; | 494 | struct scatterlist *sg; |
481 | struct ahci_sg *ahci_sg; | 495 | struct ahci_sg *ahci_sg; |
496 | unsigned int n_sg = 0; | ||
482 | 497 | ||
483 | VPRINTK("ENTER\n"); | 498 | VPRINTK("ENTER\n"); |
484 | 499 | ||
@@ -493,8 +508,12 @@ static void ahci_fill_sg(struct ata_queued_cmd *qc) | |||
493 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | 508 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
494 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | 509 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
495 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | 510 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
511 | |||
496 | ahci_sg++; | 512 | ahci_sg++; |
513 | n_sg++; | ||
497 | } | 514 | } |
515 | |||
516 | return n_sg; | ||
498 | } | 517 | } |
499 | 518 | ||
500 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | 519 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
@@ -503,13 +522,14 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) | |||
503 | struct ahci_port_priv *pp = ap->private_data; | 522 | struct ahci_port_priv *pp = ap->private_data; |
504 | u32 opts; | 523 | u32 opts; |
505 | const u32 cmd_fis_len = 5; /* five dwords */ | 524 | const u32 cmd_fis_len = 5; /* five dwords */ |
525 | unsigned int n_elem; | ||
506 | 526 | ||
507 | /* | 527 | /* |
508 | * Fill in command slot information (currently only one slot, | 528 | * Fill in command slot information (currently only one slot, |
509 | * slot 0, is currently since we don't do queueing) | 529 | * slot 0, is currently since we don't do queueing) |
510 | */ | 530 | */ |
511 | 531 | ||
512 | opts = (qc->n_elem << 16) | cmd_fis_len; | 532 | opts = cmd_fis_len; |
513 | if (qc->tf.flags & ATA_TFLAG_WRITE) | 533 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
514 | opts |= AHCI_CMD_WRITE; | 534 | opts |= AHCI_CMD_WRITE; |
515 | if (is_atapi_taskfile(&qc->tf)) | 535 | if (is_atapi_taskfile(&qc->tf)) |
@@ -533,16 +553,31 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) | |||
533 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | 553 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
534 | return; | 554 | return; |
535 | 555 | ||
536 | ahci_fill_sg(qc); | 556 | n_elem = ahci_fill_sg(qc); |
557 | |||
558 | pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16); | ||
537 | } | 559 | } |
538 | 560 | ||
539 | static void ahci_intr_error(struct ata_port *ap, u32 irq_stat) | 561 | static void ahci_restart_port(struct ata_port *ap, u32 irq_stat) |
540 | { | 562 | { |
541 | void __iomem *mmio = ap->host_set->mmio_base; | 563 | void __iomem *mmio = ap->host_set->mmio_base; |
542 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 564 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
543 | u32 tmp; | 565 | u32 tmp; |
544 | int work; | 566 | int work; |
545 | 567 | ||
568 | if ((ap->device[0].class != ATA_DEV_ATAPI) || | ||
569 | ((irq_stat & PORT_IRQ_TF_ERR) == 0)) | ||
570 | printk(KERN_WARNING "ata%u: port reset, " | ||
571 | "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n", | ||
572 | ap->id, | ||
573 | irq_stat, | ||
574 | readl(mmio + HOST_IRQ_STAT), | ||
575 | readl(port_mmio + PORT_IRQ_STAT), | ||
576 | readl(port_mmio + PORT_CMD), | ||
577 | readl(port_mmio + PORT_TFDATA), | ||
578 | readl(port_mmio + PORT_SCR_STAT), | ||
579 | readl(port_mmio + PORT_SCR_ERR)); | ||
580 | |||
546 | /* stop DMA */ | 581 | /* stop DMA */ |
547 | tmp = readl(port_mmio + PORT_CMD); | 582 | tmp = readl(port_mmio + PORT_CMD); |
548 | tmp &= ~PORT_CMD_START; | 583 | tmp &= ~PORT_CMD_START; |
@@ -580,8 +615,6 @@ static void ahci_intr_error(struct ata_port *ap, u32 irq_stat) | |||
580 | tmp |= PORT_CMD_START; | 615 | tmp |= PORT_CMD_START; |
581 | writel(tmp, port_mmio + PORT_CMD); | 616 | writel(tmp, port_mmio + PORT_CMD); |
582 | readl(port_mmio + PORT_CMD); /* flush */ | 617 | readl(port_mmio + PORT_CMD); /* flush */ |
583 | |||
584 | printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id); | ||
585 | } | 618 | } |
586 | 619 | ||
587 | static void ahci_eng_timeout(struct ata_port *ap) | 620 | static void ahci_eng_timeout(struct ata_port *ap) |
@@ -592,17 +625,17 @@ static void ahci_eng_timeout(struct ata_port *ap) | |||
592 | struct ata_queued_cmd *qc; | 625 | struct ata_queued_cmd *qc; |
593 | unsigned long flags; | 626 | unsigned long flags; |
594 | 627 | ||
595 | DPRINTK("ENTER\n"); | 628 | printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id); |
596 | 629 | ||
597 | spin_lock_irqsave(&host_set->lock, flags); | 630 | spin_lock_irqsave(&host_set->lock, flags); |
598 | 631 | ||
599 | ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT)); | ||
600 | |||
601 | qc = ata_qc_from_tag(ap, ap->active_tag); | 632 | qc = ata_qc_from_tag(ap, ap->active_tag); |
602 | if (!qc) { | 633 | if (!qc) { |
603 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | 634 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", |
604 | ap->id); | 635 | ap->id); |
605 | } else { | 636 | } else { |
637 | ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT)); | ||
638 | |||
606 | /* hack alert! We cannot use the supplied completion | 639 | /* hack alert! We cannot use the supplied completion |
607 | * function from inside the ->eh_strategy_handler() thread. | 640 | * function from inside the ->eh_strategy_handler() thread. |
608 | * libata is the only user of ->eh_strategy_handler() in | 641 | * libata is the only user of ->eh_strategy_handler() in |
@@ -637,9 +670,19 @@ static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc) | |||
637 | } | 670 | } |
638 | 671 | ||
639 | if (status & PORT_IRQ_FATAL) { | 672 | if (status & PORT_IRQ_FATAL) { |
640 | ahci_intr_error(ap, status); | 673 | unsigned int err_mask; |
674 | if (status & PORT_IRQ_TF_ERR) | ||
675 | err_mask = AC_ERR_DEV; | ||
676 | else if (status & PORT_IRQ_IF_ERR) | ||
677 | err_mask = AC_ERR_ATA_BUS; | ||
678 | else | ||
679 | err_mask = AC_ERR_HOST_BUS; | ||
680 | |||
681 | /* command processing has stopped due to error; restart */ | ||
682 | ahci_restart_port(ap, status); | ||
683 | |||
641 | if (qc) | 684 | if (qc) |
642 | ata_qc_complete(qc, AC_ERR_OTHER); | 685 | ata_qc_complete(qc, err_mask); |
643 | } | 686 | } |
644 | 687 | ||
645 | return 1; | 688 | return 1; |