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authorMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:43 -0400
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:43 -0400
commit94c12cc7d196bab34aaa98d38521549fa1e5ef76 (patch)
tree8e0cec0ed44445d74a2cb5160303d6b4dfb1bc31 /drivers/s390/cio/ioasm.h
parent25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc (diff)
[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'drivers/s390/cio/ioasm.h')
-rw-r--r--drivers/s390/cio/ioasm.h220
1 files changed, 81 insertions, 139 deletions
diff --git a/drivers/s390/cio/ioasm.h b/drivers/s390/cio/ioasm.h
index 95a9462f9a91..ad6d82940069 100644
--- a/drivers/s390/cio/ioasm.h
+++ b/drivers/s390/cio/ioasm.h
@@ -25,106 +25,74 @@ struct tpi_info {
25static inline int stsch(struct subchannel_id schid, 25static inline int stsch(struct subchannel_id schid,
26 volatile struct schib *addr) 26 volatile struct schib *addr)
27{ 27{
28 register struct subchannel_id reg1 asm ("1") = schid;
28 int ccode; 29 int ccode;
29 30
30 __asm__ __volatile__( 31 asm volatile(
31 " lr 1,%1\n" 32 " stsch 0(%2)\n"
32 " stsch 0(%2)\n" 33 " ipm %0\n"
33 " ipm %0\n" 34 " srl %0,28"
34 " srl %0,28" 35 : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
35 : "=d" (ccode)
36 : "d" (schid), "a" (addr), "m" (*addr)
37 : "cc", "1" );
38 return ccode; 36 return ccode;
39} 37}
40 38
41static inline int stsch_err(struct subchannel_id schid, 39static inline int stsch_err(struct subchannel_id schid,
42 volatile struct schib *addr) 40 volatile struct schib *addr)
43{ 41{
44 int ccode; 42 register struct subchannel_id reg1 asm ("1") = schid;
43 int ccode = -EIO;
45 44
46 __asm__ __volatile__( 45 asm volatile(
47 " lhi %0,%3\n" 46 " stsch 0(%2)\n"
48 " lr 1,%1\n" 47 "0: ipm %0\n"
49 " stsch 0(%2)\n" 48 " srl %0,28\n"
50 "0: ipm %0\n"
51 " srl %0,28\n"
52 "1:\n" 49 "1:\n"
53#ifdef CONFIG_64BIT 50 EX_TABLE(0b,1b)
54 ".section __ex_table,\"a\"\n" 51 : "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
55 " .align 8\n"
56 " .quad 0b,1b\n"
57 ".previous"
58#else
59 ".section __ex_table,\"a\"\n"
60 " .align 4\n"
61 " .long 0b,1b\n"
62 ".previous"
63#endif
64 : "=&d" (ccode)
65 : "d" (schid), "a" (addr), "K" (-EIO), "m" (*addr)
66 : "cc", "1" );
67 return ccode; 52 return ccode;
68} 53}
69 54
70static inline int msch(struct subchannel_id schid, 55static inline int msch(struct subchannel_id schid,
71 volatile struct schib *addr) 56 volatile struct schib *addr)
72{ 57{
58 register struct subchannel_id reg1 asm ("1") = schid;
73 int ccode; 59 int ccode;
74 60
75 __asm__ __volatile__( 61 asm volatile(
76 " lr 1,%1\n" 62 " msch 0(%2)\n"
77 " msch 0(%2)\n" 63 " ipm %0\n"
78 " ipm %0\n" 64 " srl %0,28"
79 " srl %0,28" 65 : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
80 : "=d" (ccode)
81 : "d" (schid), "a" (addr), "m" (*addr)
82 : "cc", "1" );
83 return ccode; 66 return ccode;
84} 67}
85 68
86static inline int msch_err(struct subchannel_id schid, 69static inline int msch_err(struct subchannel_id schid,
87 volatile struct schib *addr) 70 volatile struct schib *addr)
88{ 71{
89 int ccode; 72 register struct subchannel_id reg1 asm ("1") = schid;
73 int ccode = -EIO;
90 74
91 __asm__ __volatile__( 75 asm volatile(
92 " lhi %0,%3\n" 76 " msch 0(%2)\n"
93 " lr 1,%1\n" 77 "0: ipm %0\n"
94 " msch 0(%2)\n" 78 " srl %0,28\n"
95 "0: ipm %0\n"
96 " srl %0,28\n"
97 "1:\n" 79 "1:\n"
98#ifdef CONFIG_64BIT 80 EX_TABLE(0b,1b)
99 ".section __ex_table,\"a\"\n" 81 : "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
100 " .align 8\n"
101 " .quad 0b,1b\n"
102 ".previous"
103#else
104 ".section __ex_table,\"a\"\n"
105 " .align 4\n"
106 " .long 0b,1b\n"
107 ".previous"
108#endif
109 : "=&d" (ccode)
110 : "d" (schid), "a" (addr), "K" (-EIO), "m" (*addr)
111 : "cc", "1" );
112 return ccode; 82 return ccode;
113} 83}
114 84
115static inline int tsch(struct subchannel_id schid, 85static inline int tsch(struct subchannel_id schid,
116 volatile struct irb *addr) 86 volatile struct irb *addr)
117{ 87{
88 register struct subchannel_id reg1 asm ("1") = schid;
118 int ccode; 89 int ccode;
119 90
120 __asm__ __volatile__( 91 asm volatile(
121 " lr 1,%1\n" 92 " tsch 0(%2)\n"
122 " tsch 0(%2)\n" 93 " ipm %0\n"
123 " ipm %0\n" 94 " srl %0,28"
124 " srl %0,28" 95 : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
125 : "=d" (ccode)
126 : "d" (schid), "a" (addr), "m" (*addr)
127 : "cc", "1" );
128 return ccode; 96 return ccode;
129} 97}
130 98
@@ -132,89 +100,77 @@ static inline int tpi( volatile struct tpi_info *addr)
132{ 100{
133 int ccode; 101 int ccode;
134 102
135 __asm__ __volatile__( 103 asm volatile(
136 " tpi 0(%1)\n" 104 " tpi 0(%1)\n"
137 " ipm %0\n" 105 " ipm %0\n"
138 " srl %0,28" 106 " srl %0,28"
139 : "=d" (ccode) 107 : "=d" (ccode) : "a" (addr), "m" (*addr) : "cc");
140 : "a" (addr), "m" (*addr)
141 : "cc", "1" );
142 return ccode; 108 return ccode;
143} 109}
144 110
145static inline int ssch(struct subchannel_id schid, 111static inline int ssch(struct subchannel_id schid,
146 volatile struct orb *addr) 112 volatile struct orb *addr)
147{ 113{
114 register struct subchannel_id reg1 asm ("1") = schid;
148 int ccode; 115 int ccode;
149 116
150 __asm__ __volatile__( 117 asm volatile(
151 " lr 1,%1\n" 118 " ssch 0(%2)\n"
152 " ssch 0(%2)\n" 119 " ipm %0\n"
153 " ipm %0\n" 120 " srl %0,28"
154 " srl %0,28" 121 : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
155 : "=d" (ccode)
156 : "d" (schid), "a" (addr), "m" (*addr)
157 : "cc", "1" );
158 return ccode; 122 return ccode;
159} 123}
160 124
161static inline int rsch(struct subchannel_id schid) 125static inline int rsch(struct subchannel_id schid)
162{ 126{
127 register struct subchannel_id reg1 asm ("1") = schid;
163 int ccode; 128 int ccode;
164 129
165 __asm__ __volatile__( 130 asm volatile(
166 " lr 1,%1\n" 131 " rsch\n"
167 " rsch\n" 132 " ipm %0\n"
168 " ipm %0\n" 133 " srl %0,28"
169 " srl %0,28" 134 : "=d" (ccode) : "d" (reg1) : "cc");
170 : "=d" (ccode)
171 : "d" (schid)
172 : "cc", "1" );
173 return ccode; 135 return ccode;
174} 136}
175 137
176static inline int csch(struct subchannel_id schid) 138static inline int csch(struct subchannel_id schid)
177{ 139{
140 register struct subchannel_id reg1 asm ("1") = schid;
178 int ccode; 141 int ccode;
179 142
180 __asm__ __volatile__( 143 asm volatile(
181 " lr 1,%1\n" 144 " csch\n"
182 " csch\n" 145 " ipm %0\n"
183 " ipm %0\n" 146 " srl %0,28"
184 " srl %0,28" 147 : "=d" (ccode) : "d" (reg1) : "cc");
185 : "=d" (ccode)
186 : "d" (schid)
187 : "cc", "1" );
188 return ccode; 148 return ccode;
189} 149}
190 150
191static inline int hsch(struct subchannel_id schid) 151static inline int hsch(struct subchannel_id schid)
192{ 152{
153 register struct subchannel_id reg1 asm ("1") = schid;
193 int ccode; 154 int ccode;
194 155
195 __asm__ __volatile__( 156 asm volatile(
196 " lr 1,%1\n" 157 " hsch\n"
197 " hsch\n" 158 " ipm %0\n"
198 " ipm %0\n" 159 " srl %0,28"
199 " srl %0,28" 160 : "=d" (ccode) : "d" (reg1) : "cc");
200 : "=d" (ccode)
201 : "d" (schid)
202 : "cc", "1" );
203 return ccode; 161 return ccode;
204} 162}
205 163
206static inline int xsch(struct subchannel_id schid) 164static inline int xsch(struct subchannel_id schid)
207{ 165{
166 register struct subchannel_id reg1 asm ("1") = schid;
208 int ccode; 167 int ccode;
209 168
210 __asm__ __volatile__( 169 asm volatile(
211 " lr 1,%1\n" 170 " .insn rre,0xb2760000,%1,0\n"
212 " .insn rre,0xb2760000,%1,0\n" 171 " ipm %0\n"
213 " ipm %0\n" 172 " srl %0,28"
214 " srl %0,28" 173 : "=d" (ccode) : "d" (reg1) : "cc");
215 : "=d" (ccode)
216 : "d" (schid)
217 : "cc", "1" );
218 return ccode; 174 return ccode;
219} 175}
220 176
@@ -223,41 +179,27 @@ static inline int chsc(void *chsc_area)
223 typedef struct { char _[4096]; } addr_type; 179 typedef struct { char _[4096]; } addr_type;
224 int cc; 180 int cc;
225 181
226 __asm__ __volatile__ ( 182 asm volatile(
227 ".insn rre,0xb25f0000,%2,0 \n\t" 183 " .insn rre,0xb25f0000,%2,0\n"
228 "ipm %0 \n\t" 184 " ipm %0\n"
229 "srl %0,28 \n\t" 185 " srl %0,28\n"
230 : "=d" (cc), "=m" (*(addr_type *) chsc_area) 186 : "=d" (cc), "=m" (*(addr_type *) chsc_area)
231 : "d" (chsc_area), "m" (*(addr_type *) chsc_area) 187 : "d" (chsc_area), "m" (*(addr_type *) chsc_area)
232 : "cc" ); 188 : "cc");
233
234 return cc; 189 return cc;
235} 190}
236 191
237static inline int iac( void)
238{
239 int ccode;
240
241 __asm__ __volatile__(
242 " iac 1\n"
243 " ipm %0\n"
244 " srl %0,28"
245 : "=d" (ccode) : : "cc", "1" );
246 return ccode;
247}
248
249static inline int rchp(int chpid) 192static inline int rchp(int chpid)
250{ 193{
194 register unsigned int reg1 asm ("1") = chpid;
251 int ccode; 195 int ccode;
252 196
253 __asm__ __volatile__( 197 asm volatile(
254 " lr 1,%1\n" 198 " lr 1,%1\n"
255 " rchp\n" 199 " rchp\n"
256 " ipm %0\n" 200 " ipm %0\n"
257 " srl %0,28" 201 " srl %0,28"
258 : "=d" (ccode) 202 : "=d" (ccode) : "d" (reg1) : "cc");
259 : "d" (chpid)
260 : "cc", "1" );
261 return ccode; 203 return ccode;
262} 204}
263 205
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