aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/rtc
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-28 15:06:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-28 15:06:51 -0400
commit3c3762957818dc902222733a8184f23102e24472 (patch)
tree97a17d0923d87108715af32f83a526d24e65fb80 /drivers/rtc
parente9f29c9a56ca06d0effa557823a737cbe7ec09f7 (diff)
parent63111a3a70fb4d80e3b54ed75f13795e98f7a467 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (32 commits) sh: intc: switch irq_desc iteration to new active IRQ iterator. sh: fix up cpu hotplug IRQ migration for irq_data changes. sh: oprofile: Make sure the backtrace op is available for timer-fallback. sh64: oprofile: Fix up kernel stack pointer size mismatch. sh: oprofile: Fix up and extend op_name_from_perf_id(). sh: lockless get_user_pages_fast() sh64: _PAGE_SPECIAL support. sound: sh: ctrl_in/outX to __raw_read/writeX conversion. sh: disable deprecated genirq support. sh: update show_interrupts() for irq_data chip lookup. sh: intc: irq_data conversion. sh64: irq_data conversion. sh64: update for IRQ flag handling naming changes. rtc: rtc-rs5c313: ctrl_in/outX to __raw_read/writeX conversion. sh: mach-se: irq_data conversion. input: hp680_ts_input: ctrl_in/outX to __raw_read/writeX conversion. input: jornada680_kbd: ctrl_in/outX to __raw_read/writeX conversion. sh: hd64461: irq_data conversion. sh: mach-x3proto: irq_data conversion. sh: mach-systemh: irq_data conversion. ...
Diffstat (limited to 'drivers/rtc')
-rw-r--r--drivers/rtc/rtc-rs5c313.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/drivers/rtc/rtc-rs5c313.c b/drivers/rtc/rtc-rs5c313.c
index e6ea3f5ee1eb..e3ff179b99ca 100644
--- a/drivers/rtc/rtc-rs5c313.c
+++ b/drivers/rtc/rtc-rs5c313.c
@@ -80,21 +80,21 @@
80/* SCSPTR1 data */ 80/* SCSPTR1 data */
81unsigned char scsptr1_data; 81unsigned char scsptr1_data;
82 82
83#define RS5C313_CEENABLE ctrl_outb(RS5C313_CE_RTCCE, RS5C313_CE); 83#define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
84#define RS5C313_CEDISABLE ctrl_outb(0x00, RS5C313_CE) 84#define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE)
85#define RS5C313_MISCOP ctrl_outb(0x02, 0xB0000008) 85#define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008)
86 86
87static void rs5c313_init_port(void) 87static void rs5c313_init_port(void)
88{ 88{
89 /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */ 89 /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
90 ctrl_outb(ctrl_inb(SCSMR1) & ~SCSMR1_CA, SCSMR1); 90 __raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
91 ctrl_outb(ctrl_inb(SCSCR1) & ~SCSCR1_CKE, SCSCR1); 91 __raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
92 92
93 /* And Initialize SCL for RS5C313 clock */ 93 /* And Initialize SCL for RS5C313 clock */
94 scsptr1_data = ctrl_inb(SCSPTR1) | SCL; /* SCL:H */ 94 scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */
95 ctrl_outb(scsptr1_data, SCSPTR1); 95 __raw_writeb(scsptr1_data, SCSPTR1);
96 scsptr1_data = ctrl_inb(SCSPTR1) | SCL_OEN; /* SCL output enable */ 96 scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */
97 ctrl_outb(scsptr1_data, SCSPTR1); 97 __raw_writeb(scsptr1_data, SCSPTR1);
98 RS5C313_CEDISABLE; /* CE:L */ 98 RS5C313_CEDISABLE; /* CE:L */
99} 99}
100 100
@@ -106,21 +106,21 @@ static void rs5c313_write_data(unsigned char data)
106 /* SDA:Write Data */ 106 /* SDA:Write Data */
107 scsptr1_data = (scsptr1_data & ~SDA) | 107 scsptr1_data = (scsptr1_data & ~SDA) |
108 ((((0x80 >> i) & data) >> (7 - i)) << 2); 108 ((((0x80 >> i) & data) >> (7 - i)) << 2);
109 ctrl_outb(scsptr1_data, SCSPTR1); 109 __raw_writeb(scsptr1_data, SCSPTR1);
110 if (i == 0) { 110 if (i == 0) {
111 scsptr1_data |= SDA_OEN; /* SDA:output enable */ 111 scsptr1_data |= SDA_OEN; /* SDA:output enable */
112 ctrl_outb(scsptr1_data, SCSPTR1); 112 __raw_writeb(scsptr1_data, SCSPTR1);
113 } 113 }
114 ndelay(700); 114 ndelay(700);
115 scsptr1_data &= ~SCL; /* SCL:L */ 115 scsptr1_data &= ~SCL; /* SCL:L */
116 ctrl_outb(scsptr1_data, SCSPTR1); 116 __raw_writeb(scsptr1_data, SCSPTR1);
117 ndelay(700); 117 ndelay(700);
118 scsptr1_data |= SCL; /* SCL:H */ 118 scsptr1_data |= SCL; /* SCL:H */
119 ctrl_outb(scsptr1_data, SCSPTR1); 119 __raw_writeb(scsptr1_data, SCSPTR1);
120 } 120 }
121 121
122 scsptr1_data &= ~SDA_OEN; /* SDA:output disable */ 122 scsptr1_data &= ~SDA_OEN; /* SDA:output disable */
123 ctrl_outb(scsptr1_data, SCSPTR1); 123 __raw_writeb(scsptr1_data, SCSPTR1);
124} 124}
125 125
126static unsigned char rs5c313_read_data(void) 126static unsigned char rs5c313_read_data(void)
@@ -131,12 +131,12 @@ static unsigned char rs5c313_read_data(void)
131 for (i = 0; i < 8; i++) { 131 for (i = 0; i < 8; i++) {
132 ndelay(700); 132 ndelay(700);
133 /* SDA:Read Data */ 133 /* SDA:Read Data */
134 data |= ((ctrl_inb(SCSPTR1) & SDA) >> 2) << (7 - i); 134 data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
135 scsptr1_data &= ~SCL; /* SCL:L */ 135 scsptr1_data &= ~SCL; /* SCL:L */
136 ctrl_outb(scsptr1_data, SCSPTR1); 136 __raw_writeb(scsptr1_data, SCSPTR1);
137 ndelay(700); 137 ndelay(700);
138 scsptr1_data |= SCL; /* SCL:H */ 138 scsptr1_data |= SCL; /* SCL:H */
139 ctrl_outb(scsptr1_data, SCSPTR1); 139 __raw_writeb(scsptr1_data, SCSPTR1);
140 } 140 }
141 return data & 0x0F; 141 return data & 0x0F;
142} 142}