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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-09-24 04:07:43 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2013-11-22 15:20:36 -0500
commit8f1ae77f466660b6da2455cccecc07ae631fa66d (patch)
tree72bb8bfd609c1e5bde3118fc75a3d478baee8d00 /drivers/reset
parent6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff)
reset: Add Allwinner SoCs Reset Controller Driver
The Allwinner A31 and most of the other Allwinner SoCs have an IP maintaining a few other IPs in the SoC in reset by default. Among these IPs are the A31's High Speed Timers, hence why we can't use the regular driver construct in every cases, and need to call the registering function directly during machine initialisation. Apart from this, the implementation is fairly straightforward, and could easily be moved to a generic MMIO-based reset controller driver if the need ever arise. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/reset')
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-sunxi.c175
2 files changed, 176 insertions, 0 deletions
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f2b995..cc29832c9638 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,2 @@
1obj-$(CONFIG_RESET_CONTROLLER) += core.o 1obj-$(CONFIG_RESET_CONTROLLER) += core.o
2obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
new file mode 100644
index 000000000000..695bd3496eba
--- /dev/null
+++ b/drivers/reset/reset-sunxi.c
@@ -0,0 +1,175 @@
1/*
2 * Allwinner SoCs Reset Controller driver
3 *
4 * Copyright 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/reset-controller.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/types.h>
24
25struct sunxi_reset_data {
26 spinlock_t lock;
27 void __iomem *membase;
28 struct reset_controller_dev rcdev;
29};
30
31static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
32 unsigned long id)
33{
34 struct sunxi_reset_data *data = container_of(rcdev,
35 struct sunxi_reset_data,
36 rcdev);
37 int bank = id / BITS_PER_LONG;
38 int offset = id % BITS_PER_LONG;
39 unsigned long flags;
40 u32 reg;
41
42 spin_lock_irqsave(&data->lock, flags);
43
44 reg = readl(data->membase + (bank * 4));
45 writel(reg & ~BIT(offset), data->membase + (bank * 4));
46
47 spin_unlock_irqrestore(&data->lock, flags);
48
49 return 0;
50}
51
52static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
53 unsigned long id)
54{
55 struct sunxi_reset_data *data = container_of(rcdev,
56 struct sunxi_reset_data,
57 rcdev);
58 int bank = id / BITS_PER_LONG;
59 int offset = id % BITS_PER_LONG;
60 unsigned long flags;
61 u32 reg;
62
63 spin_lock_irqsave(&data->lock, flags);
64
65 reg = readl(data->membase + (bank * 4));
66 writel(reg | BIT(offset), data->membase + (bank * 4));
67
68 spin_unlock_irqrestore(&data->lock, flags);
69
70 return 0;
71}
72
73static struct reset_control_ops sunxi_reset_ops = {
74 .assert = sunxi_reset_assert,
75 .deassert = sunxi_reset_deassert,
76};
77
78static int sunxi_reset_init(struct device_node *np)
79{
80 struct sunxi_reset_data *data;
81 struct resource res;
82 resource_size_t size;
83 int ret;
84
85 data = kzalloc(sizeof(*data), GFP_KERNEL);
86 if (!data)
87 return -ENOMEM;
88
89 ret = of_address_to_resource(np, 0, &res);
90 if (ret)
91 goto err_alloc;
92
93 size = resource_size(&res);
94 if (!request_mem_region(res.start, size, np->name)) {
95 ret = -EBUSY;
96 goto err_alloc;
97 }
98
99 data->membase = ioremap(res.start, size);
100 if (!data->membase) {
101 ret = -ENOMEM;
102 goto err_alloc;
103 }
104
105 data->rcdev.owner = THIS_MODULE;
106 data->rcdev.nr_resets = size * 32;
107 data->rcdev.ops = &sunxi_reset_ops;
108 data->rcdev.of_node = np;
109 reset_controller_register(&data->rcdev);
110
111 return 0;
112
113err_alloc:
114 kfree(data);
115 return ret;
116};
117
118/*
119 * These are the reset controller we need to initialize early on in
120 * our system, before we can even think of using a regular device
121 * driver for it.
122 */
123static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
124 { .compatible = "allwinner,sun6i-a31-ahb1-reset", },
125 { /* sentinel */ },
126};
127
128void __init sun6i_reset_init(void)
129{
130 struct device_node *np;
131
132 for_each_matching_node(np, sunxi_early_reset_dt_ids)
133 sunxi_reset_init(np);
134}
135
136/*
137 * And these are the controllers we can register through the regular
138 * device model.
139 */
140static const struct of_device_id sunxi_reset_dt_ids[] = {
141 { .compatible = "allwinner,sun6i-a31-clock-reset", },
142 { /* sentinel */ },
143};
144MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
145
146static int sunxi_reset_probe(struct platform_device *pdev)
147{
148 return sunxi_reset_init(pdev->dev.of_node);
149}
150
151static int sunxi_reset_remove(struct platform_device *pdev)
152{
153 struct sunxi_reset_data *data = platform_get_drvdata(pdev);
154
155 reset_controller_unregister(&data->rcdev);
156 iounmap(data->membase);
157 kfree(data);
158
159 return 0;
160}
161
162static struct platform_driver sunxi_reset_driver = {
163 .probe = sunxi_reset_probe,
164 .remove = sunxi_reset_remove,
165 .driver = {
166 .name = "sunxi-reset",
167 .owner = THIS_MODULE,
168 .of_match_table = sunxi_reset_dt_ids,
169 },
170};
171module_platform_driver(sunxi_reset_driver);
172
173MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
174MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
175MODULE_LICENSE("GPL");