diff options
author | Philip, Avinash <avinashphilip@ti.com> | 2012-09-06 01:10:02 -0400 |
---|---|---|
committer | Thierry Reding <thierry.reding@avionic-design.de> | 2012-09-10 11:05:52 -0400 |
commit | 454870a44b0687675180506b7774fb559d610675 (patch) | |
tree | 4ce95213a641f5911350a1a085e5fc1cee9c477b /drivers/pwm | |
parent | 6354316dbe5a13b25bea15d7ffc891be025eb267 (diff) |
pwm: pwm-tiecap: Add support for configuring polarity of PWM
ECAP APWM hardware supports polarity configuration of PWM output.
This commit adds support for polarity configuration of ECAP APWM.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Diffstat (limited to 'drivers/pwm')
-rw-r--r-- | drivers/pwm/pwm-tiecap.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c index 4b6688909fee..081471fbb097 100644 --- a/drivers/pwm/pwm-tiecap.c +++ b/drivers/pwm/pwm-tiecap.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #define CAP3 0x10 | 32 | #define CAP3 0x10 |
33 | #define CAP4 0x14 | 33 | #define CAP4 0x14 |
34 | #define ECCTL2 0x2A | 34 | #define ECCTL2 0x2A |
35 | #define ECCTL2_APWM_POL_LOW BIT(10) | ||
35 | #define ECCTL2_APWM_MODE BIT(9) | 36 | #define ECCTL2_APWM_MODE BIT(9) |
36 | #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) | 37 | #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) |
37 | #define ECCTL2_TSCTR_FREERUN BIT(4) | 38 | #define ECCTL2_TSCTR_FREERUN BIT(4) |
@@ -111,6 +112,26 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |||
111 | return 0; | 112 | return 0; |
112 | } | 113 | } |
113 | 114 | ||
115 | static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, | ||
116 | enum pwm_polarity polarity) | ||
117 | { | ||
118 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); | ||
119 | unsigned short reg_val; | ||
120 | |||
121 | pm_runtime_get_sync(pc->chip.dev); | ||
122 | reg_val = readw(pc->mmio_base + ECCTL2); | ||
123 | if (polarity == PWM_POLARITY_INVERSED) | ||
124 | /* Duty cycle defines LOW period of PWM */ | ||
125 | reg_val |= ECCTL2_APWM_POL_LOW; | ||
126 | else | ||
127 | /* Duty cycle defines HIGH period of PWM */ | ||
128 | reg_val &= ~ECCTL2_APWM_POL_LOW; | ||
129 | |||
130 | writew(reg_val, pc->mmio_base + ECCTL2); | ||
131 | pm_runtime_put_sync(pc->chip.dev); | ||
132 | return 0; | ||
133 | } | ||
134 | |||
114 | static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | 135 | static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
115 | { | 136 | { |
116 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); | 137 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); |
@@ -157,6 +178,7 @@ static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |||
157 | static const struct pwm_ops ecap_pwm_ops = { | 178 | static const struct pwm_ops ecap_pwm_ops = { |
158 | .free = ecap_pwm_free, | 179 | .free = ecap_pwm_free, |
159 | .config = ecap_pwm_config, | 180 | .config = ecap_pwm_config, |
181 | .set_polarity = ecap_pwm_set_polarity, | ||
160 | .enable = ecap_pwm_enable, | 182 | .enable = ecap_pwm_enable, |
161 | .disable = ecap_pwm_disable, | 183 | .disable = ecap_pwm_disable, |
162 | .owner = THIS_MODULE, | 184 | .owner = THIS_MODULE, |